CEN. Binary Counter CLR CLK EN ADDRESS REGISTER 18/19. Byte 1 Write Register. Byte 2. Write Register. Byte 3. Write Register.

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1 56K X 36 51K X V Synchronous SRAMs 3.3V I/O Burst Counter Flow-Through Outputs Single Cycle Deselect IDT71V67703 IDT71V67903 Features 56K x 36 51K x 18 memory configuratio Supports fast access times: 7.5 up to 117MHz clock frequency 8.0 up to 100MHz clock frequency 8.5 up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW) byte write enable (BWE) and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply () Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP) 119 ball grid array (BGA) and 165 fine pitch ball grid array (fbga) Green parts available see ordering information Functional Block Diagram LBO ADV CLK ADSC CEN Binary Counter CLR Burst Sequence Burst Logic Q0 Q1 A0* A1* INTERNAL ADDRESS 18/19 56K x 36/ 51K x 18- BIT MEMORY ARRAY A0 A17/18 GW BWE BW1 BW BW3 BW4 CLK EN ADDRESS REGISTER Byte 1 Write Register Byte Write Register Byte 3 Write Register Byte 4 Write Register 18/19 A0A1 A-A Byte 1 Write Driver Byte Write Driver Byte 3 Write Driver Byte 4 Write Driver 36/18 36/18 CE CS0 CS1 D Q Enable Register CLK EN DATA INPUT REGISTER ZZ Powerdown OE I/O0 I/O31 I/OP1 I/OP4 36/18 OE OUTPUT BUFFER 5309 drw 01 DECEMBER Integrated Device Technology Inc. 1 DSC-5309/06

2 Description The IDT71V67703/7903 are high-speed SRAMs organized as 56K x 36/51K x 18. The IDT71V67703/7903 SRAMs contain write data address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer as the IDT71V67703/7903 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor initiating the access sequence. The first cycle of output data will flowthrough from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected (ADV=LOW) the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V67703/7903 SRAMs utilize IDT s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 0mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fbga). Pin Description Summary A0-A18 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0 CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE Byte Write Enable Input Synchronous (1) BW1 BW BW3 BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous Address Status (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0-I/O31 I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD Core Power I/O Power Supply N/A Ground Supply N/A NOTE: 1. BW3 and BW4 are not applicable for the IDT71V tbl

3 Pin Definitio (1) Symbol Pin Function I/O Active Description A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK and ADSC Low or Low and CE Low. ADSC ADV Address Status (Cache Controller) Address Status (Processor) Burst Address Advance I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the address registers with new addresses. I LOW Synchronous Address Status from Processor. is an active LOW input that is used to load the address registers with new addresses. is gated by CE. I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not incremented; that is there is no address advance. BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. BW1-BW4 Individual Byte Write Enables I LOW Synchronous byte write enables. BW1 controls I/O0-7 I/OP1 BW controls I/O8-15 I/OP etc. Any active byte write causes all outputs to be disabled. CE Chip Enable I LOW Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V67703/7903. CE also gates. CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input. CS0 Chip Select 0 I HIGH Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip. CS1 Chip Select 1 I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip. GW Global Write Enable I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of CLK. GW supersedes individual byte write enables. I/O0-I/O31 I/OP1-I/OP4 Data Input/Output I/O N/A Synchronous data input/output (I/O) pi. The data input path is registered triggered by the rising edge of CLK. The data output path is flow-through (no output register). LBO Linear Burst Order I LOW Asynchronous burst order selection input. When LBO is HIGH the inter-leaved burst sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state while the device is operating. OE Output Enable I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pi if the chip is also selected. When OE is HIGH the I/O pi are in a highimpedance state. VDD Power Supply N/A N/A 3.3V core power supply. Power Supply N/A N/A 3.3V I/O Supply. Ground N/A N/A Ground. No Connect N/A N/A pi are not electrically connected to the device. ZZ Sleep Mode 1 HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V67703/7903 to its lowest power coumption level. Data retention is guaranteed in Sleep Mode. NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK tbl

4 Absolute Maximum Ratings (1) Symbol Rating Commercial Unit Recommended Operating Temperature Supply Voltage VTERM () VTERM (36) VTERM (46) Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND - to +4.6 V - to VDD V - to VDD + V Grade Temperature (1) VDD Commercial 0 C to +70 C 0V 3.3V±5% 3.3V±5% Industrial -40 C to +85 C 0V 3.3V±5% 3.3V±5% NOTE: 1. TA is the "itant on" case temperature tbl 04 VTERM (56) TA (7) TBIAS TSTG Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature - to + V -0 to +70 o C -55 to +15 o C -55 to +15 o C PT Power Dissipation.0 W IOUT DC Output Current 50 ma 5309 tbl Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability.. VDD terminals only. 3. terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supplies have ramped up. Power supply sequencing is not necessary; however the voltage on any input or I/O pin cannot exceed during power supply ramp up. 7. TA is the "itant on" case temperature. Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage V I/O Supply Voltage V Supply Voltage V VIH Input High Voltage - Inputs.0 VDD +0.3 V VIH Input High Voltage - I/O V VIL Input Low Voltage -0.3 (1) 0.8 V NOTE: 1. VIL (min) = -1.0V for pulse width less than tcyc/ once per cycle tbl Pin TQFP Capacitance (TA = +5 C f = 1.0MHz) Symbol Parameter (1) Conditio Max. Unit CIN Input Capacitance VIN = 3dV 5 pf CI/O I/O Capacitance VOUT = 3dV 7 pf 119 BGA Capacitance (TA = +5 C f = 1.0MHz) 5309 tbl 07 Symbol Parameter (1) Conditio Max. Unit 165 fbga Capacitance (TA = +5 C f = 1.0MHz) Symbol Parameter (1) Conditio Max. Unit CIN Input Capacitance VIN = 3dV 7 pf CI/O I/O Capacitance VOUT = 3dV 7 pf 5309 tbl 07b CIN Input Capacitance VIN = 3dV 7 pf CI/O I/O Capacitance VOUT = 3dV 7 pf 5309 tbl 07a NOTE: 1. This parameter is guaranteed by device characterization but not production tested

5 Pin Configuration 56K x Pin TQFP A6 A7 CE CS0 BW4 BW3 BW BW1 CS1 VDD CLK GW BWE OE ADSC ADV A8 A I/OP3 I/O16 I/O17 I/O18 I/O19 I/O0 I/O1 I/O I/O3 (1) VDD I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O30 I/O31 I/OP I/OP I/O15 I/O14 I/O13 I/O1 I/O11 I/O10 I/O9 I/O8 VDD ZZ () I/O7 I/O6 I/O5 I/O4 I/O3 I/O I/O1 I/O0 I/OP1 LBO A5 A4 A3 A A1 A0 VDD A17 A10 A11 A1 A13 A14 A15 A drw 0a Top View 1. Pin 14 does not have to be directly connected to as long as the input voltage is < VIL.. Pin 64 can be left unconnected and the device will always remain in active mode

6 Pin Configuration 51K x Pin TQFP A6 A7 CE CS0 BW BW1 CS1 VDD CLK GW BWE OE ADSC ADV A8 A I/O8 I/O9 I/O10 I/O11 (1) VDD I/O1 I/O13 I/O14 I/O15 I/OP A10 I/OP1 I/O7 I/O6 I/O5 I/O4 VDD ZZ () I/O3 I/O I/O1 I/O0 LBO A5 A4 A3 A A1 A0 VDD A18 A11 A1 A13 A14 A15 A16 A drw 0b Top View 1. Pin 14 does not have to be directly connected to as long as the input voltage is < VIL.. Pin 64 can be left unconnected and the device will always remain in active mode

7 Pin Configuration 56K x BGA A A6 A4 A8 A16 B CS (4) 0 A3 ADSC A9 A17 C A7 A VDD A1 A15 D I/O16 I/OP3 I/OP I/O15 E I/O17 I/O18 CE I/O13 I/O14 F I/O19 OE I/O1 G I/O0 I/O1 BW3 ADV BW I/O11 I/O10 H I/O I/O3 GW I/O9 I/O8 J VDD VDD VDD K I/O4 I/O6 CLK I/O6 I/O7 L I/O5 I/O7 BW4 BW1 I/O4 I/O5 M I/O8 BWE I/O3 N I/O9 I/O30 A1 I/O I/O1 P I/O31 I/OP4 A0 I/OP1 I/O0 R A5 LBO VDD (1) A13 T A10 A11 A14 ZZ() U DNU (3) DNU (3) DNU (3) DNU (3) DNU (3) Top View Pin Configuration 51K x BGA 5309 drw 0c A A6 A4 A8 A16 B CS 0 (4) A3 ADSC A9 A18 C A7 A VDD A13 A17 D I/O8 I/OP1 E I/O9 CE I/O7 F OE I/O6 G I/O10 BW ADV I/O5 H I/O11 GW I/O4 J VDD VDD VDD K I/O1 CLK I/O3 L I/O13 BW1 I/O M I/O14 BWE N I/O15 A1 I/O1 P I/OP A0 I/O0 R A5 LBO VDD (1) A1 T A10 A15 A14 A11 ZZ() U DNU (3) DNU (3) DNU (3) DNU (3) DNU (3) Top View 1. R5 does not have to be directly connected to as long as the input voltage is < VIL.. T7 can be left unconnected and the device will always remain in active mode. 3. DNU= Do not use; these signals can either be left unconnected or tied to Vss. 4. On future 18M devices CS 0 will be removed B will be used for address expaion drw 0d 6.4 7

8 Pin Configuration 56K x fbga A (3) A7 CE BW3 BW CS1 BWE ADSC ADV A8 B A6 CS0 BW4 BW1 CLK GW OE A9 (3) C I/OP3 I/OP D I/O17 I/O16 VDD VDD I/O15 I/O14 E I/O19 I/O18 VDD VDD I/O13 I/O1 F I/O1 I/O0 VDD VDD I/O11 I/O10 G I/O3 I/O VDD VDD I/O9 I/O8 H (1) VDD VDD ZZ () J I/O5 I/O4 VDD VDD I/O7 I/O6 K I/O7 I/O6 VDD VDD I/O5 I/O4 L I/O9 I/O8 VDD VDD I/O3 I/O M I/O31 I/O30 VDD VDD I/O1 I/O0 N I/OP4 (3) I/OP1 P (3) A5 A DNU (4) A1 DNU (4) A10 A13 A14 A17 R LBO (3) A4 A3 DNU (4) A0 DNU (4) A11 A1 A15 A tbl 17a Pin Configuration 51K x fbga A (3) A7 CE BW CS1 BWE ADSC ADV A8 A10 B A6 CS0 BW1 CLK GW OE A9 (3) C I/OP1 D I/O8 VDD VDD I/O7 E I/O9 VDD VDD I/O6 F I/O10 VDD VDD I/O5 G I/O11 VDD VDD I/O4 H (1) VDD VDD ZZ () J I/O1 VDD VDD I/O3 K I/O13 VDD VDD I/O L I/O14 VDD VDD I/O1 M I/O15 VDD VDD I/O0 N I/OP (3) P (3) A5 A DNU (4) A1 DNU (4) A11 A14 A15 A18 R LBO (3) A4 A3 DNU (4) A0 DNU (4) A1 A13 A16 A17 1. H1 does not have to be directly connected to as long as the input voltage is < VIL.. H11 can be left unconnected and the device will always remain in active mode. 3. Pin N6 B11 A1 R and P are reserved for 18M 36M 7M and 144M and 88M respectively. 4. DNU= Do not use; these signals can either be left unconnected or tied to Vss tbl 17b 6.4 8

9 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 5%) Symbol Parameter Test Conditio Min. Max. Unit ILI Input Leakage Current VDD = Max. VIN = 0V to VDD ILI LBO Input Leakage Current (1) VDD = Max. VIN = 0V to VDD ILO Output Leakage Current VOUT = 0V to VCC 5 µa 30 µa 5 µa VOL Output Low Voltage IOL = +8mA VDD = Min. 0.4 V VOH Output High Voltage IOH = -8mA VDD = Min..4 V NOTE: 5309 tbl The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ in will be internally pulled to if not actively driven. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1) Symbol Parameter Test Conditio Com'l Ind Com'l Ind Com'l Ind IDD Operating Power Supply Current Device Selected Outputs Open VDD = Max. = Max. VIN > VIH or < VIL f = fmax () ISB1 CMOS Standby Power Supply Current Device Deselected Outputs Open VDD = Max. = Max. VIN > VHD or < VLD f = 0 (3) ISB Clock Running Power Supply Current Device Deselected Outputs Open VDD = Max. = Max. VIN > VHD or < VLD f = fmax (.3) Unit ma ma ma IZZ Full Sleep Mode Supply Current ZZ > VHD VDD = Max ma 1. All values are maximum guaranteed values.. At f = fmax inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 mea no input lines are changing. 3. For I/Os VHD = - 0.V VLD = 0.V. For other inputs VHD = VDD - 0.V VLD = 0.V tbl 09 AC Test Conditio ( = 3.3V/.5V) Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load 0 to 3V 1.5V 1.5V See Figure tbl 10 AC Test Load I/O / 50Ω Z0 = 50Ω 5309 drw 03 Figure 1. AC Test Load ΔtCD 3 (Typical ) Capacitance (pf) 5309 drw 05 Figure. Lumped Capacitive Load Typical Derating 6.4 9

10 Synchronous Truth Table (13) Operation Address Used CE CS0 CS1 ADSC ADV GW BWE BWx OE () CLK I/O Deselected Cycle Power Down None H X X X L X X X X X HI-Z Deselected Cycle Power Down None L X H L X X X X X X HI-Z Deselected Cycle Power Down None L L X L X X X X X X HI-Z Deselected Cycle Power Down None L X H X L X X X X X HI-Z Deselected Cycle Power Down None L L X X L X X X X X HI-Z Read Cycle Begin Burst External L H L L X X X X X L DOUT Read Cycle Begin Burst External L H L L X X X X X H HI-Z Read Cycle Begin Burst External L H L H L X H H X L DOUT Read Cycle Begin Burst External L H L H L X H L H L DOUT Read Cycle Begin Burst External L H L H L X H L H H HI-Z Write Cycle Begin Burst External L H L H L X H L L X DIN Write Cycle Begin Burst External L H L H L X L X X X DIN Read Cycle Continue Burst Next X X X H H L H H X L DOUT Read Cycle Continue Burst Next X X X H H L H H X H HI-Z Read Cycle Continue Burst Next X X X H H L H X H L DOUT Read Cycle Continue Burst Next X X X H H L H X H H HI-Z Read Cycle Continue Burst Next H X X X H L H H X L DOUT Read Cycle Continue Burst Next H X X X H L H H X H HI-Z Read Cycle Continue Burst Next H X X X H L H X H L DOUT Read Cycle Continue Burst Next H X X X H L H X H H HI-Z Write Cycle Continue Burst Next X X X H H L H L L X DIN Write Cycle Continue Burst Next X X X H H L L X X X DIN Write Cycle Continue Burst Next H X X X H L H L L X DIN Write Cycle Continue Burst Next H X X X H L L X X X DIN Read Cycle Suspend Burst Current X X X H H H H H X L DOUT Read Cycle Suspend Burst Current X X X H H H H H X H HI-Z Read Cycle Suspend Burst Current X X X H H H H X H L DOUT Read Cycle Suspend Burst Current X X X H H H H X H H HI-Z Read Cycle Suspend Burst Current H X X X H H H H X L DOUT Read Cycle Suspend Burst Current H X X X H H H H X H HI-Z Read Cycle Suspend Burst Current H X X X H H H X H L DOUT Read Cycle Suspend Burst Current H X X X H H H X H H HI-Z Write Cycle Suspend Burst Current X X X H H H H L L X DIN Write Cycle Suspend Burst Current X X X H H H L X X X DIN Write Cycle Suspend Burst Current H X X X H H H L L X DIN Write Cycle Suspend Burst Current H X X X H H L X X X DIN 1. L = VIL H = VIH X = Don t Care.. OE is an asynchronous input. 3. ZZ - low for the table tbl

11 Synchronous Write Function Truth Table (1 ) Operation GW BWE BW1 BW BW3 BW4 Read H H X X X X Read H L H H H H Write all Bytes L X X X X X Write all Bytes H L L L L L Write Byte 1 (3) H L L H H H Write Byte (3) H L H L H H Write Byte 3 (3) H L H H L H Write Byte 4 (3) H L H H H L 1. L = VIL H = VIH X = Don t Care.. BW3 and BW4 are not applicable for the IDT71V Multiple bytes may be selected during the same cycle tbl 1 Asynchronous Truth Table (1) Operation () OE ZZ I/O Status Power Read L L Data Out Active Read H L High-Z Active Write X L High-Z Data In Active Deselected X L High-Z Standby Sleep Mode X H High-Z Sleep 1. L = VIL H = VIH X = Don t Care.. Synchronous function pi must be biased appropriately to satisfy operation requirements tbl 13 Interleaved Burst Sequence Table ( LBO=VDD) Sequence 1 Sequence Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address Second Address Third Address Fourth Address (1) NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state tbl 14 Linear Burst Sequence Table ( LBO=) Sequence 1 Sequence Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address Second Address Third Address Fourth Address (1) NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state tbl

12 AC Electrical Characteristics (VDD = 3.3V ±5% Commercial and Industrial Temperature Ranges) Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Clock Parameter tcyc Clock Cycle Time tch (1) Clock High Pulse Width tcl (1) Clock Low Pulse Width Output Parameters tcd Clock High to Valid Data tcdc Clock High to Data Change tclz () Clock High to Output Active tchz () Clock High to Data High-Z toe Output Enable Access Time tolz () Output Enable Low to Output Active tohz () Outp ut Enable High to Output High-Z Set Up Times tsa Address Setup Time 1.5 tss Address Status Setup Time 1.5 tsd Data In Setup Time 1.5 tsw Write Setup Time 1.5 tsav Address Advance Setup Time 1.5 tsc Chip Enable/Select Setup Time 1.5 Hold Times tha Address Hold Time ths Address Status Hold Time thd Data In Hold Time thw Write Hold Time thav Address Advance Hold Time thc Chip Enable/Select Hold Time Sleep Mode and Configuration Parameters tzzpw ZZ Pulse Width tzzr (3) ZZ Recovery Time tcfg (4) Configuration Set-up Time Measured as HIGH above VIH and LOW below VIL.. Traition is measured ±00mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tcfg is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation tbl

13 Timing Waveform of Flow-Through Read Cycle (1) tcyc tss tch tcl ths CLK (1) ADSC tsa tha Ax Ay ADDRESS tsw thw GW BWE BWx tsc thc CE CS1 (Note 3) tsav thav ADV ADV HIGH suspends burst toe OE tcd tohz tchz (Burst wraps around to its initial state) tcdc tolz O1(Ay) O(Ay) O3(Ay) O4(Ay) O1(Ay) O(Ay) DATAOUT O1(Ax) Burst Flow-through Read Output Disabled 5309 drw 06 Flow-through Read 1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O (Ay) represents the next output data in the burst sequence of the base address Ay etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.. ZZ input is LOW and LBO is Don't Care for this cycle. 3. CS0 timing traitio are identical but inverted to the CE and CS1 signals. For example when CE and CS1 are LOW on this waveform CS0 is HIGH

14 Timing Waveform of Combined Flow-Through Read and Write Cycles (13) tcyc tch tcl () tss ths CLK tsa tha Ax Ay Az ADDRESS thw tsw GW ADV tsd thd OE toe tolz tcdc I1(Ay) tcd tclz tohz DATAIN O(Az) O3(Az) O4(Az) O1(Az) O1(Ax) DATAOUT tcd Single Read Write Flow-through Burst Read 5309 drw Device is selected through entire cycle; CE and CS1 are LOW CS0 is HIGH.. ZZ input is LOW and LBO is Don't Care for this cycle. 3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O (Az) represents the next output data in the burst sequence of the base address Az etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input

15 Timing Waveform of Write Cycle No. 1 - GW Controlled (13) tcyc CLK tch tcl tss ths (1) ADSC tha tsa Ax Ay Az ADDRESS thw tsw GW is ignored when initiates a cycle and is sampled on the next cycle rising edge GW tsc thc tsav thav CE CS1 (Note 3) ADV (ADV suspends burst) OE thd tsd I(Az) I3(Az) I1(Ax) I1(Ay) I(Ay) I(Ay) I3(Ay) I4(Ay) I1(Az) () DATAIN tohz O4(Aw) O3(Aw) DATAOUT 5309 drw ZZ input is LOW BWE is HIGH and LBO is Don't Care for this cycle.. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I (Ay) represents the next input data in the burst sequence of the base address Ay etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing traitio are identical but inverted to the CE and CS1 signals. For example when CE and CS1 are LOW on this waveform CS0 is HIGH

16 Timing Waveform of Write Cycle No. - Byte Controlled (13) tcyc CLK tss tch tcl ths ADSC tha tsa Az Ax Ay ADDRESS thw BWE is ignored when initiates a cycle and is sampled on the next cycle rising edge tsw BWE thw BWx is ignored when initiates a cycle and is sampled on the next clock rising edge tsw BWx tsc thc tsav CE CS1 (Note 3) ADV (ADV HIGH suspends burst) OE thd tsd I3(Az) I1(Ax) I1(Ay) I(Ay) I(Ay) I3(Ay) I4(Ay) I1(Az) I(Az) DATAIN tohz O4(Aw) O3(Aw) DATAOUT Extended Burst Write Burst Write Single Write Burst Read 5309 drw ZZ input is LOW GW is HIGH and LBO is Don't Care for this cycle.. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address Ay; I (Ay) represents the next input data in the burst sequence of the base address Ay etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I (Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing traitio are identical but inverted to the CE and CS1 signals. For example when CE and CS1 are LOW on this waveform CS0 is HIGH

17 Timing Waveform of Sleep (ZZ) and Power-Down Modes (13) 5309 drw 13 Az tcyc CLK tss tch tcl ths ADSC ADDRESS tsa tha Ax GW CE CS1 (Note 4) tsc thc ADV OE toe tolz DATAOUT O1(Ax) tzzr ZZ tzzpw Single Read Snooze Mode 1. Device must power up in deselected Mode.. LBO is Don't Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. 4. CS0 timing traitio are identical but inverted to the CE and CS1 signaals. For example when CE and CS1 are LOW on this waveform CS0 is HIGH

18 Non-Burst Read Cycle Timing Waveform CLK ADSC ADDRESS Av Aw Ax Ay Az GW BWE BWx CE CS1 CS0 OE DATAOUT (Av) (Aw) (Ax) (Ay) 1. ZZ input is LOW ADV is HIGH and LBO is Don't Care for this cycle.. (Ax) represents the data for address Ax etc. 3. For read cycles and ADSC function identically and are therefore interchangable drw 10 Non-Burst Write Cycle Timing Waveform CLK ADSC ADDRESS Av Aw Ax Ay Az GW CE CS1 CS0 DATAIN (Av) (Aw) (Ax) (Ay) (Az) 1. ZZ input is LOW ADV and OE are HIGH and LBO is Don't Care for this cycle.. (Ax) represents the data for address Ax etc. 3. Although only GW writes are shown the functionality of BWE and BWx together is the same as GW. 4. For write cycles and ADSC have different limitatio drw

19 Ordering Information XXXX Device Type S Power X Speed XX Package X X Process/ Temperature Range X Blank 8 Blank I Tube or Tray Tape and Reel Commercial (0 C to +70 C) Industrial (-40 C to +85 C) G Green PF BG BQ 100-Pin Plastic Thin Quad Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 fine pitch Ball Grid Array (fbga) Access Time in Tenths of Nanoseconds 71V V K x 36 Flow-Through Burst Synchronous SRAM 51K x 18 Flow-Through Burst Synchronous SRAM 5309 drw

20 Datasheet Document History 1/31/99 Created Datasheet from 71V677 and 71V679 Datasheets For.5V I/O offering see 71V6770 AND 71V6790 Datasheets. 04/6/00 Pg. 4 Add capacitance for BGA package; Iert clarification note to Absolute Max Ratings and Recommended Operating Temperature tables. Pg. 7 Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout Pg. 18 Ierted 100 pin TQFP Package Diagram Outline 05/4/00 Pg Add new package offering 13 x 15 fbga Pg Correct note on BGA and TQFP pin configuration Pg. 0 Correction in the 119 BGA Package Diagram Outline 07/1/00 Pg. 568 Remove note from TQFP and BQ165 pinouts Pg. 7 Add/Remove note from BG119 pinout Pg. 0 Update BG 119 pinout 1/18/00 Pg. 9 Updated ISB levels for /9/01 Pg. 1 Remove JTAG pi Pg. 7 Changed U-U6 pi to DNU. Pg. 8 Changed P5P7R5 & R7 to DNU pi. Pg. 9 Raised specs by 10mA on and //0 Pg. 1-3 Changed datasheet from Advanced to Final Release. Pg. 491 Added I temp to datasheet. 04/15/03 Pg. 4 Updated 165 fbga table from TBD to 7. 1/0/03 Pg. 7 Updated 119BGS pin configuratio- reordered I/O signals on P6 P7 (18K x 36) and P7 N6 L6 K7 H6 G7 F6 E7 D6 (56K x 18). 0/0/09 Pg. Removed "IDT" from the orderable part number 11/19/14 Pg.1 & 0 Added green parts available note to Features & to Ordering Information Pg. 1-3 Moved the FBD the pin description and pin definition tables to pages 1-3 respectively to align the datasheet reading flow to that of our other established datasheets Pg. 0 Added tape & reel to ordering information Pg Removed three Package Diagrm Outlines. from this datasheet. Please see idt.com for Package Diagrm Outlines specific to these devices. CORPORATE HEADQUARTERS for SALES: for Tech Support: 604 Silver Creek Valley Road or sramhelp@idt.com San Jose CA fax: The IDT logo is a registered trademark of Integrated Device Technology Inc