IS61WV2568EDBLL IS64WV2568EDBLL

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ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power

V ± % ( ns) Fully static operation: no clock or refresh required Three state outputs Industrial and Automotive temperature support Lead-free available Error Detection and Error Correction FUTIONAL

This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.

1 ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply Vdd.V to.v ( ns) Vdd.V ± % ( ns) Fully static operation: no clock or refresh required Three state outputs Industrial and Automotive temperature support Lead-free available Error Detection and Error Correction FUTIONAL BLOCK DIAGRAM DEMBER 0 DESCRIPTION The ISSI IS/WVEDBLL is a high-speed,,0,-bit static RAMs organized as, words by bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS/WVEDBLL is packaged in the JEDEC standard -pin TSOP-II, -pin SOJ and -pin Mini BGA (mm x mm). A0-A Decoder Memory Array (Kx) ECC Array (Kx) IO0- I/O Data ECC Circuit Column I/O / /OE /WE Control Circuit Copyright 0 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.

2 PIN CONFIGURATION mini BGA -Pin TSOP (Type II) A B C D E F G H A0 A A A A I/O A WE A A I/O0 I/O A I/O VDD VDD I/O A I/O I/O OE A A I/O A A A A A A A0 A A A A I/O0 I/O VDD I/O I/O WE A A A A A A A A A OE I/O I/O VDD I/O I/O A A A A PIN DESCRIPTIONS -Pin SOJ A0-A OE WE I/O0-I/O Vdd Address Inputs Chip Enable Input Output Enable Input Write Enable Input Bidirectional Ports Power Ground No Connection A0 A A A A I/O0 I/O VDD I/O I/O WE A A A A A 0 0 A A A A OE I/O I/O VDD I/O I/O A A A A Integrated Silicon Solution, Inc.

3 ABSOLUTE MAXIMUM RATINGS () Symbol Parameter Value Unit Vterm Terminal Voltage with Respect to 0. to Vdd + 0. V Vdd Vdd Relates to 0. to.0 V Tstg Storage Temperature to +0 C Pt Power Dissipation.0 W Notes:. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITAE (,) Symbol Parameter Conditions Max. Unit Cin Input Capacitance Vin = 0V pf C I/O Input/Output Capacitance Vout = 0V pf Notes:. Tested initially and after any design or process changes that may affect these parameters.. Test conditions: Ta = C, f = MHz, Vdd =.V. ERROR DETECTION AND ERROR CORRECTION Independent ECC with hamming code for each byte Detect and correct one bit error per byte Better reliability than parity code schemes which can only detect an error but not correct an error Backward Compatible: Drop in replacement to current in industry standard devices (without ECC) TRUTH TABLE Mode WE OE I/O Operation Vdd Current Not Selected H X X High-Z Isb, Isb (Power-down) Output Disabled L H H High-Z Icc Read L H L Dout Icc Write L L X Din Icc OPERATING RANGE (Vdd) Range Ambient Temperature ISWVEDBLL ISWVEDBLL Vdd (, ns) Vdd (ns) Industrial 0 C to + C.V-.V (ns).v ± % (ns) Automotive (A) 0 C to + C.V-.V Automotive (A) 0 C to + C.V-.V Note:. Contact SRAM@issi.com for.v option Integrated Silicon Solution, Inc.

4 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd =.V + % Symbol Parameter Test Conditions Min. Max. Unit Voh Output HIGH Voltage Vdd = Min., Ioh =.0 ma. V Vol Output LOW Voltage Vdd = Min., Iol =.0 ma 0. V Vih Input HIGH Voltage Vdd + 0. V Vil Input LOW Voltage () V Ili Input Leakage Vin Vdd µa Ilo Output Leakage Vout Vdd, Outputs Disabled µa Note:. Vil (min.) = 0.V DC; Vil (min.) =.0V AC (pulse width < ns). Not 0% tested. Vih (max.) = Vdd + 0.V DC; Vih (max.) = Vdd +.0V AC (pulse width < ns). Not 0% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd =.V-.V Symbol Parameter Test Conditions Min. Max. Unit Voh Output HIGH Voltage Vdd = Min., Ioh =.0 ma. V Vol Output LOW Voltage Vdd = Min., Iol =.0 ma 0. V Vih Input HIGH Voltage.0 Vdd + 0. V Vil Input LOW Voltage () V Ili Input Leakage Vin Vdd µa Ilo Output Leakage Vout Vdd, Outputs Disabled µa Note:. Vil (min.) = 0.V DC; Vil (min.) =.0V AC (pulse width < ns). Not 0% tested. Vih (max.) = Vdd + 0.V DC; Vih (max.) = Vdd +.0V AC (pulse width < ns). Not 0% tested. POWER SUPPLY CHARACTERISTICS () (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com. 0 0 ma Supply Current Iout = 0 ma, f = fmax Ind. 0 Auto. 0 typ. () Icc Operating Vdd = Max., Com ma Supply Current Iout = 0 ma, f = 0 Ind. Auto. 0 0 Isb TTL Standby Current Vdd = Max., Com. ma (TTL Inputs) Vin = Vih or Vil Ind. Vih, f = 0 Auto. 0 0 Isb CMOS Standby Vdd = Max., Com. ma Current (CMOS Inputs) Vdd 0.V, Ind. Vin Vdd 0.V, or Auto. Vin 0.V, f = 0 typ. ().. Note:. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.. Typical values are measured at Vdd =.0V, Ta = o C and not 0% tested. Integrated Silicon Solution, Inc.

5 AC TEST CONDITIONS Parameter AC TEST LOADS Unit (.V-.V) 0.V to Vdd-0.V V/ ns Vdd/ Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load See Figures and OUTPUT ZO = 0Ω Figure. 0Ω 0 pf Including jig and scope.v.v OUTPUT pf Including jig and scope Ω Figure. Ω READ CYCLE SWITCHING CHARACTERISTICS () (Over Operating Range) Symbol Parameter Min. Max. Min. Max. Min. Max. Unit trc Read Cycle Time 0 ns taa Address Access Time 0 ns toha Output Hold Time.0.0. ns tace Access Time 0 ns tdoe OE Access Time.. ns thzoe () OE to High-Z Output ns tlzoe () OE to Low-Z Output ns thzce ( to High-Z Output ns tlzce () to Low-Z Output ns tpu Power Up Time ns tpd Power Down Time 0 ns Notes:. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure ).. Tested with the load in Figure. Transition is measured ±00 mv from steady-state voltage. Integrated Silicon Solution, Inc.

6 AC WAVEFORMS READ CYCLE NO. (,) (Address Controlled) ( = OE = Vil) ADDRESS t RC t OHA t AA t OHA DOUT PREVIOUS DATA VALID DATA VALID READ.eps READ CYCLE NO. (,) ( and OE Controlled) ADDRESS t RC t AA t OHA OE t DOE t HZOE t LZOE t LZ t A t HZ DOUT HIGH-Z DATA VALID _RD.eps Notes:. WE is HIGH for a Read Cycle.. The device is continuously selected. OE, = Vil.. Address is valid prior to or coincident with LOW transitions. Integrated Silicon Solution, Inc.

7 WRITE CYCLE SWITCHING CHARACTERISTICS (,) (Over Operating Range) Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twc Write Cycle Time 0 ns tsce to Write End. ns taw Address Setup Time. ns to Write End tha Address Hold from Write End ns tsa Address Setup Time ns tpwe WE Pulse Width. ns tpwe WE Pulse Width (OE = LOW).0 ns tsd Data Setup to Write End ns thd Data Hold from Write End ns thzwe () WE LOW to High-Z Output. ns tlzwe () WE HIGH to Low-Z Output ns Notes:. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure ).. Tested with the load in Figure. Transition is measured ±00 mv from steady-state voltage. Not 0% tested.. The internal write time is defined by the overlap of LOW, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development Integrated Silicon Solution, Inc.

8 AC WAVEFORMS WRITE CYCLE NO. (,) ( Controlled, OE = HIGH or LOW) t WC ADDRESS VALID ADDRESS t SA t S t HA WE DOUT DATA UNDEFINED t AW t PWE t PWE t HZWE HIGH-Z t LZWE t SD t HD DIN DATAIN VALID _WR.eps Integrated Silicon Solution, Inc.

9 WRITE CYCLE NO. (,) (WE Controlled: OE is HIGH During Write Cycle) ADDRESS t WC VALID ADDRESS OE t HA LOW t AW WE t SA t HZWE t PWE t LZWE DOUT DATA UNDEFINED HIGH-Z t SD t HD DIN DATAIN VALID _WR.eps Notes:. The internal write time is defined by the overlap of LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.. I/O will assume the High-Z state if OE > Vih. WRITE CYCLE NO. (WE Controlled: OE is LOW During Write Cycle) ADDRESS OE t WC VALID ADDRESS LOW t HA LOW t AW WE t SA t HZWE t PWE t LZWE DOUT DATA UNDEFINED HIGH-Z t SD t HD DIN DATAIN VALID _WR.eps Integrated Silicon Solution, Inc.

10 HIGH SPEED DATA RETENTION SWITCHING CHARACTERISTICS (.V-.V) Symbol Parameter Test Condition Options Min. Typ. () Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform.0. V Idr Data Retention Current Vdd =.0V, Vdd 0.V Com. 0. ma Ind. Auto. tsdr Data Retention Setup Time See Data Retention Waveform 0 ns trdr Recovery Time See Data Retention Waveform trc ns Note : Typical values are measured at Vdd = Vdr(min), Ta = o C and not 0% tested. DATA RETENTION WAVEFORM ( Controlled) tsdr Data Retention Mode trdr VDD VDR VDD - 0.V Integrated Silicon Solution, Inc.

11 ORDERING INFORMATION Industrial Range: -0 C to + C Speed (ns) Order Part No. Package ISWVEDBLL-BLI mini BGA (mm x mm), Lead-free ISWVEDBLL-TLI TSOP (Type II), Lead-free ISWVEDBLL-KLI 00-mil Plastic SOJ, Lead-free Industrial Range: -0 C to + C Speed (ns) Order Part No. Package ISWVEDBLL-BI mini BGA (mm x mm) ISWVEDBLL-BLI mini BGA (mm x mm), Lead-free ISWVEDBLL-TI TSOP (Type II) ISWVEDBLL-TLI TSOP (Type II), Lead-free ISWVEDBLL-KLI 00-mil Plastic SOJ, Lead-free Automotive (A) Range: -0 C to + C Speed (ns) Order Part No. Package ISWVEDBLL-BA mini BGA (mm x mm) ISWVEDBLL-BLA mini BGA (mm x mm), Lead-free ISWVEDBLL-CTA TSOP (Type II), Copper Leadframe ISWVEDBLL-CTLA TSOP (Type II), Lead-free, Copper Leadframe ISWVEDBLL-KLA 00-mil Plastic SOJ, Lead-free Automotive (A) Range: -0 C to + C Speed (ns) Order Part No. Package ISWVEDBLL-BA mini BGA (mm x mm) ISWVEDBLL-BLA mini BGA (mm x mm), Lead-free ISWVEDBLL-CTA TSOP (Type II), Copper Leadframe ISWVEDBLL-CTLA TSOP (Type II), Lead-free, Copper Leadframe ISWVEDBLL-KLA 00-mil Plastic SOJ, Lead-free Integrated Silicon Solution, Inc.

12 NOTE :. CONTROLLING DIMENSION : MM. DIMENSION D AND E DO NOT ILUDE MOLD PROTRUSION.. DIMENSION b DOES NOT ILUDE DAMBAR PROTRUSION/INTRUSION. Package Outline 0/0/00 Integrated Silicon Solution, Inc.

13 /0/00 NOTE :. Controlling dimension : mm. Dimension D and E do not include mold protrusion.. Dimension b does not include dambar protrusion/intrusion.. Formed leads shall be planar with respect to one another within 0.mm at the seating plane after final test.. Reference document : JEDEC SPEC MS-0. Integrated Silicon Solution, Inc.

14 NOTE :. CONTROLLING DIMENSION : MM.. Reference document : JEDEC MO-0 Package Outline 0//00 Integrated Silicon Solution, Inc.

IS61WV10248EDBLL IS64WV10248EDBLL

IS61WV10248EDBLL IS64WV10248EDBLL 1M x 8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEBRUARY 2013 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater