8K x 8 Static RAM CY6264. Features. Functional Description

Size: px

Start display at page:

Download "8K x 8 Static RAM CY6264. Features. Functional Description"

Henry Carson
5 years ago
Views:

8K x 8 Static RAM Features 55, 70 ns access times CMOS for optimum speed/power Easy memory expansion with CE 1, CE 2, and OE features TTL-compatible inputs and outputs Automatic power-down when

1 8K x 8 Static RAM Features 55, 70 ns access times CMOS for optimum speed/power Easy memory expansion with CE 1, CE 2, and OE features TTL-compatible inputs and outputs Automatic power-down when deselected Functional Description The CY6264 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE 1 ), an active HIGH chip enable (CE 2 ), and active LOW output enable (OE) and three-state drivers. Both devices have an automatic power-down feature (CE 1 ), reducing the power consumption by over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE 1 and WE inputs are both LOW and CE 2 is HIGH, data on the eight data input/output pins (I/O 0 through I/O 7 ) is written into the memory location addressed by the address present on the address pins (A 0 through A 12 ). Reading the device is accomplished by selecting the device and enabling the outputs, CE 1 and OE active LOW, CE 2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity. Logic Block Diagram Pin Configuration SOIC Top View A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 ROW DECODER INPUT BUFFER 256 x 32 x 8 ARRAY I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 NC A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 I/O 0 I/O 1 I/O 2 GND V CC WE CE 2 A 3 A 2 A 1 OE A 0 CE 1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 COLUMN DECODER A 0 A 9 A 10 A 11 A 12 SENSE AMPS I/O 6 CE 1 CE 2 WE OE POWER DOWN I/O 7 Cypress Semiconductor Corporation 3901 North First Street San Jose, CA Document #: Rev. ** Revised June 27, 2005

2 Selection Guide CY CY Unit Maximum Access Time ns Maximum Operating Current Commercial ma Industrial 200 Maximum Standby Current Commercial 20/15 20/15 ma Industrial 30 Shaded areas contain advance information. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage to Ground Potential V to +7.0V DC Voltage Applied to Outputs in High Z State [1] V to +7.0V DC Input Voltage [1] V to +7.0V Output Current into Outputs (LOW) ma Static Discharge Voltage... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current... >200 ma Operating Range Ambient Range Temperature V CC Commercial 0 C to +70 C 5V ± 10% Industrial 40 C to +85 C Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Min. Max. V OH Output HIGH Voltage V CC = Min., I OH = 4.0 ma V V OL Output LOW Voltage V CC = Min., I OL = 8.0 ma V V IH Input HIGH Voltage 2.2 V CC 2.2 V CC V V IL Input LOW Voltage [1] V I IX Input Load Current GND < V I < V CC µa I OZ Output Leakage GND < V I < V CC, µa Current Output Disabled I OS I CC Output Short Circuit Current [2] V CC Operating Supply Current I SB1 Automatic CE 1 Power Down Current I SB2 Automatic CE 1 Power Down Current Shaded areas contain advance information. V CC = Max., V OUT = GND V CC = Max., I OUT = 0 ma Max. V CC, CE 1 > V IH, Min. Duty Cycle=100% Unit ma Com l ma Ind l 200 Com l ma Ind l 40 Max. V CC, CE 1 > V CC 0.3V, Com l ma V IN > V CC 0.3V or V IN < 0.3V Ind l 30 Notes: 1. Minimum voltage is equal to 3.0V for pulse durations less than 30 ns. 2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Document #: Rev. ** Page 2 of 10

3 Switching Characteristics Over the Operating Range [3] Parameter READ CYCLE Description Min. Max. Min. Max. t RC Read Cycle Time ns t AA Address to Data Valid ns t OHA Data Hold from Address Change 5 5 ns t ACE1 CE 1 LOW to Data Valid ns t ACE2 CE 2 HIGH to Data Valid ns t DOE OE LOW to Data Valid ns t LZOE OE LOW to Low Z 3 5 ns t HZOE OE HIGH to High Z [4] ns t LZCE1 CE 1 LOW to Low Z [5] 5 5 ns t LZCE2 CE 2 HIGH to Low Z 3 5 ns t HZCE CE 1 HIGH to High Z [4, 5] CE 2 LOW to High Z Unit ns t PU CE 1 LOW to Power-Up 0 0 ns t PD CE 1 HIGH to Power-Down ns WRITE CYCLE [6] t WC Write Cycle Time ns t SCE1 CE 1 LOW to Write End ns t SCE2 CE 2 HIGH to Write End ns t AW Address Set-Up to Write End ns t HA Address Hold from Write End 0 0 ns t SA Address Set-Up to Write Start 0 0 ns t PWE WE Pulse Width ns t SD Data Set-Up to Write End ns t HD Data Hold from Write End 0 0 ns t HZWE WE LOW to High Z [4] ns t LZWE WE HIGH to Low Z 5 5 ns Shaded areas contain advance information. Capacitance [7] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 7 pf C OUT Output Capacitance V CC = 5.0V 7 pf Notes: 3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance. 4. t HZOE, t HZCE, and t HZWE are specified with C L = 5 pf as in part (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 5. At any given temperature and voltage condition, t HZCE is less than t LZCE for any given device. 6. The internal write time of the memory is defined by the overlap of CE 1 LOW, CE 2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: Rev. ** Page 3 of 10

4 AC Test Loads and Waveforms 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE R1 481Ω (a) R2 255Ω 5V OUTPUT 5 pf INCLUDING JIG AND SCOPE R1 481Ω (b) R2 255Ω CY6264 ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND < 5ns < 5 ns Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Waveforms Read Cycle No. 1 [8, 9] t RC ADDRESS t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 [10, 11] CE 1 t RC CE 2 OE t ACE DATA OUT t DOE t LZOE HIGH IMPEDANCE DATA VALID t HZOE thzce HIGH IMPEDANCE t LZCE V CC SUPPLY CURRENT t PU 50% t PD 50% ICC ISB Notes: 8. Device is continuously selected. OE, CE = V IL. CE 2 = V IH. 9. Address valid prior to or coincident with CE transition LOW. 10. WE is HIGH for read cycle. 11. Data I/O is High Z if OE = V IH, CE 1 = V IH, or WE = V IL. Document #: Rev. ** Page 4 of 10

5 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [9, 11] t WC ADDRESS t SCE1 CE 1 CE 2 t SCE2 OE t AW t HA WE t SA t PWE t SD t HD DATA IN DATA IN VALID t HZWE t LZWE DATA I/O DATA UNDEFINED HIGH IMPEDANCE Write Cycle No. 2 (CE Controlled) [9, 11, 12] t WC ADDRESS CE 1 t SCE1 t SA CE 2 t AW t SCE2 t HA t PWE WE t SD t HD DATA IN DATA IN VALID t HZWE DATA I/O DATA UNDEFINED HIGH IMPEDANCE Note: 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: Rev. ** Page 5 of 10

6 Typical DC and AC Characteristics NORMALIZED I CC, I SB NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE I CC I SB SUPPLY VOLTAGE (V) NORMALIZED I CC, I SB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE I SB V CC =5.0V V IN =5.0V I CC AMBIENT TEMPERATURE ( C) OUTPUT SOURCE CURRENT (ma) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE V CC =5.0V T A =25 C OUTPUT VOLTAGE (V) NORMALIZED t AA NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE T A =25 C SUPPLY VOLTAGE (V) NORMALIZED t AA NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE V CC =5.0V AMBIENT TEMPERATURE ( C) OUTPUT SINK CURRENT (ma) OUTPUT SINK CURRENT vs.output VOLTAGE V CC =5.0V T A =25 C OUTPUT VOLTAGE (V) NORMALIZED I PO TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE DELTA t AA (ns) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING V CC =4.5V T A =25 C NORMALIZED I CC NORMALIZED I CC vs. CYCLE TIME 1.25 V CC =5.0V T A =25 C V CC =0.5V SUPPLY VOLTAGE(V) CAPACITANCE (pf) CYCLE FREQUENCY (MHz) Document #: Rev. ** Page 6 of 10

7 Truth Table CE 1 CE 2 WE OE Input/Output Mode H X X X High Z Deselect/Power-Down X L X X High Z Deselect L H H L Data Out Read L H L X Data In Write L H H H High Z Deselect Address Designators Address Name Address Function Pin Number A4 X3 2 A5 X4 3 A6 X5 4 A7 X6 5 A8 X7 6 A9 Y1 7 A10 Y4 8 A11 Y3 9 A12 Y0 10 A0 Y2 21 A1 X0 23 A2 X1 24 A3 X2 25 Document #: Rev. ** Page 7 of 10

8 Ordering Information Speed (ns) Ordering Code Package Name Package Type 55 CY SC S Lead 330-Mil SOIC [13] Commercial 70 CY SC S Lead 330-Mil SOIC [13] Commercial 55 CY SNC SN28 28-Lead 300-Mil SOIC Commercial 55 CY SNXC SN28 28-Lead 300-Mil SOIC (Pb-free) Commercial 70 CY SNC SN28 28-Lead 300-Mil SOIC Commercial 70 CY SNXC SN28 28-Lead 300-Mil SOIC (Pb-free) Commercial 70 CY SNI SN28 28-Lead 300-Mil SOIC Industrial 70 CY SNXI SN28 28-Lead 300-Mil SOIC (Pb-free) Industrial Shaded areas contain advance information. Package Diagrams 28-lead (300 mil) SNC Package Outline (Narrow Body) SN28 CY6264 Operating Range PIN1ID DIMENSIONS IN INCHES OMEDATA CSPI MIN. MAX DETAIL "A" DETAIL "B" SEATING PLANE B Note: 13. Not recommended for new designs. A TYP *B Document #: Rev. ** Page 8 of 10

9 Package Diagrams (continued) 28-Lead SOIC with Wide Body S28.33 CURRENT SOIC WITH WIDE BODY PIN1ID DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 0.79gms MIN. MAX [8.585] 0.346[8.788] 0.460[11.684] 0.480[12.192] PART # S28.33 STANDARD PKG. SZ28.33 LEAD FREE PKG [18.288] 0.728[18.491] SEATING PLANE 0.094[2.387] 0.110[2.794] 0.050[1.270] TYP [0.355] 0.020[0.508] 0.002[0.050] 0.014[0.355] 0.004[0.102] 0.030[0.762] 0.050[1.270] 0.008[0.203] 0.012[0.304] *B Document #: Rev. ** Page 9 of 10 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

10 Document History Page Document Title:CY6264 8K x 8 Static RAM Document Number: Orig. of REV. ECN NO. Issue Date Change Description of Change ** See ECN PCI Spec # change from to Document #: Rev. ** Page 10 of 10

SENSE AMPS POWER DOWN

SENSE AMPS POWER DOWN 185 CY7C185 8K x 8 Static RAM Features High speed 15 ns Fast t DOE Low active power 715 mw Low standby power 220 mw CMOS for optimum speed/power Easy memory expansion with,, and OE features TTL-compatible