Very Low Power CMOS SRAM 2M X 8 bit. Pb-Free and Green package materials are compliant to RoHS. STANDBY (ICCSB1, Max) V CC=3.0V

Size: px

Start display at page:

Download "Very Low Power CMOS SRAM 2M X 8 bit. Pb-Free and Green package materials are compliant to RoHS. STANDBY (ICCSB1, Max) V CC=3.0V"

Myra Stokes
5 years ago
Views:

1 Very Low Power CMOS SRAM 2M X bit Pb-Free and Green package materials are compliant to RoHS BS62LV1600 FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption : = 3.0V Operation current : 46mA (Max.) at 55ns 2mA (Max.) at 1MHz Standby current : 1.5uA (Typ.) at 25 O C = 5.0V Operation current : 115mA (Max.) at 55ns 10mA (Max.) at 1MHz Standby current : 6.0uA (Typ.) at 25 O C High speed access time : ns (Max.) at : 3.0~5.5V ns (Max.) at : 2.7~5.5V Automatic power down when chip is deselected Easy expansion with, and OE options Three state outputs and TTL compatible Fully static operation Data retention supply voltage as low as 1.5V DESCRIPTION The BS62LV1600 is a high performance, very low power CMOS Static Random Access Memory organized as 204K by bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 1.5uA at 3.0V/25 O C and maximum access time of 55ns at 3.0V/5 O C. Easy memory expansion is provided by an active LOW chip enable (), an active HIGH chip enable (), and active LOW output enable (OE) and three-state output drivers. The BS62LV1600 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV1600 is available in JEDEC standard 44-pin TSOP II and 4-ball BGA package. POWER CONSUMPTION PRODUCT FAMILY BS62LV1600EC BS62LV1600FC BS62LV1600EI BS62LV1600FI OPERATING TEMPERATURE Commercial +0 O C to +70 O C Industrial -40 O C to +5 O C STANDBY (ICCSB1, Max) =5.0V =3.0V POWER DISSIPATION Operating (ICC, Max) =5.0V =3.0V 1MHz 10MHz f Max. 1MHz 10MHz f Max. 50uA.0uA 9mA 4mA 113mA 1.5mA 19mA 45mA 100uA 16uA 10mA 50mA 115mA 2mA 20mA 46mA PKG TYPE TSOP II-44 BGA TSOP II-44 BGA PIN CONFIGURATIONS BLOCK DIAGRAM A A4 A3 A2 A1 A0 DQ0 DQ1 VCC VSS DQ2 DQ3 A20 WE A19 A1 A17 A16 A BS62LV1600EC BS62LV1600EI OE A0 A1 A2 A5 A6 A7 OE A DQ7 DQ6 VSS VCC DQ5 DQ4 A9 A10 A11 A12 A13 A14 A20 A13 A17 A15 A1 A16 A14 A12 A7 A6 A5 A4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Address Input Buffer 12 Row Decoder Data Input Buffer Data Output Buffer 4096 Memory Array 4096 x Column I/O Write Driver Sense Amp 512 Column Decoder B C DQ0 A3 A5 A4 A6 DQ4 WE OE Control 9 Address Input Buffer VCC D VSS DQ1 A17 A7 DQ5 VCC VSS A11 A9 A A3 A2 A1 A0 A10 A19 E VCC DQ2 A16 DQ6 VSS F DQ3 A14 A15 DQ7 G A20 A12 A13 WE H A1 A A9 A10 A11 A19 4-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. 1 Revision 2.2 Jan. 2006

2 PIN DESCRIPTIONS Name A0-A20 Address Input Chip Enable 1 Input Chip Enable 2 Input WE Write Enable Input OE Output Enable Input DQ0-DQ7 Data Input/Output Ports V SS Function These 21 address inputs select one of the 204K x -bit in the RAM is active LOW and is active HIGH. Both chip enables must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. There bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground TRUTH TABLE MODE WE OE I/O OPERATION CURRENT Not selected (Power Down) H X X X X L X X High Z I CCSB, I CCSB1 Output Disabled L H H H High Z I CC Read L H H L D OUT I CC Write L H L X D IN I CC ABSOLUTE MAXIMUM RATINGS (1) SYMBOL PARAMETER RATING UNITS V TERM T BIAS Terminal Voltage with Respect to GND Temperature Under Bias -0.5 (2) to 7.0 V -40 to +125 O C OPERATING RANGE RANG AMBIENT TEMPERATURE Commercial 0 O C to + 70 O C 2.4V ~ 5.5V Industrial -40 O C to + 5 O C 2.4V ~ 5.5V T STG Storage Temperature -60 to +150 O C P T Power Dissipation 1.0 W I OUT DC Output Current 20 ma 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability V in case of AC pulse width less than 30 ns. CAPACITAE (1) (T A = 25 O C, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS C IN C IO Input Capacitance Input/Output Capacitance V IN = 0V 10 pf V I/O = 0V 12 pf 1. This parameter is guaranteed and not 100% tested. 2

3 DC ELECTRICAL CHARACTERISTICS (T A =-40 O C to +5 O C) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Power Supply V V IL Input Low Voltage -0.5 (2) V V IH Input High Voltage (3) V I IL Input Leakage Current V IN = 0V to ua I LO Output Leakage Current V I/O = 0V to, = V IH or = V IL, or OE = V IH ua V OL Output Low Voltage = Max, I OL = 2.0mA V V OH Output High Voltage = Min, I OH = -1.0mA V I CC I CC1 I CCSB (6) I CCSB1 Operating Power Supply Current Operating Power Supply Current Standby Current TTL Standby Current CMOS = V IL and = V IH, (4) I DQ = 0mA, f = F MAX = V IL and = V IH, I DQ = 0mA, f = 1MHz = V IH, or = V IL, I DQ = 0mA -0.2V or 0.2V, V IN -0.2V or V IN 0.2V VCC=3.0V 46 VCC=5.0V VCC=3.0V 2 VCC=5.0V VCC=3.0V 1.0 VCC=5.0V VCC=3.0V VCC=5.0V ma ma ma ua 1. Typical characteristics are at T A=25 O C and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: +1.0V in case of pulse width less than 20 ns. 4. F MAX=1/t RC. 5. I CC(MAX.) is 45mA/113mA at =3.0V/5.0V and T A=70 O C. 6. I CCSB1(MAX.) is.0ua/50ua at =3.0V/5.0V and T A=70 O C. DATA RETENTION CHARACTERISTICS (T A = -40 O C to +5 O C) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS V DR for Data Retention -0.2V or 0.2V, VIN -0.2V or VIN 0.2V V I CCDR (3) Data Retention Current -0.2V or 0.2V, VIN -0.2V or VIN 0.2V ua t CDR t R Chip Deselect to Data Retention Time Operation Recovery Time See Retention Waveform ns t RC (2) ns 1. =1.5V, T A=25 O C and not 100% tested. 2. t RC = Read Cycle Time. 3. I CCRD(Max.) is 4.0uA at T A=70 O C. LOW DATA RETENTION WAVEFORM (1) ( Controlled) Data Retention Mode t CDR V DR 1.5V t R V IH - 0.2V V IH 3

4 LOW DATA RETENTION WAVEFORM (2) ( Controlled) Data Retention Mode V DR 1.5V t CDR t R V IL 0.2V V IL AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS Input Pulse Levels Vcc / 0V WAVEFORM INPUTS OUTPUTS Input Rise and Fall Times Input and Output Timing Reference Level Output Output Load t CLZ, t OLZ, t CHZ, t OHZ, t WHZ Others 1 TTL C L (1) GND 1. Including jig and scope capacitance. 10% 1V/ns 0.5Vcc C L = 5pF+1TTL C L = 30pF+1TTL ALL INPUT PULSES 90% Rise Time : 1V/ns 90% 10% Fall Time : 1V/ns MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE ANY CHANGE PERMITTED DOES NOT APPLY MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDAE OFF STATE AC ELECTRICAL CHARACTERISTICS (T A = -40 O C to +5 O C) READ CYCLE JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION CYCLE TIME : 55ns ( =3.0~5.5V) MIN. TYP. MAX. CYCLE TIME : 70ns ( = 2.7~5.5V) MIN. TYP. MAX. t AVAX t RC Read Cycle Time ns t AVQX t AA Address Access Time ns t E1LQV t ACS1 Chip Select Access Time () ns t E2HQV t ACS2 Chip Select Access Time () ns t GLQV t OE Output Enable to Output Valid ns t E1LQX t CLZ1 Chip Select to Output Low Z () ns t E2HQX t CLZ2 Chip Select to Output Low Z () ns t GLQX t OLZ Output Enable to Output Low Z ns t E1HQZ t CHZ1 Chip Select to Output High Z () ns t E2LQZ t CHZ2 Chip Select to Output High Z () ns t GHQZ t OHZ Output Enable to Output High Z ns t AVQX t OH Data Hold from Address Change ns UNITS 4

5 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) t RC ADDRESS t OH t AA t OH D OUT READ CYCLE 2 (1,3,4) t ACS1 D OUT t CLZ t ACS2 t CHZ1, t CHZ2 READ CYCLE 3 (1, 4) t RC ADDRESS t AA OE t OE t OH D OUT t OLZ t CLZ1 t ACS1 t ACS2 t CLZ2 t OHZ (1,5) t CHZ1 t CHZ2 (1,5) NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when = V IL and = V IH. 3. Address valid prior to or coincident with transition low and/or transition high. 4. OE = V IL. 5. Transition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. 5

6 AC ELECTRICAL CHARACTERISTICS (T A = -40 O C to +5 O C) WRITE CYCLE JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION CYCLE TIME : 55ns ( = 3.0~5.5V) MIN. TYP. MAX. CYCLE TIME : 70ns ( = 2.7~5.5V) MIN. TYP. MAX. t AVAX t WC Write Cycle Time ns t AVWL t AS Address Set up Time ns t AVWH t AW Address Valid to End of Write ns t E1LWH t CW Chip Select to End of Write ns t WLWH t WP Write Pulse Width ns t WHAX t WR1 Write Recovery Time (, WE) ns t E2LAX t WR2 Write Recovery Time () ns t WLQZ t WHZ Write to Output High Z ns t DVWH t DW Data to Write Time Overlap ns t WHDX t DH Data Hold from Write Time ns t GHQZ t OHZ Output Disable to Output in High Z ns t WHQX t OW End of Write to Output Active ns UNITS SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) ADDRESS t WC OE t WR1 (3) t CW (11) WE t AS t AW t CW (11) t WP (2) t WR2 (3) t OHZ (4,10) D OUT t DH t DW D IN 6

7 WRITE CYCLE 2 (1,6) t WC ADDRESS t CW (11) WE t AW t CW (11) t WP (2) t WR2 (3) t AS t WHZ (4,10) t OW (7) () D OUT t DW t DH (,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of and active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t WR is measured from the earlier of or WE going high or going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the low transition or the high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = V IL). 7. D OUT is the same phase of write data of this write cycle.. D OUT is the read data of next address. 9. If is low and is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. 11. t CW is measured from the later of going low or going high to the end of write. 7

8 ORDERING INFORMATION BS62LV1600 X X Z Y Y SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0 o C ~ +70 o C I: -40 o C ~ +5 o C PACKAGE E: TSOP II-44 F: BGA Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP II-44

9 PACKAGE DIMENSIONS (continued) 0.25±0.05 NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.4 Max. SIDE VIEW 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. D 0.1 N D E D1 E1 e D SOLDER BALL 0.35 ± E1 E±0.1 e VIEW A 4 mini-bga (9mm x 12mm) 9

10 Revision History Revision No. History Draft Date Remark 2.2 Add Icc1 characteristic parameter Jan. 13, 2006 Improve Iccsb1 spec. I-grade from 220uA to 100uA at 5.0V 20uA to 16uA at 3.0V C-grade from 110uA to 50uA at 5.0V 10uA to.0ua at 3.0V 2.3 Change I-grade operation temperature range May. 25, from 25 O C to 40 O C 10

BSI BH62UV8000. Ultra Low Power/High Speed CMOS SRAM 1M X 8 bit

BSI BH62UV8000. Ultra Low Power/High Speed CMOS SRAM 1M X 8 bit FEATURES Wide low operation voltage : 1.65V ~ 3.6V Ultra low power consumption : = 3.0V = 2.0V High speed access time : -70 70ns at 1.V at 5 O C Ultra Low Power/High Speed CMOS SRAM 1M X bit Operation