UTRON UT K X 8 BIT LOW POWER CMOS SRAM

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Madeleine Arnold
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1 FEATURES GENERAL DESCRIPTION Access time : 35/70ns (max) Low power consumption: Operating : 60/40 ma (typical) Standby : 3mA (typical) normal ua (typical) L-version 1uA (typical) LL-version Single 5V power supply All inputs and outputs are TTL compatible Fully static operation Three state outputs Data retention voltage : V (min) Package : 8-pin 600 mil PDIP 8-pin 330 mil SOP 8-pin 8x134mm STSOP FUNCTIONAL BLOCK DIAGRAM The UT656 is a 6,144-bit low power CMOS static random access memory organized as 3,768 words by 8 bits It is fabricated using high performance, high reliability CMOS technology The UT656 is designed for high-speed and low power application It is particularly well suited for battery back-up nonvolatile memory application The UT656 operates from a single 5V power supply and all inputs and outputs are fully TTL compatible PIN CONFIGURATION A4 A3 A14 A13 A1 A7 A6 A5 A8 I/O1 I/O8 ROW DECODER I/O CONTROL MEMORY ARRAY 51 ROWS 51 COLUMNS COLUMN I/O COLUMN DECODER VCC VSS A14 A1 A7 A6 A5 A4 A3 A A1 A0 I/O1 I/O I/O3 Vss UT Vcc WE A13 A8 A9 A11 OE A10 I/O8 I/O7 I/O6 I/O5 I/O4 LOGIC WE CONTROL OE A10 A9 A11 A A1 A0 PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A14 Address Inputs I/O1 - I/O8 Data Inputs/Outputs Chip Enable Input WE Write Enable Input OE Output Enable Input V CC Power Supply Ground V SS OE A11 A9 A8 A13 WE Vcc A14 A1 A7 A6 A5 A4 A PDIP/SOP UT A10 I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O I/O1 A0 A1 A STSOP 1

2 ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Terminal Voltage with Respect to V SS V TERM -05 to +70 V Operating Temperature T A 0 to +70 Storage Temperature T STG -65 to +150 Power Dissipation P D 1 W DC Output Current I OUT 50 ma Soldering Temperature (under 10 sec0 Tsolder 60 *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to the absolute maximum rating conditions for extended period may affect device reliability TRUTH TABLE MODE OE WE I/O OPERATION SUPPLY CURRENT Standby H X X High - Z ISB, ISB1 Output Disable L H H High - Z I CC Read L L H D OUT I CC Write L X L D IN I CC Note: H = VIH, L=VIL, X = Don't care DC ELECTRICAL CHARACTERISTICS (V CC = 5V±10%, TA = 0 to 70 ) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT Input High Voltage V IH - V CC +05 V Input Low Voltage V IL V Input Leakage Current I LI V SS V IN V CC µa Output Leakage I LO V SS V I/O V CC µa Current =V IH or OE = V IH or WE = V IL Output High Voltage V OH I OH = - 1mA V Output Low Voltage V OL I OL = 4mA V Operating Power I CC Cycle time=min, ma Supply Current I I/O = 0mA, = V IL, ma Standby Power I SB =V IH normal ma Supply Current I SB1 V CC -0V ma I SB =V IH -L/-LL ma I SB1 V CC -0V -L µa -LL µa

3 CAPACITAN (TA=5, f=10mhz) PARAMETER SYMBOL MIN MAX UNIT Input Capacitance CIN - 8 pf Input/Output Capacitance CI/O - 10 pf Note : These parameters are guaranteed by device characterization, but not production tested AC TEST CONDITIONS Input Pulse Levels 0V to 30V Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 15V Output Load C L = 100pF, I OH /I OL = -1mA/4mA AC ELECTRICAL CHARACTERISTICS (V CC = 5V±10%, TA = 0 to 70 ) (1) READ CYCLE PARAMETER SYMBOL UT UT UNIT MIN MAX MIN MAX Read Cycle Time trc ns Address Access Time taa ns Chip Enable Access Time ta ns Output Enable Access Time toe ns Chip Enable to Output in Low Z tclz* ns Output Enable to Output in Low Z tolz* ns Chip Disable to Output in High Z tchz* ns Output Disable to Output in High Z tohz* ns Output Hold from Address Change toh ns () WRITE CYCLE PARAMETER SYMBOL UT UT UNIT MIN MAX MIN MAX Write Cycle Time twc ns Address Valid to End of Write taw ns Chip Enable to End of Write tcw ns Address Set-up Time tas ns Write Pulse Width twp ns Write Recovery Time twr ns Data to Write Time Overlap tdw ns Data Hold from End of Write Time tdh ns Output Active from End of Write tow* ns Write to Output in High Z twhz* ns *These parameters are guaranteed by device characterization, but not production tested 3

4 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,,4) t RC Address t AA t OH t OH DOUT Data Valid READ CYCLE ( and OE Controlled) (1,3,5,6) trc Address taa OE ta toe tchz tclz tohz DOUT High-z tolz Data valid toh High-Z Notes : 1 WE is HIGH for read cycle Device is continuously selected =VIL 3 Address must be valid prior to or coincident with transition; otherwise taa is the limiting parameter 4 OE is LOW 5 tclz, tolz, tchz and tohz are specified with CL = 5pF Transition is measured ±500mV from steady state 6 At any given temperature and voltage condition, tchz is less than tclz, tohz is less than tolz 4

5 WRITE CYCLE 1 ( WE Controlled) (1,,3,5) Address twc taw tas tcw twp twr WE twhz High-Z tow DOUT (4) (4) tdw tdh DIN Data Valid WRITE CYCLE ( Controlled) (1,,5) twc Address taw tas tcw twr twp WE DOUT twhz (4) High-Z tdw tdh DIN Data Valid Notes : 1 WE or must be HIGH during all address transitions A write occurs during the overlap of a low and a low WE 3 During a WE controlled with write cycle with OE LOW, twp must be greater than twhz+tdw to allow the drivers to turn off and data to be placed on the bus 4 During this period, I/O pins are in the output state, and input signals must not be applied 5 If the LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high impedance state 6 t OW and t WHZ are specified with CL = 5pF Transition is measured ±500mV from steady state 5

6 DATA RETENTION CHARACTERISTICS (TA = 0 to 70 ) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT Vcc for Data Retention VDR VCC-0V 0-55 V Data Retention Current IDR Vcc=3V - L µa 0* µa VCC-0V - LL µa 5* µa Chip Disable to Data tcdr See Data Retention ns Retention Time Waveforms (below) Recovery Time t R t RC* - - ns t RC* = Read Cycle Time * Those parameters are limited for temperature below 40 DATA RETENTION WAVEFORM Data Retention Mode V CC 45V t CDR V DR V 45V t R V SS V CC -0V

7 PACKAGE OUTLINE DIMENSION 8 pin 600 mil PDIP Package Outline Dimension C UNIT SYMBOL INCH(BASE) MM(REF) A (MIN) 054 (MIN) A 0150± ±017 B 000 (MAX) 0508(MAX) B (MAX) 1397(MAX) c 001 (MAX) 0304 (MAX) D 1430 (MAX) 363 (MAX) E 06 (TYP) 154 (TYP) E1 05 (MAX) 1308 (MAX) e 0100 (TYP) 540(TYP) eb 065 (MAX) 1587 (MAX) L 0180(MAX) 457(MAX) S 006 (MAX) 154 (MAX) Q1 008(MAX) 03(MAX) Θ 15 o (MAX) 15 o (MAX) 7

8 8 pin 330 mil SOP Package Outline Dimension B C E UNIT SYMBOL INCH(BASE) MM(REF) A 010 (MAX) 3048 (MAX) A1 000(MIN) 005(MIN) A 0098± ±017 b (TYP) 0406(TYP) c 0010 (TYP) 054(TYP) D 078 (MAX) (MAX) E 0340 (MAX) 8636 (MAX) E1 0465± ±0305 e 0050 (TYP) 170(TYP) L 005 (MAX) 170 (MAX) L1 0067± ±003 S 0047 (MAX) 1194 (MAX) y 0003(MAX) 0076(MAX) Θ 0 o 10 o 0 o 10 o 8

9 8 pin 8mmx134mm STSOP Package Outline Dimension Note: E dimension is not including end flash the total of both sides end flash is not above 03mm 5 UNIT SYMBOL INCH(BASE) MM(REF) A 0047 (MAX) 10 (MAX) A1 0004± ±005 A 0039± ±005 b 0006 (TYP) 015(TYP) c 0010 (TYP) 054(TYP) Db 0465± ±010 E 0315± ±010 e 00 (TYP) 055(TYP) D 058± ±00 L 000± ±010 L ± ±010 y 008(MAX) 0003(MAX) Θ 0 o 5 o 0 o 5 o 9

10 ORDERING INFORMATION PART NO ACSS TIME STANDBY CURRENT PACKAGE (ns) (µa) UT656PC ma 8PIN PDIP UT656PC-70L µa 8PIN PDIP UT656PC-70LL µa 8PIN PDIP UT656SC ma 8PIN SOP UT656SC-35L µa 8PIN SOP UT656SC-35LL µa 8PIN SOP UT656SC ma 8PIN SOP UT656SC-70L µa 8PIN SOP UT656SC-70LL µa 8PIN SOP UT656LS-35L µa 8PIN STSOP UT656LS-35LL µa 8PIN STSOP UT656LS-70L µa 8PIN STSOP UT656LS-70LL µa 8PIN STSOP

11 REVISION HISTORY REVISION DESCRIPTION DATE REV 10 Original REV 11 The value of symbol E is revised as 035 inch AUG 4,1999 REV 1 Combine version_ut656(normal) and DEC 8,1999 version_ut656sc-35 into version_ut656 REV 14 1 The pin configurations name of TSOP-1 is revised as MAY 10,001 STSOP The data retention waveform, V CC -0V(page 6) REV 15 Add data retention current for temperature below 40 JUL11,001

LY K X 8 BIT LOW POWER CMOS SRAM

LY K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Description Issue Date Rev. 1.0. Initial Issue Jul.25.2004 Rev. 2.0. Revised Vcc Range(Vcc=4.5~5.5V => 2.7~5.5V) May.4.2005 Rev. 2.1. Revised ISB1 May.13.2005 Rev. 2.2 Adding