SRAM AS5C K x 8 SRAM Ultra Low Power SRAM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATION FEATURES GENERAL DESCRIPTION

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1 512K x 8 Ultra Low Power AVAILABLE AS MILITARY SPECIFICATION SMD ,2 MIL STD FEATURES Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby) Fully Static, No Clocks Single +5V ±10% power supply Easy memory expansion with and OE\ options All inputs and outputs are TTL-compatible Three state outputs Operating temperature range: Ceramic -55 o C to +125 o C & -40 o C to +85 o C Plastic -40 o C to +85 o C 3 1. Not applicable to plastic package 2. Applies to CW package only. 3. Contact factory for -55 o C to +125 o C OPTIONS MARKING Timing 55ns access ns access ns access ns access -100 Packages Ceramic Dip (600 mil) CW No. 112 Ceramic SOJ 5 ECJ No. 502 Plastic TSOP DG No Options 2V data retention/very low power L 4. For DG package, contact factory 5. Contact Factory NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availability of specifi c part number combinations. Pin Name WE\ OE\ A0 - A18 I/O1 - I/O8 Vcc Vss Function Write Enable Input Chip Select Input Output Enable Input Address Inputs Data Inputs/Outputs Power Ground For more products and information please visit our web site at A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/01 I/02 I/03 Vss PIN ASSIGNMENT (Top View) 32-Pin DIP, 32-Pin SOJ & 32-Pin TSOP Vcc A15 A17 WE\ A13 A8 A9 A11 OE\ A10 I/08 I/07 I/06 I/05 I/04 GENERAL DESCRIPTION The is organized as 524,288 x 8 utilizing a special ultra low power design process. Micross pinout adheres to the JEDEC standard for pinout on 4 megabit s. The evolutionary 32 pin version allows for easy upgrades from the 1 meg design. For flexibility in memory applications, Micross offers chip enable () and output enable (OE\) capabilities. These features can place the outputs in High-Z for additional flexibility in system design. This devices operates from a single +5V power supply and all inputs and outputs are fully TTL-compatible. Writing to these devices is accomplished when write enable (WE\) and inputs are both LOW. Reading is accomplished when WE\ remains HIGH and and OE\ go LOW. The device offers a reduced power standby mode when disabled, by lowering VCC to 2V and maintaining = 2V. This allows system designers to meet ultra low standby power requirements. 1

2 FUNCTIONAL BLOCK DIAGRAM Clk. gen. Precharge circuit A18 A16 A14 A12 A7 A6 A5 A4 A1 A0 Row select Memory Array 1024 rows 512 x 8 columns I/O1 I/O8 Data cont I/O Circuit Column Select Data cont A9 A8 A13 A17 A15 A10 A11 A3 A2 WE\ OE\ Control logic 2

3 ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss...-.5V to +7.0V Voltage on any pin Relative to Vss...-.5V to +7.0V Storage Temperature C to +150 C Operating Temperature Range o C to +125 o C Soldering Temperature Range o C Maximum Junction Temperature** C Power Dissipation...1.0W *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55 o C < T A < 125 o C; Vcc = 5V +10%) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Input Leakage Current (V IN = V SS to V CC ) I LI -5 5 μα Output Leakage Current (=V IH or OE\=V IH or WE\=V IL, V IO =V SS to V CC ) I LO -5 5 μα Output Low Voltage (I OL = 2.1mA) V 15 Output High Voltage (I OH = -1.0 ma) V 15 V OL V OH Supply Voltage V V CC 15 Input High (Logic 1) Voltage 2.2 Vcc +0.5 V 1, 15 Input Low (Logic 0) Voltage V IL V 2, 15 V IH PARAMETER Power Supply Current: Operating Power Supply Current: Standby TTL CMOS MAX CONDITIONS SYM UNITS NOTES Cycle Time = Min., 100% Duty Cycle, I IO = 0mA, I cc ma 3 = V IL, V IN = V IH or V IL = V IH, Other inputs = V IL or V IH I SB ma = Vcc -0.2V, Other inputs = 0 ~ Vcc I SB ma 3

4 CAPACITANCE PARAMETER CONDITIONS SYMBOL MAXIMUM UNITS NOTES Input Capacitance T A = 25 o C, f = 1MHz V IN =0V C IN 8 pf 4 Input/Output Capactiance V CC = 5V V IO =0V C IO 10 pf 4 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55 o C < T A < 125 o C; Vcc = 5V +10%) DESCRIPTION SYM MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES READ Cycle READ cycle Time t RC ns Address access time t AA ns Chip Enable access time t ACE ns Output hold from address change t OH ns Chip Enable to output in Low-Z t LZCE ns 4,6 Chip disable to output in High-Z t HZCE ns 4,6 Chip Enable to power-up time t PU ns 4 Chip disable to power-down time t PD ns 4 Output Enable access time t AOE ns Output Enable to output in Low-Z t LZOE ns 4,6 Output disable to output in High-Z t HZOE ns 4,6 WRITE Cycle WRITE cycle time t WC ns Chip Enable to end of write t CW ns Address valid to end of write t AW ns Address setup time t AS ns Address hold from end of write t AH ns WRITE pulse width t WP ns Data setup time t DS ns Data hold time t DH ns Write disable to output in Low-Z t LZWE ns 4,6 Write Enable to output in High-Z t HZWE ns 4,6 4

5 AC TEST CONDITIONS Input pulse levels... Vss to 3.0V Input rise and fall times... 3ns Input timing reference levels V Output reference levels V Output load... See Figures 1 Q ohms ohms C C=30pF = 100pF 1.73V Fig. 1 Output Load Equivalent NOTES 1. Overshoot: Vcc +3.0V for pulse width < 20ms. 2. Undershoot: -3V for pulse width < 20ms. 3. I CC is dependent on output loading and cycle rates. 4. This parameter is guaranteed but not tested. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. At any given temperature and voltage condition, t HZCE is less than t LZCE, and t HZWE is less than t LZWE. 7. WE\ is HIGH for READ cycle. 8. Device is continuously selected. Chip enables and output enables are held in their active state. 9. Address valid prior to, or coincident with, latest occurring chip enable. 10. t RC = Read Cycle Time. 11. Chip enable and write enable can initiate and terminate a WRITE cycle. 12. Output enable (OE\) is inactive (HIGH). 13. Output enable (OE\) is active (LOW). 14. ASI does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150 C. Care should be taken to limit power to acceptable levels. 15. All voltage referenced to Vss (GND). DATA RETENTION ELECTRICAL CHARACTERISTICS DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES V CC for Retention Data V DR 2 V Data Retention Current Chip Deselect to Data Retention Time > (V CC - 0.2V) V CC = 2V I CCDR 100 μa V IN > (V CC - 0.2V) V CC = 3V I CCDR 200 μa t CDR 0 ns 4 Operation Recovery Time t R 5 ms 4, 10 5

6 Controlled V CC 4.5V LOW V CC DATA RETENTION WAVEFORM t SDR Data Retention t RDR 2.2V V DR GND > Vcc - 0.2V READ CYCLE NO. 1 1 (Address Controlled, = OE\ = V IL, WE\ = V IH ) ADDRESS t RC t OH t AA DATA OUT Previous Data Valid Data Valid READ CYCLE NO. 2 2 (WE\ = V IH ) ADDRESS t RC t AA t OH t CO1 t OE t HZ OE\ t OHZ t OLZ DATA OUT High-Z t LZ Data Valid 6 Don t Care Undefined

7 WRITE CYCLE NO. 1 (WE Controlled) ADDRESS t WC t CW(4) t AW WE\ t WP(3) t DW t DH DATA IN Data Valid DATA OUT Data Undefined t WHZ t OW WRITE CYCLE NO. 2 (Write Enabled Controlled) ADDRESS t WC t CW(4) t AW WE\ t WP(3) t DW t DH DATA IN Data Valid DATA OUT High-Z High-Z NOTES: 1. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature adn voltage condition, thz (MAX) is less than tlz (MIN) both for a given device and from device to device interconnection. 3. A write occurs during the overlap of a low adn a low WE\. A write begins at the latest transistion among going Low and WE\ going Low: A write end at the earliest transistion among going High and WE\ going High, twp is measured from the beginning of write to the end of write. 4. tcw is measured from the going Low to end of write. 5. tas is measured from the address valid to the beginning of write. 6. twr is measure from the end of write to the address change. twr applied in case a write ends are or WE\ going High. 7

8 MECHANICAL DEFINITION* Micross Case #112 (Package Designator CW) D A L L1 Pin 1 e b b1 E E1 b2 MICROSS PACKAGE SPECIFICATIONS SYMBOL MIN MAX A b b b D E E e L L *All measurements are in inches. 8

9 MECHANICAL DEFINITION* Micross Case #502 (Package Designator ECJ) A b2 b1 e D1 D L b E1 A1 E MICROSS SPECIFICATIONS SYMBOL MIN MAX A A A b D D E E e BSC L L *All measurements are in inches. 9

10 MECHANICAL DEFINITION* Micross Case #1002 (Package Designator DG) ± TYP ~ / MAX ± ± MAX MAX MIN TYP ± TYP *All measurements are in inches. 10

11 ORDERING INFORMATION EXAMPLE: CW-55L/XT 1 EXAMPLE: ECJ-85L/883C 1 Device Number Package Speed Package Speed Options** Process Device Number Type ns Type ns Options** Process CW -55 L /* ECJ -55 L /* CW -70 L /* ECJ -70 L /* CW -85 L /* ECJ -85 L /* CW -100 L /* ECJ -100 L /* EXAMPLE: DG-70/IT 2 Device Number Package Speed Type ns Options** Process DG -55 L /* DG -70 L /* DG -85 L /* DG -100 L /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing -40 o C to +85 o C -55 o C to +125 o C -55 o C to +125 o C ** OPTIONS L = 2V Data Retention/Ultra Low Power NOTES: 1. All CSOJ devices, please consult factory. Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availability of specific part number combinations. 2. Plastic devices not available as 883. For XT or 55ns devices, contact factory. 11

12 MICROSS TO DSCC PART NUMBER CROSS REFERENCE FOR Package Designator CW Micross Part # SMD Part CW-120/H HYA CW-120L/H HYA CW-100/H HYA CW-100L/H HYA CW-85/H HYA CW-85L/H HYA CW-70/H HYA CW-70L/H HYA CW-120/H CW-120L/H CW-100/H CW-100L/H CW-85/H CW-85L/H CW-70/H CW-70L/H HYC HYC HYC HYC HYC HYC HYC HYC * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. 12

P4C1041 HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM

P4C1041 HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) 10/12/15/20 ns (Commercial) 12/15/20 ns (Industrial/Military) Low Power Single 5.0V ± 10% Power Supply 2.0V