Very Low Power/Voltage CMOS SRAM 1M X 16 bit DESCRIPTION. SPEED (ns) 55ns : 3.0~3.6V 70ns : 2.7~3.6V BLOCK DIAGRAM

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1 Very Low Power/Voltage CMOS SRAM 1M X 16 bit (Dual CE Pins) FEATURES operation voltage : 27~36V Very low power consumption : = 30V C-grade: 45mA (@55ns) operating current I -grade: 46mA (@55ns) operating current C-grade: 36mA (@70ns) operating current I -grade: 37mA (@70ns) operating current 30uA (Typ) CMOS standby current High speed access time : ns ns Automatic power down when chip is deselected Three state outputs and TTL compatible Fully static operation Data retention supply voltage as low as 15V Easy expansion with, and OE options I/O Configuration x8/x16 selectable by LB and UB pin DESCRIPTION The is a high performance, very low power CMOS Static Random Access Memory organized as 1,048,576 words by 16 bits and operates from a range of 27V to 36V supply voltage Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 30uA at 30V/25 o C and maximum access time of 55ns at 30V/85 o C Easy memory expansion is provided by an active LOW chip enable(), active HIGH chip enable (), active LOW output enable(oe) and three-state output drivers The has an automatic power down feature, reducing the power consumption significantly when chip is deselected The is available in 48-pin BGA package PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE RANGE SPEED (ns) 55ns : 30~36V 70ns : 27~36V POWER DISSIPATION STANDBY (ICCSB1, Max) =3V Operating (ICC, Max) =3V =3V PKG TYPE FC +0 O C to +70 O C 27V ~ 36V 55 / ua 45mA 36mA BGA FI -40 O C to +85 O C 27V ~ 36V 55 / ua 46mA 37mA BGA ns 70ns PIN CONFIGURATIONS BLOCK DIAGRAM A B C D E F G H LB OE A0 A1 A2 D8 UB A3 A4 D0 D9 D10 A5 A6 D1 D2 VSS D11 A17 A7 D3 VCC VCC D12 NC A16 D4 VSS D14 D13 A14 A15 D5 D6 D15 A19 A12 A13 WE D7 A18 A8 A9 A10 A11 NC A4 A3 A2 A1 A0 A17 A16 A15 A14 A13 A12 D0 D15 WE OE UB LB Vss Address Input Buffer Control 22 Row Decoder Data Input Buffer Data Output Buffer Memory Array 2048 x Column I/O Write Driver Sense Amp 512 Column Decoder 18 Address Input Buffer A11 A10 A9 A8 A7 A6 A5A18 A19 48-Ball CSP top View Brilliance Semiconductor, Inc reserves the right to modify document contents without notice R0201- Downloaded from Elcodiscom electronic components distributor 1

2 PIN DESCRIPTIONS Name A0-A19 Address Input Function These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM Chip Enable 1 Input Chip Enable 2 Input WE Write Enable Input OE Output Enable Input LB and UB Data Byte Control Input is active LOW and is active HIGH Both chip enables must be active when data read from or write to the device If either chip enable is not active, the device is deselected and is in a standby power mode The DQ pins will be in the high impedance state when the device is deselected The write enable input is active LOW and controls read and write operations With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location The output enable input is active LOW If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled The DQ pins will be in the high impedance state when OE is inactive Lower byte and upper byte data input/output control pins D0 - D15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM Power Supply Vss Ground TRUTH TABLE MODE WE OE LB UB D0~D7 D8~D15 CURRENT Not selected H X X X X X High Z High Z ICCSB, I CCSB1 (Power Down) X L X X X X High Z High Z ICCSB, I CCSB1 Output Disabled L H H H X X High Z High Z ICC Read L H H L L L Dout Dout ICC H L High Z Dout ICC L H Dout High Z ICC Write L H L X L L Din Din ICC H L X Din ICC ABSOLUTE MAXIMUM RATINGS (1) SYMBOL RATING UNITS VTERM Terminal Voltage with Respect to GND -05 to +05 TBIAS Temperature Under Bias -40 to +85 TSTG Storage Temperature -60 to +150 PT Power Dissipation 10 W IOUT DC Output Current 20 ma 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability L H Din X ICC V O C O C OPERATING RANGE RANGE AMBIENT TEMPERATURE Commercial 0 O C to +70 O C 27V ~ 36V Industrial -40 O C to +85 O C 27V ~ 36V CAPACITANCE (1) (TA = 25 o C, f = 10 MHz) SYMBOL CONDITIONS MAX UNIT CIN Input Capacitance VIN=0V 10 pf CDQ Input/Output Capacitance VI/O=0V 12 pf 1 This parameter is guaranteed and not 100% tested R0201- Downloaded from Elcodiscom electronic components distributor 2

3 DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85 o C ) VIL VIH BSI TEST CONDITIONS MIN TYP (1) MAX UNITS Guaranteed Input Low -- Voltage (3) =3V V Guaranteed Input High Voltage (3) =3V V IIL Input Leakage Current = Max, VIN = 0V to ua ILO Output Leakage Current = Max, = VIH, or = V il, or OE = VIH, VI/O = 0V to ua VOL Output Low Voltage = Max, IOL= 2mA =3V V VOH Output High Voltage = Min, IOH= -1mA =3V V (4) ICC Operating Power Supply Current = VIL and = 55ns VIH =3V, IDQ = 0mA, F = Fmax (2) 70ns ma ICCSB Standby Current-TTL = VIH or = VIL, IDQ = 0mA =3V ma ICCSB1 Standby Current-CMOS -02V or 02V ;VIN - 02V or VIN 02V =3V ua 1 Typical characteristics are at TA = 25 o C 2 Fmax = 1/t RC 3 These are absolute values with respect to device ground and all overshoots due to system or tester notice are included 4 Icc_Max is 45mA(@55ns) / 36mA(@70ns) during 0~70 o C operation 5 IccsB1 is 10uA at =30V and TA=70 o C DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85 o C ) (1) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS V DR for Data Retention - 02V or 02V, VIN - 02V or VIN 02V V (3) I CCDR t CDR t R Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time - 02V or 02V, VIN - 02V or VIN 02V See Retention Waveform ua ns (2) T RC ns 1 = 15V, T A = + 25 O C 2 t RC = Read Cycle Time 3 IccDR(Max) is 25uA at TA=70 O C LOW V CC DATA RETENTION WAVEFORM (1) ( Controlled ) Data Retention Mode VDR 15V t CDR t R VIH - 02V VIH LOW V CC DATA RETENTION WAVEFORM (2) ( Controlled ) Data Retention Mode VDR 15V t CDR t R VIL 02V VIL R0201- Downloaded from Elcodiscom electronic components distributor 3

4 AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS Input Pulse Levels / 0V WAVEFORM INPUTS OUTPUTS Input Rise and Fall Times 1V/ns MUST BE STEADY MUST BE STEADY Input and Output Timing Reference Level Output Load 05 C L = 30pF+1TTL C L = 100pF+1TTL MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H, DON T CARE: ANY CHANGE PERMITTED WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85 o C ) READ CYCLE JEDEC CYCLE TIME : 70ns CYCLE TIME : 55ns DESCRIPTION = 27~36V = 30~36V MIN TYP MAX MIN TYP MAX UNIT t AVAX t RC Read Cycle Time ns t AVQV t AA Address Access Time ns t ELQV t ACS1 Chip Select Access Time () ns t ELQV t ACS2 Chip Select Access Time () ns t BA t (1) BA Data Byte Control Access Time (LB,UB) ns t GLQV t OE Output Enable to Output Valid ns t ELQX t CLZ Chip Select to Output Low Z (,) ns t BE t BE Data Byte Control to Output Low Z (LB,UB) ns t GLQX t OLZ Output Enable to Output in Low Z ns t EHQZ t CHZ Chip Deselect to Output in High Z (,) ns t BDO t BDO Data Byte Control to Output High Z (LB,UB) ns t GHQZ t OHZ Output Disable to Output in High Z ns t AXOX t OH Data Hold from Address Change ns NOTE : 1 tba is 35ns/30ns (@speed=70ns/55ns) with address toggle tba is 70ns/55ns (@speed=70ns/55ns) without address toggle R0201- Downloaded from Elcodiscom electronic components distributor 4

5 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t OH t AA t OH READ CYCLE2 (1,3,4) t ACS2 t ACS1 t CLZ t CHZ READ CYCLE3 (1,4) t RC ADDRESS t AA OE t OE t OH t ACS2 t OLZ t ACS1 t CLZ t OHZ (1,5) t CHZ LB,UB t BE t BA t BDO NOTES: 1 WE is high in read Cycle 2 Device is continuously selected when = VIL and = VIH 3 Address valid prior to or coincident with transition low 4 OE = VIL 5 The parameter is guaranteed but not 100% tested R0201- Downloaded from Elcodiscom electronic components distributor 5

6 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85 o C ) WRITE CYCLE JEDEC DESCRIPTION SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t AVAX t WC Write Cycle Time ns t E1LWH t CW Chip Select to End of Write ns t AVWL t AS Address Setup Time ns t AVWH t AW Address Valid to End of Write ns t WLWH t WP Write Pulse Width ns t WHAX t WR Write recovery Time (,,WE) ns (1) t BW t BW Date Byte Control to End of Write (LB,UB) ns t WLQZ t WHZ Write to Output in High Z ns t DVWH t DW Data to Write Time Overlap ns t WHDX t DH Data Hold from Write Time ns t GHQZ t OHZ Output Disable to Output in High Z ns t WHOX t OW End of Write to Output Active ns ADDRESS t WC CYCLE TIME : 70ns CYCLE TIME : 55ns = 27~36V = 30~36V MIN TYP MAX MIN TYP MAX NOTE : 1 tbw is 30ns/25ns (@speed=70ns/55ns) with address toggle ; tbw is 70ns/55ns (@speed=70ns/55ns) without address toggle (3) t WR UNIT OE (11) t CW LB,UB t BW t AW (3) WE t AS (4,10) t OHZ t WP (2) t DH t DW D IN R0201- Downloaded from Elcodiscom electronic components distributor 6

7 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t CW LB,UB t BW WE t AS t AW (4,10) t WHZ t WP (2) t WR (3) t OW (7) (8) t DW t DH (8,9) D IN NOTES: 1 WE must be high during address transitions 2 The internal write time of the memory is defined by the overlap of, and WE low All signals must be active to initiate a write and any one signal can terminate a write by going inactive The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write 3 TWR is measured from the earlier of going low, or or WE going high at the end of write cycle 4 During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied 5 If the high transition or low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state 6 OE is continuously low (OE = VIL ) 7 DOUT is the same phase of write data of this write cycle 8 DOUT is the read data of next address 9 If is high or is low during this period, DQ pins are in the output state Then the data input signals of opposite phase to the outputs must not be applied to them 10 The parameter is guaranteed but not 100% tested 11 TCW is measured from the later of going high or going low to the end of write R0201- Downloaded from Elcodiscom electronic components distributor 7

8 ORDERING INFORMATION X X Z Y Y SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0 o C ~ +70 o C I: -40 o C ~ +85 o C PACKAGE F :BGA Note: BSI (Brilliance Semiconductor Inc) assumes no responsibility for the application or use of any product or circuit described herein BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments PACKAGE DIMENSIONS 14 Max SIDE VIEW 025± 005 NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS 3375 D 01 D1 N D E D1 E1 e SOLDER BALL 035± E1 ± E 01 e VIEW A 48 mini-bga (9mm x 12mm) R0201- Downloaded from Elcodiscom electronic components distributor 8

Very Low Power/Voltage CMOS SRAM 512K X 16 bit DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) 55ns : 3.0~5.5V 70ns : 2.7~5.5V

Very Low Power/Voltage CMOS SRAM 512K X 16 bit DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) 55ns : 3.0~5.5V 70ns : 2.7~5.5V FEATURES Wide operation voltage : 24~55V Very low power consumption : = 30V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: