4M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014
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1 Revision History Rev. No. History Issue Date 1.0 Initial issue Apr.15, Rev. 1.0
2 GENERAL DESCRIPTION The and are a 4,194,304-bit high-speed Static Random Access Memory organized as 256K(512) words by 16(8) bits. The () uses 16(8) common input and output lines and have an output enable pin which operates faster than address access time at read cycle, And allows that lower and upper byte access by data byte control(ub, LB ).The device is fabricated using advanced CMOS process,6-tr based cell technology and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The is packaged in a 400mil 44-pin TSOP2 and 48FBGA. The is packaged in a 400mil 44-pin TSOP2 and 36FBGA. FEATURES Fast Access Time 8,10,12,15ns(Max) CMOS Low Power Dissipation Standby (TTL): 10mA (Max.) (CMOS): 6mA (Max.) Operating: 35mA (8ns, Max..) : 30mA(10ns,Max.) Single 3.3±0.3V or 5.0±0.5V Power Supply Wide range (1.65V~3.6V) of Power Supply TTL Compatible inputs and Outputs Fully Static Operation, No Clock or Refresh required Three State Outputs Data Byte Control(x16 Mode) LB : I/O 0 ~I/O 7,UB : I/O 8 ~I/O 15 Standard 44TSOP2 and 36FBGA Package Pin Configuration for 512k x 8 Standard 44TSOP2 and 48FBGA Package Pin Configuration for 256k x 16 Operating in Commercial and Industrial Temperature range. 2 Rev. 1.0
3 Order Information Speed Density Org. Part Number V CC (V) t AA (ns) t OE (ns) Package CS16FS40963GC(I) TSOP2 CS16FS4096WGC(I) TSOP2 CS16FS4096WGC(I) TSOP2 CS16FS4096WGC(I) TSOP2 CS16FS40963HC(I) FBGA CS16FS4096WHC(I) FBGA CS16FS4096WHC(I) FBGA CS16FS4096WHC(I) FBGA 4Mb 256Kx16 CS16FS40965GC(I) TSOP2 CS16FS40963GC(I) TSOP2 CS16FS4096WGC(I) TSOP2 CS16FS4096WGC(I) TSOP2 CS16FS4096WGC(I) TSOP2 CS16FS40963HC(I) FBGA CS16FS4096WHC(I) FBGA CS16FS4096WHC(I) FBGA CS16FS4096WHC(I) FBGA Temp. C : Commercial I : Industrial Speed Density Org. Part Number V CC (V) t AA (ns) t OE (ns) Package CS18FS40963GC(I) TSOP2 CS18FS4096WGC(I) TSOP2 CS18FS4096WGC(I) TSOP2 4Mb CS18FS4096WGC(I) TSOP2 512Kx8 CS18FS40963YC(I) FBGA CS18FS4096WYC(I) FBGA CS18FS4096WYC(I) FBGA CS18FS4096WYC(I) FBGA Temp. C : Commercial I : Industrial 3 Rev. 1.0
4 CS18FS40965GC(I) TSOP2 CS18FS40963GC(I) TSOP2 CS18FS4096WGC(I) TSOP2 CS18FS4096WGC(I) TSOP2 CS18FS4096WGC(I) TSOP2 CS18FS40963YC(I) FBGA CS18FS4096WYC(I) FBGA CS18FS4096WYC(I) FBGA CS18FS4096WYC(I) FBGA PIN CONFIGURATIONS 44TSOP2-400mil 4 Rev. 1.0
5 6x8mm mini-bga with ball pitch 0.75mm (512k x 8) (256k x 16) 36 ball mini-bga 48ball mini-bga FUNCTIONAL BLOCK DIAGRAM (512k x 8) (256k x 16) 5 Rev. 1.0
6 Absolute Maximum Ratings* Voltage on Any Pin Relative to V SS Parameter Symbol Rating Unit 3.3V Product 5.0V Product Wide V CC ** Product V in, V OUT -0.5 to V CC +0.5V V Voltage on V CC 3.3V Product -0.5 to 4.6 Supply Relative to 5.0V Product V in, V OUT -0.5 to 7.0 V V SS Wide V CC ** Product -0.5 to 4.6 Power Dissipation P D 1.0 W Storage Temperature T STG -65 to 150 C Operating Temperature Commercial T A 0 to 70 C Industrial T A -40 to 85 C *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Wide VCC Range is 1.65V~3.6V Recommended DC Operating Conditions*(T A =0 to 70 ) Parameter Operating V CC (V) Symbol Min. Typ. Max. Unit 5.0 V CC Supply Voltage 3.3 V CC Wide 2.4~3.6 V CC / V Wide 1.65~2.2 V CC Ground V SS V 5.0 V IH V CC +0.5 Input High Voltage 3.3 V IH V CC +0.5 V Wide 2.4~3.6 V IH V CC +0.3 Wide 1.65~2.2 V IH V CC V IL Input Low Voltage 3.3 V IL V Wide 2.4~3.6 V IL Rev. 1.0
7 Wide 1.65~2.2 V IL *The above parameters are also guaranteed for industrial temperature range. DC and Operating Characteristics*(T A =0 to 70 ) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current Output Leakage Current** Operating Current** Standby Current Output Low Voltage Level I LI V IN =V SS to V CC -2 2 ua I LO I CC CS =V IH or OE =V IH or WE =V IL V OUT =V SS to V CC Min.Cycle,100% Duty CS =V IL, V IN =V IH or V IL,I OUT = 0mA -2 2 ua 8ns 35 10ns 12ns ns 25 I SB Min. Cycle, CS =V IH - 10 I SB1 V OL f=0mhz, CS V CC -0.2V V IN V CC -0.2V or V in 0.2V - 6 V CC =4.5V, I OL =8mA, 5.0V Product V CC =3.0V, I OL =8mA, 3.3V Product & Wide V CC ** Product V CC =2.4V, I OL =1mA, Wide V CC ** Product V CC =1.65V, I OL =0.1mA, Wide V CC ** Product V CC =4.5V, I OH = -4mA, 5.0V Product ma ma V Output High Voltage Level V OH V CC =3.0V, I OH = -4mA, 3.3V Product & Wide V CC ** Product V CC =2.4V, I OH = -1mA, Wide V CC ** Product V CC =1.65V, I OH = -0.1mA, Wide V CC ** Product *The above parameters are also guarantee for industrial temperature range. V **Wide V CC Range is 1.65V ~ 3.6V 7 Rev. 1.0
8 Capacitance*(T A = 25, f= 1.0MHz) Item Symbol Test Conditions TYP Max Unit Input/ Output Capacitance C I/O V I/O =0V - 8 pf Input Capacitance C IN V IN =0V - 6 pf *Capacitance is sampled and not 100% tested. Test Conditions* Parameter Value 0 to 3.0V (V CC =3.3V or 5.0V) Input/ Output Capacitance 0 to 2.5V (V CC =2.5V) 0 to 1.8V (V CC =1.8V) Input Rise and Fall Time 1V/1ns Input and Output Timing Reference Levels 1.5V (V CC =3.3V or 5.0V) 1/2V CC (V CC = 1.8V or 2.5V) Output Load See Fig. 1 *The above parameters are also guaranteed for industrial temperature range. 8 Rev. 1.0
9 Functional Description (x8 Mode) CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z I SB,I SB1 L H H Output Disable High-Z I CC L H L Read D OUT I CC L L X Write D IN I CC *X means don t care Functional Description (x16 Mode) CS WE OE LB ** UB ** Mode I/O Pin I/O 0 ~I/O 7 I/O 8 ~I/O 15 Supply Current H X X* X X Not Select High-Z High-Z I SB, I SB1 L H H X X Output High-Z High-Z I CC L X X H H Disable L H D OUT High-Z L H L H L Read High-Z D OUT I CC L L X L L D OUT D OUT L H D IN High-Z H L Write High-Z D IN L L D IN D IN I CC *X means don t care 9 Rev. 1.0
10 Data Retention Characteristics*(T A =0 to 70 ) Parameter V CC for Data Retention Data Retention Current Product 5.0V Product 3.3V Product Wide 2.4V~3.6V Wide 1.65V~2.2V 5.0V Product 3.3V Product Wide 2.4V~3.6V Wide 1.65V~2.2V Operating V CC (V) 5.0 Symbol Test Condition Min. Typ. Max. Unit V DR CS V CC - 0.2V 2.5/ V CC =2.0V CS V CC - 0.2V V IN V CC - 0.2V or /3.3 I DR V IN 0.2V V CC =1.5V,CS V CC - 0.2V, V IN V CC - 0.2V or V IN 0.2V Data Retention Set-Up Time t SDR See Data ns Recovery Time t RDR Retention Wave form (below) ms V ma Data Retention Wave form 10 Rev. 1.0
11 Read Cycle* Parameter Symbol 8ns 10ns 12ns 15ns Min Max Min Max Min Max Min Max Unit Read Cycle Time t RC ns Address Access Time t AA ns Chip Select to Output t CO ns Output Enable to Valid Output t OE ns UB, LB Access Time** t BA ns Chip Enable to Low-Z Output t LZ ns Output Enable to Low-Z Output t OLZ ns UB, LB Enable to Low-Z Output** Chip Disable to High-Z Output Output Disable to High-Z Output UB, LB Disable to High-Z Output** Output Hold from Address Change Chip Selection Power Up Time Chip Selection Power Down Time t BLZ ns t HZ ns t OHZ ns t BHZ ns t OH ns t PU ns t PD ns *The above parameters are also guaranteed for industrial temperature range. 11 Rev. 1.0
12 Write Cycle* Parameter Symbol 8ns 10ns 12ns 15ns Min Max Min Max Min Max Min Max Write Cycle Time t WC ns Chip Select to End of Write Unit t CW ns Address Set-up Time t AS ns Address Valid to End of Write Write Pulse Width( OE High) Write Pulse Width( OE Low) UB, LB Valid to End of Write** t AW ns t WP ns t WP ns t BW ns Write Recovery Time t WR ns Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z t WHZ ns t DW ns t DH ns t OW ns *The above parameters are also guaranteed for industrial temperature range. 12 Rev. 1.0
13 Timing Diagram Timing Waveform of Read Cycle (1) (Address Controlled, CS =OE =V IL, WE =V IH,UB, LB =V IL **) ** Those parameters are applied for x16 mode only. Timing Waveform of Read Cycle (2) (WE =VIH) NOTES (Read Cycle) 1. WE is high for read cycle 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or V OL levels. 4. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from 13 Rev. 1.0
14 device to device. 5. Transition is measured ±200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS =V IL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. ** Those parameters are applied for x16 mode only. Timing Waveform of Write Cycle (1) ( OE Clock) ** Those parameters are applied for x16 mode only. 14 Rev. 1.0
15 Timing Waveform of Write Cycle (2) ( OE =Low fixed) ** Those parameters are applied for x16 mode only. Timing Waveform of Write Cycle (3) ( CS =Controlled) ** Those parameters are applied for x16 mode only. 15 Rev. 1.0
16 Timing Waveform of Write Cycle (4) (UB, LB Controlled) NOTES (Write Cycle) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. t WP is measured from the beginning of write to the end of write. 3. t CW is measured from the later of CS going low to end of write. 4. t AS is measured from the address valid to the beginning of write. 5. WE is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. IfOE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. D OUT is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. ** Those parameters are applied for x16 mode only 16 Rev. 1.0
17 Package outline dimensions 44L-TSOP2-400mil 17 Rev. 1.0
18 36ball mini-bga-6x8mm (ball pitch: 0.75mm) 18 Rev. 1.0
19 48ball mini-bga-6x8mm (ball pitch: 0.75mm) 19 Rev. 1.0
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TOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
TOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 DESCRIPTION The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and
SRM2B256SLMX55/70/10
256K-BIT STATIC RAM Wide Temperature Range Extremely Low Standby Current Access Time 100ns (2.7V) 55ns (4.5V) 32,768 Words 8-Bit Asynchronous DESCRIPTION The SRM2B256SLMX is a low voltage operating 32,768
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55YEM216ABXN is a 4,194,304-bit static random access memory (SRAM) organized
PRELIMINARY C106A 1. 7C106A 12 7C106A 15 7C106A 20 7C106A 25 7C106A 35 Maximum Access Time (ns) Maximum Operating
1CY 7C10 6A Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 910 mw Low standby power 275 mw 2.0V data retention (optional) 100 µw Automatic power-down when deselected TTL-compatible
IS62WV25616EALL/EBLL/ECLL IS65WV25616EBLL/ECLL. 256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM JANUARY 2018
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2018 KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current:
HY62WT08081E Series 32Kx8bit CMOS SRAM
32Kx8bit CMOS SRAM Document Title 32K x8 bit 2.7~5.5V Low Power Slow SRAM Revision History Revision No History Draft Date Remark 00 Initial Feb.05.2001 Preliminary 01 Revised Feb.13.2001 Final - Change
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005 FEATURES IS61C6416AL and High-speed access time: 12 ns, 15ns Low Active Power: 175 mw (typical) Low Standby Power: 1 mw (typical) CMOS standby and High-speed
64K x V Static RAM Module
831V33 Features High-density 3.3V 2-megabit SRAM module High-speed SRAMs Access time of 12 ns Low active power 1.512W (max.) at 12 ns 64 pins Available in ZIP format Functional Description CYM1831V33 64K
Rev. No. History Issue Date Remark
8K X 8 BIT CMOS SRAM Document Title 8K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 9, 2004 Preliminary 1.0 Remove non-pb-free package type July 3, 2006
DESCRIPTION ECC. Array 1Mx5
1Mx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES High-speed access time: 10ns, 12ns A0 A19 Single power supply 2.4V-3.6V Error Detection and Correction with optional ERR1/ERR2 output
Rev. No. History Issue Date Remark
32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 2, 2001 Preliminary 0.1 Add ultra temp grade and 28-pin DIP package
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JULY 2006 FEATURES High-speed access time: 10, 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS stand-by
Pin Connection (Top View)
TOSHIBA TC551001BPL/BFL/BFTL/BTRL-70L/85L SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM Description The TC551001BPL is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
Features High speed t AA = 12 ns Low active power 1320 mw (max.) Low CMOS standby power (Commercial L version) 2.75 mw (max.) 2.0V Data Retention (400 µw at 2.0V retention) Automatic power-down when deselected
256K x 8 Static RAM Module
41 CYM1441 Features High-density 2-megabit module High-speed CMOS s Access time of 20 ns Low active power 5.3W (max.) SMD technology Separate data I/O 60-pin ZIP package TTL-compatible inputs and outputs
IS62/65WV102416EALL IS62/65WV102416EBLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating (typical): - 10.8mW (1.8V), 18mW (3.0V) CMOS Standby (typical): - 48
IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POR ASYNCHRONOUS CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
Revision No History Draft Date Remark. 10 Initial Revision History Insert Jul Final
128Kx8bit CMOS SRAM Document Title 128K x8 bit 5.0V Low Power CMOS slow SRAM Revision History Revision No History Draft Date Remark 10 Initial Revision History Insert Jul.14.2000 Final 11 Marking Information
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM DESCRIPTION The TC51WHM516AXBN is a 33,554,432-bit pseudo static random access memory(psram) organized
Item Previous Current 8ns 110mA 80mA. 10ns 90mA 65mA 12ns 80mA 55mA 15ns 70mA 45mA 8ns 130mA 100mA
Document Title 256Kx16 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial release with
IS61C25616AL IS61C25616AS IS64C25616AL IS64C25616AS
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) High-speed access time: 10ns, 12 ns Low Active Power: 150 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby LOW POR:
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM MAY 2012 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM JULY 2007 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION APRIL 2008 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 10, 12 ns CMOS Low Power Operation 1 mw (typical) CMOS standby 125 mw (typical) operating Fully static operation: no clock
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT29BV040A
Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Software Protected Programming Fast Read Access Time 200 ns Low Power Dissipation 15 ma Active Current 50 µa CMOS Standby
IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES High-speed access times: 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
64K x 16 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
IS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
IS63LV1024 IS63LV1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT FEATURES High-speed access times: 8, 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise
1 Mbit (128K x 8) Static RAM
1 Mbit (128K x 8) Static RAM Features Temperature Ranges Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Pin and Function compatible with CY7C1019BV33 High Speed t AA = 10 ns CMOS for optimum Speed
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7 A 15 7
Features High speed t AA = 12 ns Low active power 495 mw (max.) Low CMOS standby power 11 mw (max.) (L Version) 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs
CMOS STATIC RAM 1 MEG (128K x 8-BIT)
CMOS STATIC RAM 1 MEG (12K x -BIT) IDT71024 Integrated Device Technology, Inc. FEATURES: 12K x advanced high-speed CMOS static RAM Commercial (0 to 70 C), Industrial (-40 to 5 C) and Military (-55 to 125
16 Meg FPM DRAM AS4LC4M4. 4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT ACTIVE POWER DISSIPATION PERFORMANCE RANGE
4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883 FEATURES Fast Page Mode Operation CAS\-before-RAS\ Refresh Capability RAS\-only and
IS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW POR CMOS STATIC RAM FEATURES Access time: 45, 70 ns Low active power: 200 mw (typical) Low standby power 250 µw (typical) CMOS standby 28 mw (typical) TTL standby Fully static operation: no
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
8K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 0 ns CMOS low power operation mw (typical) CMOS standby 25 mw (typical) operating TTL compatible interface levels Single
IS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection
IS62C5128BL, IS65C5128BL
512K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2011 FEATURES High-speed access time: 45ns Low Active Power: 50 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby TTL compatible interface levels Single
power and 32,786 x 8-bits and outputs -2.0V(min.) data fabricated using
查询 HY62256A 供应商 Data Sheet-sram/62256ald1 http://www.hea.com/hean2/sram/62256ald1.htm HY62256A-(I) Series 32Kx8bit CMOS SRAM Description Features The Fully static operation and HY62256A/HY62256A-I Tri-state
IS62WV102416FALL/BLL IS65WV102416FALL/BLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM MARCH 2018
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
CY Features. Logic Block Diagram
Features Temperature Ranges -Commercial:0 to 70 -Industrial: -40 to 85 -Automotive: -40 to 125 High speed: 55ns and 70 ns Voltage range : 4.5V 5.5V operation Low active power (70ns, LL version, Com l and
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
IS61WV20488FALL IS61/64WV20488FBLL. 2Mx8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
2Mx8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS61WV2568EDBLL IS64WV2568EDBLL
ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply
IS61/64WV5128EFALL IS61/64WV5128EFBLL. 512Kx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
512Kx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC APRIL 2018 KEY FEATURES A0 A17 A18 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV5128EFALL) 2.4V-3.6V () Error Detection
I/O 1 I/O 2 I/O 3 A 10 6
Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 467 mw (max, 12 ns L version) Low standby power 0.275 mw (max, L version) 2V data retention ( L version only) Easy memory
LY61L25616A 256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 VCC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current ICC1 on
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
IS62C51216AL IS65C51216AL
IS62C51216AL IS65C51216AL 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
UM61512A Series 64K X 8 BIT HIGH SPEED CMOS SRAM. Features. General Description. Pin Configurations UM61512AV UM61512A
Series 64K X 8 BIT HIGH SPEE CMOS SRAM Features Single +5V power supply Access times: 15/20/25ns (max.) Current: Operating: 160mA (max.) Standby: 10mA (max.) Full static operation, no clock or refreshing