A4 A3 A2 A1 A0 DQ0 DQ15. DQ2 DQ3 Vcc GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12
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1 128K x 16 Low Power SRAM Rev /2007 Features 48-Ball BGA (CSP), Top View Single power supply voltage of 2.7V to 3.6V Power down features using CE Low operating current : 30mA(max for 55 ns) Maximum Standby current : 35µA at 3.6 V Data retention supply voltage: 1.5V to 3.6V Direct TTL compatibility for all input and output Wide operating temperature range: -40 C to 85 C Package type: 48-ball TFBGA, 6x8mm 44L pin TSOP II Ordering Information Part Number Speed IDDS2 Package BC ns 35 µa 6x8 BGA BC-55G 55 ns 35 µa 6x8 BGA Green 44L TSOP II, Top View TS ns 35 µa 44pin TSOP II BC ns 35 µa 6x8 BGA BC-70G 70 ns 35 µa 6x8 BGA Green TS ns 35 µa 44pin TSOP II Pin Description Symbol A0 - A16 DQ0 DQ15 CE OE# WE# LB#, UB# GND VDD NC Function Address Inputs Data Inputs / Outputs Chip Enable Inputs Output Enable Read / Write Control Input Data Byte Control Inputs Ground Power Supply No Connection A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 Vcc GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND Vcc DQ11 DQ10 DQ9 DQ8 NC A08 A09 A10 A11 NC Pin Configuration Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886) FAX: (886) Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
2 Overview The is a 2,097,152-bit SRAM organized as 131,072 words by 16 bits. It is designed with advanced CMOS technology. This Device operates from a single 2.7V to 3.6V power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when chip enable (CE#) is asserted high. There are two control inputs. CE# is used to select the device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from -40 C to 85 C, the can be used in environments exhibiting extreme temperature conditions. Etron Technology Inc. 1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C TEL: (886) FAX: (886) Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
3 Block Diagram 3 Rev 1.5 Apr. 2007
4 Operating Mode Mode CE# OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15 Power L L D OUT D OUT Active Read L L H H L High-Z D OUT Active L H D OUT High-Z Active L L D IN D IN Active Write L X L H L High-Z D IN Active L H D IN High-Z Active Output Deselect L H H X X High-Z High-Z Active H X X X X Standby L X X H H Note: X = don't care. H=logic high. L=logic low. High-Z High-Z Standby Absolute Maximum Ratings Supply voltage, V DD Input voltages, V IN Input and output voltages, V I/O Operating temperature, T OPR Storage temperature, T STRG Soldering Temperature (10s), T SOLDER Power dissipation, P D -0.3 to +4.6V -0.3 to +4.6V -0.5 to V DD +0.5V -40 to +85 C -55 to +150 C 240 C(for Non Green Package) 260 C(for Green Package) 0.6 W DC Recommended Operating Conditions (Ta= -40 C to 85 C) Symbol Parameter Min Typ Max Unit V DD Power Supply Voltage V V IH Input High Voltage 2.2 V DD (1) V V IL Input Low Voltage -0.3 (2) 0.6 V V DR Data Retention Supply Voltage V Note: (1) Overshoot : VDD +2.0V in case of pulse width 20ns (2) Undershoot : -2.0V in case of pulse width 20ns 4 Rev 1.5 Apr. 2007
5 DC Characteristics (Ta = -40 C to 85 C, V DD = 2.7V to 3.6V) Parameter Symbol Test Conditions Min Max Unit Input low current I IL I IN = 0V to V DD µa Output low voltage Output high voltage V OL I OL = 2.1 ma V V OH I OH = -1.0 ma 2.2 V Operating current I DD1 V DD = 3.6 V, CE1# = V IL and CE2 = V IH and Cycle time = min 55 ns ns 25 ma I DD2 I OUT = 0mA Cycle time = 1µs 4 Other Input = V IH / V IL Standby current I DDS2** (Note) CE# V DD 0.2V or LB# = UB# V DD 0.2V 35 µa Capacitance (Ta = 25 C; f = 1 MHz) Parameter Symbol Min Typ Max Unit Test Conditions Input capacitance C IN 10 pf V IN = GND Output capacitance C OUT 10 pf V OUT = GND Notes: This parameter is periodically sampled and is not 100% tested. 5 Rev 1.5 Apr. 2007
6 AC Characteristics and Operating Conditions (Ta = -40 C to 85 C, V DD = 2.7V to 3.6V) Read Cycle Symbol Parameter Unit Min Max Min Max t RC Read cycle time t AA Address access time t CO Chip Enable (CE#) Access Time t OE Output enable access time t BA Data Byte Control Access Time t LZ Chip Enable Low to Output in Low-Z t OLZ Output enable Low to Output in Low-Z 3 3 ns t BLZ Data Byte Control Low to Output in Low-Z 5 5 t HZ Chip Enable High to Output in High-Z t OHZ Output Enable High to Output in High-Z t BHZ Data Byte Control High to Output in High-Z t OH Output Data Hold Time 0 0 Write Cycle Symbol Parameter Unit Min Max Min Max t WC Write cycle time t WP Write pulse width t CW Chip Enable to end of write t BW Data Byte Control to end of Write t AS Address setup time 0 0 t WR Write Recovery time 0 0 ns t WHZ WE# Low to Output in High-Z t OW WE# High to Output in Low-Z 5 5 t DS Data Setup Time t DH Data Hold Time 0 0 AC Test Condition Output load : 50pF + one TTL gate Input pulse level : 0.4V, 2.4V Timing measurements : 0.5 x VDD tr, tf : 5ns 6 Rev 1.5 Apr. 2007
7 Read Cycle (See Note 1) 7 Rev 1.5 Apr. 2007
8 Write Cycle1 (WE# Controlled)(See Note 4) 8 Rev 1.5 Apr. 2007
9 Write Cycle 2 (CE# Controlled)(See Note 4) 9 Rev 1.5 Apr. 2007
10 Write Cycle3 (UB#, LB# Controlled)(See Note 4) Note: 1. WE# remains HIGH for the read cycle. 2. If CE# goes LOW with or after WE# goes LOW, the outputs will remain at high impedance. 3. If CE# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance. 4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 10 Rev 1.5 Apr. 2007
11 Data Retention Characteristics (Ta = -40 C to 85 C) Symbol Parameter Min Typ Max Unit V DR I DR Data Retention Supply Voltage Data Retention Current CE1# VDD - 0.2V, CE2 0.2V, VIN VDD - 0.2V or VIN 0.2V VDD = 1.5V, CE# VDD - 0.2V, VIN VDD - 0.2V or VIN 0.2V V - 35 µa t SDR Chip Deselect to Data Retention Mode Time 0 ns t RDR Recovery Time t RC ns CE# Controlled Data Retention Mode Note: 1. CE VDD 0.2V or UB# = LB# VDD 0.2V 11 Rev 1.5 Apr. 2007
12 Package Diagrams 48-Ball (6mm x 8mm) BGA Units in mm 12 Rev 1.5 Apr. 2007
13 Package Diagrams 44L 400 mil TSOP II E HE S D y F Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A A A b e C D E HE L L1 0.8 BASIC BASIC F S REF REF y D DETAIL A L1 13 Rev 1.5 Apr. 2007
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512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash FEATURES: GLS27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories Organized as 64K x8 / 128K x8 / 256K x8 4.5-5.5V Read Operation
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 10, 12 ns CMOS Low Power Operation 1 mw (typical) CMOS standby 125 mw (typical) operating Fully static operation: no clock
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
IS62WV6416ALL IS62WV6416BLL
IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access time: 45ns, 55ns CMOS low power operation: 30 mw (typical) operating 15 µw (typical)
IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION APRIL 2008 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
8K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 0 ns CMOS low power operation mw (typical) CMOS standby 25 mw (typical) operating TTL compatible interface levels Single
RMLV0808BGSB - 4S2. 8Mb Advanced LPSRAM (1024k word 8bit) Description. Features. Part Name Information. R10DS0232EJ0200 Rev
8Mb Advanced LPSRAM (1024k word 8bit) Description The RMLV0808BGSB is a family of 8-Mbit static RAMs organized 1,048,576-word 8-bit, fabricated by Renesas s high-performance Advanced LPSRAM technologies.
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
128K x 8 LOW POR CMOS STATIC RAM DECEMBER 2003 FEATURES High-speed access time: 35, 70 ns Low active power: 450 mw (typical) Low standby power: 150 µw (typical) CMOS standby Output Enable (OE) and two
1-Megabit (128K x 8) Unregulated Battery-Voltage OTP EPROM AT27BV010
Features Fast Read Access Time 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power
IS62WV51216EFALL/BLL IS65WV51216EFALL/BLL. 512Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM AUGUST 2017
512Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC AUGUST 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
IS62WV102416FALL/BLL IS65WV102416FALL/BLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM MARCH 2018
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
IS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
64K x 16 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
A 4 A 3 A 2 ROW DECODER 64K x 16 RAM Array I/O 1 I/O X 2048 I/O 9 I/O 16
021 CY7C1021 Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 1320 mw (max.) Automatic power-down when deselected Independent Control of Upper and Lower bits Available in
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM JULY 2007 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
LY61L25616A 256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 VCC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current ICC1 on
IS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES High-speed access time: 35, 45, 55 ns CMOS low power operation 30 mw (typical) operating 6 µw (typical) CMOS standby TTL compatible interface
LY62L K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 1.1 Adding PKG type : 32 SOP Mar.3.2006 Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR May.14.2007
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW POR CMOS STATIC RAM FEATURES Access time: 45, 70 ns Low active power: 200 mw (typical) Low standby power 250 µw (typical) CMOS standby 28 mw (typical) TTL standby Fully static operation: no
EEPROM AS58LC K x 8 EEPROM Radiation Tolerant. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535
128K x 8 EEPROM Radiation Tolerant AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535 FEATURES High speed: 250ns and 300ns Data Retention: 10 Years Low power dissipation, active current (20mW/MHz (TYP)),
CY Features. Logic Block Diagram
Features Temperature Ranges -Commercial:0 to 70 -Industrial: -40 to 85 -Automotive: -40 to 125 High speed: 55ns and 70 ns Voltage range : 4.5V 5.5V operation Low active power (70ns, LL version, Com l and
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
IS62WV102416GALL/BLL IS65WV102416GALL/BLL. 1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM. FUNCTIONAL Block Diagram NOVEMBER 2017
1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM NOVEMBER 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
Rev. No. History Issue Date Remark
8K X 8 BIT CMOS SRAM Document Title 8K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 9, 2004 Preliminary 1.0 Remove non-pb-free package type July 3, 2006
IS62C25616EL, IS65C25616EL
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM AUGUST 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 5.0uA
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM MAY 2012 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM DEMBER 00 FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical)
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7 A 15 7
Features High speed t AA = 12 ns Low active power 495 mw (max.) Low CMOS standby power 11 mw (max.) (L Version) 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
LY61L K X 16 BIT HIGH SPEED CMOS SRAM
Y6125616 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue May.24.2006 Rev. 1.1 Added Extended Grade Jan.22.2007 Rev. 1.2 Added PKG Type : 48-ball 6mm x 8mm TFBGA Jan.30.2007 Rev.
128K x 8 Static RAM CY7C1019B CY7C10191B. Features. Functional Description. Logic Block Diagram. Pin Configurations
128K x 8 Static RAM Features High speed t AA = 10, 12, 15 ns CMOS for optimum speed/power Center power/ground pinout Automatic power-down when deselected Easy memory expansion with and OE options Functionally
P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM
ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 1/1/15//5 (Commercial) 15//5/35 (Military) Low Power Operation 715 mw Active 1 (Commercial)
IS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
Features High speed t AA = 12 ns Low active power 1320 mw (max.) Low CMOS standby power (Commercial L version) 2.75 mw (max.) 2.0V Data Retention (400 µw at 2.0V retention) Automatic power-down when deselected