LY61L25616A 256K X 16 BIT HIGH SPEED CMOS SRAM

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1 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul Rev. 1.1 VCC - 0.2V revised as 0.2V for TEST CONDITION Jul of Average Operating Power supply Current ICC1 on page3 Rev. 1.2 May Revised VIH(max)/VI(min) in DC EECTRICA CHARACTERISTICS Added in tba/tbhz*/tbz* in AC EECTRICA CHARACTERISTICS Added WRITE CYCE 3 in TIMING WAVEFORMS Rev Revise TEST CONDITION for VOH, VO on page 5 IOH = -8mA revised as -4mA IO =4mA revised as 8mA 2. Revise VIH(max) & VI(min) note on page 5 VIH(max) = VCC + 2.0V for pulse width less than 6ns. VI(min) = VSS - 2.0V for pulse width less than 6ns. Rev. 1.4 Revised the address pin sequence of TSOP II pin configuration on page 3 in order to be compatible with industry convention. (No function specifications and applications have been changed and all the characteristics are kept all the same as Rev 1.3 ) Added tbw in AC EECTRICA CHARACTERISTICS Revised WRITE CYCE 1,2 in TIMING WAVEFORMS Jun Sep Rev. 1.5 Added G-8I/-8IT in ORDERING INFORMATION Jan Revised PIN DESCRIPTION in page 1 Deleted C grade in ORDERING INFORMATION Deleted WRITE CYCE Notes : 1. WE#,, B#, UB# must be high during all address transitions. in page 7. Feb yontek Inc. reserves the rights to change the specifications and products without notice. TE:

2 FEATURES Fast access time : 8/10/12ns ow power consumption: Operating current: 50/40/35mA (TYP.) Standby current: 2mA (TYP.) Single 3.3V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : B# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.) Green package available Package : 44-pin 400mil TSOP II 48-ball 6mm x 8mm TFBGA GENERA DESCRIPTION The is a 4,194,304-bit high speed CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The operates from a single power supply of 3.3V and all inputs and outputs are fully TT compatible PRODUCT FAMIY Product Family Operating Temperature 0 ~ 70 (I) -40 ~ 85 VCC Range Speed Power Dissipation Standby(ISB1,TYP.) Operating(ICC1,TYP.) 2.7 ~ 3.6V 10/12ns 2mA 40/35mA 3.0 ~ 3.6V 8ns 2mA 50mA 2.7 ~ 3.6V 10/12ns 2mA 40/35mA 3.0 ~ 3.6V 8ns 2mA 50mA FUNCTIONA BOCK DIAGRAM PIN DESCRIPTION Vcc Vss SYMBO A0 - A17 DQ0 - DQ15 DESCRIPTION Address Inputs Data Inputs/Outputs A0-A17 DECODER 256Kx16 MEMORY ARRAY WE# Chip Enable Inputs Write Enable Input OE# Output Enable Input B# ower Byte Control UB# Upper Byte Control DQ0-DQ7 ower Byte DQ8-DQ15 Upper Byte I/O DATA CIRCUIT COUMN I/O VCC VSS NC Power Supply Ground No Connection WE# OE# B# UB# CONTRO CIRCUIT yontek Inc. reserves the rights to change the specifications and products without notice. TE:

3 PIN CONFIGURATION A0 A1 A2 A3 A4 DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE# A5 A6 A7 A8 A XXXXXXXX XXXXXXXX A17 A16 A15 OE# UB# B# DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 NC A14 A13 A12 A11 A10 TSOP II A B# OE# A0 A1 A2 NC B DQ8 UB# A3 A4 DQ0 C D E F DQ9 DQ10 A5 Vss DQ11 A17 Vcc DQ12 NC DQ14 DQ13 A14 A6 A7 A16 A15 DQ1 DQ2 DQ3 Vcc DQ4 Vss DQ5 DQ6 XXXXXXXX XXXXXXXX G DQ15 NC A12 A13 WE# DQ7 H NC A8 A9 A10 A11 NC TFBGA(See through with Top View) TFBGA (Top View) yontek Inc. reserves the rights to change the specifications and products without notice. TE:

4 ABSOUTE MAXIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on VCC relative to VSS VT1-0.5 to 4.6 V Voltage on any other pin relative to VSS VT2-0.5 to VCC+0.5 V Operating Temperature TA 0 to 70(C grade) -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 ma *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABE MODE OE# WE# B# UB# I/O OPERATION DQ0 - DQ7 DQ8 - DQ15 SUPPY CURRENT Standby H X X X X ISB,ISB1 Output Disable H H X X X X H H ICC,ICC1 Read H H H H DOUT DOUT ICC,ICC1 H DOUT DOUT Write X X X H H DIN DIN DIN DIN ICC,ICC1 Note: H = VIH, = VI, X = Don't care yontek Inc. reserves the rights to change the specifications and products without notice. TE:

5 DC EECTRICA CHARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. *4 MAX. UNIT Supply Voltage VCC V -10/ V Input High Voltage VIH * VCC+0.3 V Input ow Voltage VI * V Input eakage Current II VCC VIN VSS µa Output eakage VCC VOUT VSS, IO Current Output Disabled µa Output High Voltage VOH IOH = -4mA V Output ow Voltage VO IO = 8mA V Cycle time = MIN ma ICC = VI, II/O = 0mA, ma Others at VI or VIH ma Average Operating Power supply Current ICC1 0.2, Others at 0.2V or VCC-0.2V II/O = 0mA; f=max ma ma ma ISB =VIH, Others at VI or VIH ma Standby Power VCC - 0.2V, Supply Current ISB ma Others at 0.2V or VCC - 0.2V Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VI(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25 CAPACITANCE (T A = 25, f = 1.0MHz) PARAMETER SYMBO MIN. MAX. UNIT Input Capacitance CIN - 8 pf Input/Output Capacitance CI/O - 10 pf Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Speed 8/10/12ns Input Pulse evels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference evels 1.5V Output oad C = 30pF + 1TT, IOH/IO = -4mA/8mA yontek Inc. reserves the rights to change the specifications and products without notice. TE:

6 AC EECTRICA CHARACTERISTICS (1) READ CYCE PARAMETER SYM MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time trc ns Address Access Time taa ns Chip Enable Access Time tace ns Output Enable Access Time toe ns Chip Enable to Output in ow-z tcz* ns Output Enable to Output in ow-z toz* ns Chip Disable to Output in tchz* ns Output Disable to Output in tohz* ns Output Hold from Address Change toh ns B#, UB# Access Time tba ns B#, UB# to Output tbhz* ns B#, UB# to ow-z Output tbz* ns (2) WRITE CYCE PARAMETER SYM MIN. MAX. MIN. MAX. MIN. MAX. UNIT Write Cycle Time twc ns Address Valid to End of Write taw ns Chip Enable to End of Write tcw ns Address Set-up Time tas ns Write Pulse Width twp ns Write Recovery Time twr ns Data to Write Time Overlap tdw ns Data Hold from End of Write Time tdh ns Output Active from End of Write tow* ns Write to Output in twhz* ns B#, UB# Valid to End of Write tbw ns *These parameters are guaranteed by device characterization, but not production tested. yontek Inc. reserves the rights to change the specifications and products without notice. TE:

7 TIMING WAVEFORMS READ CYCE 1 (Address Controlled) (1,2) Address trc taa toh Dout Previous Data Valid Data Valid READ CYCE 2 ( and OE# Controlled) (1,3,4,5) Address trc taa B#,UB# tace OE# tba tbz tcz toz toe toh tohz tbhz tchz Dout Data Valid Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, = low, B# or UB# = low. 3.Address must be valid prior to or coincident with = low, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tCZ, tbz, toz, tchz, tbhz and tohz are specified with C = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, t CHZ is less than t CZ, t BHZ is less than t BZ, t OHZ is less than t OZ yontek Inc. reserves the rights to change the specifications and products without notice. TE:

8 WRITE CYCE 1 (WE# Controlled) (1,2,4,5) twc Address taw tcw tbw B#,UB# tas twp twr WE# twhz tow Dout (4) (4) tdw tdh Din Data Valid WRITE CYCE 2 ( Controlled) (1,4,5) twc Address taw tas twr B#,UB# tbw tcw twp WE# Dout twhz (4) tdw tdh Din Data Valid yontek Inc. reserves the rights to change the specifications and products without notice. TE:

9 WRITE CYCE 3 (B#,UB# Controlled) (1,4,5) twc Address taw twr B#,UB# tas tcw tbw twp WE# Dout (4) twhz tdw tdh Din Data Valid Notes : 1.A write occurs during the overlap of a low, low WE#, B# or UB# = low. 2.During a WE# controlled write cycle with OE# low, twp must be greater than twhz + tdw to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the, B#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and twhz are specified with C = 5pF. Transition is measured ±500mV from steady state. yontek Inc. reserves the rights to change the specifications and products without notice. TE:

10 DATA RETENTION CHARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. MAX. UNIT VCC for Data Retention VDR VCC - 0.2V V Data Retention Current IDR VCC = 1.5V, VCC - 0.2V Others at 0.2V or VCC 0.2V ma Chip Disable to Data Retention Time tcdr See Data Retention Waveforms (below) ns Recovery Time tr trc* - - ns trc* = Read Cycle Time DATA RETENTION WAVEFORM VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr VIH Vcc-0.2V VIH yontek Inc. reserves the rights to change the specifications and products without notice. TE:

11 PACKAGE OUTINE DIMENSION 44-pin 400 mil TSOP Ⅱ Package Outline Dimension SYMBOS DIMENSIONS IN MIMETERS DIMENSIONS IN MIS MIN. NOM. MAX. MIN. NOM. MAX. A A A b c D E E e ZD y Θ 0 o 3 o 6 o 0 o 3 o 6 o yontek Inc. reserves the rights to change the specifications and products without notice. TE:

12 48-ball 6mm 8mm TFBGA Package Outline Dimension yontek Inc. reserves the rights to change the specifications and products without notice. TE:

13 ORDERING INFORMATION Package Type 44-pin (400mil) TSOP II Access Time (Speed/ns) Temperature Range( ) Packing Type yontek Item No ~85 Tray M-8I Tape Reel M-8IT ~85 Tray M-10I Tape Reel M-10IT yontek Inc. reserves the rights to change the specifications and products without notice. TE:

14 ORDERING INFORMATION Package Type 48-ball (6mm x 8mm) TFBGA Access Time (Speed/ns) Temperature Range( ) Packing Type yontek Item No ~85 Tray G-8I Tape Reel G-8IT ~85 Tray G-10I Tape Reel G-10IT yontek Inc. reserves the rights to change the specifications and products without notice. TE:

15 THIS PAGE IS EFT BANK INTENTIONAY. yontek Inc. reserves the rights to change the specifications and products without notice. TE:

LY61L K X 16 BIT HIGH SPEED CMOS SRAM

LY61L K X 16 BIT HIGH SPEED CMOS SRAM Y6125616 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue May.24.2006 Rev. 1.1 Added Extended Grade Jan.22.2007 Rev. 1.2 Added PKG Type : 48-ball 6mm x 8mm TFBGA Jan.30.2007 Rev.