SRM2B256SLMX55/70/10
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1 256K-BIT STATIC RAM Wide Temperature Range Extremely Low Standby Current Access Time 100ns (2.7V) 55ns (4.5V) 32,768 Words 8-Bit Asynchronous DESCRIPTION The SRM2B256SLMX is a low voltage operating 32,768 words 8-bit asynchronous, static, random access memory fabricated using an advanced CMOS technology. Its very low standby power consumption makes it ideal for applications requiring non-volatile storage with back-up batteries, and 25 to 85 C operating temperature range makes it ideal for industrial use. The asynchronous and static nature of the memory requires no external clock or refresh circuit. 3-state output ports allow easy expansion of memory capacity. These features make the SRM2B256SLMX usable for a wide range of applications, from microprocessor systems to terminal devices. FEATURES Wide temperature range to 85 C Extended supply voltage range to 5.5V Fast access ns (3V ± 10%) 55ns (5V ± 10%) Extremely low standby current SL Version Completely static No clock required 3-state output Battery back-up operation Package SRM2B256SLCX DIP2-28pin (plastic) SRM2B256SLMX SOP2-28pin (plastic) SRM2B256SLTMX TSOP (I)-28pin (plastic) SRM2B256SLRMX TSOP (I)-28pin-R1 (plastic) MEM- 57
2 BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Address Buffer 9 6 X Decoder Y Decoder Memory Cell Array 512 x 64 x 8 64 x 8 Column Gate Control Logic 8 OE WE OE, WE Control Logic I/O Buffer I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O MEM-
3 PIN CONFIGURATION (DIP/SOP2) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS VDD WE A13 A8 A9 A11 OE A10 I/O8 I/O7 I/O6 I/O5 I/O4 SRM2B256SLMX/CX (TSOP) (TSOP-R1)(Reverse bending) OE A11 A9 A8 A13 WE V DD A14 A12 A7 A6 A5 A4 A SRM2B256SLTMX A10 I/O8 I/O7 I/O6 I/O5 I/O4 V SS I/O3 I/O2 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 V DD WE A13 A8 A9 A11 OE SRM2B256SLRMX A2 A1 A0 I/O1 I/O2 I/O3 V SS I/O4 I/O5 I/O6 I/O7 I/O8 A10 PIN DESCRIPTION A0 to A14 WE OE I/O1 to I/O8 VDD VSS Address input Write Enable Output Enable Chip Select Data I/O Power Supply (2.7V to 5.5V) Power Supply (0V) MEM- 59
4 ABSOLUTE MAXIMUM RATINGS VSS = 0V Parameter Symbol Rating Unit Supply voltage VDD 0.5 to 7.0 V Input voltage VI 0.5* to 7.0 V Input/output voltage VI/O 0.5* to VDD V Power dissipation PD W Operating temperature TOPR 25 to 85 C Storage temperature TSTG 65 to 150 C Soldering temperature and TSOL 260 C, 10s (Lead only) * VI, VI/O (Min.) = 3.0V when pulse width is less or equal to 50ns DC RECOMMENDED OPERATING CONDITIONS VSS = 0V, Ta = 25 to 85 C Parameter Supply voltage Input voltage VDD = 3V ± 10% VDD = 5V ± 10% Symbol Unit Min. Typ. Max. Min. Typ. Max. VDD V VSS V VIH 2.2 VDD VDD V VIL 0.3* * V * VIL (Min.) = 3V when pulse width is less or equal to 50ns MEM-
5 ELECTRICAL CHARACTERISTI DC Electrical Characteristics (VSS = 0V, Ta = 25 to 85 C) Parameter Symbol Conditions VDD = 3V VDD = 5V Min Typ*1 Max Min Typ*2 Max Input leakage ILI VI = 0 to VDD µa Standby supply current IDDS = VIH ma IDDS1 VDD 0.2V µa Unit Average operating current IDDA IDDA1 VI = VIL, VIH II/O = 0mA, tcyc = Min VI = VIL, VIH II/O = 0mA, tcyc = 1µs ma 5 10 ma Operating supply current IDDO VI = VIL, VIH ILO = 0mA 5 10 ma Output leakage High level output voltage Low level output voltage ILO = VIH or WE = VIL or OE = VIH, VI/O = 0 to VDD µa VOH IOH = ma, 0.5mA* V VOL IOL = 2.1mA, ma* V *1 Typical values are measured at Ta = 25 C and VDD = 3.0V *2 Typical values are measured at Ta = 25 C and VDD = 5.0V *3 VDD = 3.0V Terminal Capacitance (f = 1MHz, Ta = 25 C) Parameter Symbol Conditions Min Typ Max Unit Address capacitance CADD VADD = 0V 8 pf Input capacitance CI VI = 0V 8 pf I/O capacitance CI/O VI/O = 0V 10 pf MEM- 61
6 AC Electrical Characteristics Read Cycle VSS = 0V, Ta = 25 to 85 C SRM2B256SLMX55 SRM2B256SLMX70 SRM2B256SLMX10 Parameter Symbol Condi -tions VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V Unit Read cycle trc Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max ns Address access access OE access tacc ns *1 ta ns toe ns output set tclz ns output floating OE output set OE output floating Output hold tchz ns *2 tolz ns tohz ns toh * ns MEM-
7 Write Cycle VSS = 0V, Ta = 25 to 85 C SRM2B256SLMX55 SRM2B256SLMX70 SRM2B256SLMX10 Parameter Symbol Condi -tions VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V Unit Write cycle twc Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max ns Chip Select Address valid to end of write Address setup Write pulse width Address hold Input data set Input data hold Write to output floating Output active from end to write tcw ns taw ns tas ns *1 twp ns twr ns tdw ns tdh ns twhz ns *2 tow ns *1. Test Conditions 1. Input pulse level: 0.6V to 2.4V (5V) /0.4V to 2.2V (3V) 2. tr = tr = 5ns 3. Input and output timing reference levels : 1.5V 4. Output load CL = 100pF I/O C L 1TTL C L = 100pF (Includes Jig Capacitance) *2. Test Conditions 1. Input pulse level: 0.6V to 2.4V (5V) /0.4V to 2.2V (3V) 2. tr = tr = 5ns 3. Input timing reference levels : 1.5V 4. Output timing reference levels: ± 200mV (the level displaced from stable output voltage level) 5. Output load CL = 5pF 1TTL I/O C L C L = 5pF (Includes Jig Capacitance) MEM- 63
8 Timing Charts Read Cycle*1 t RC ADDRESS t ACC t A t OH t CLZ t CHZ OE Dout t OE t OLZ t CHZ Note: *1. During read cycle, WE must be H level. Write Cycle (1) ( Control)*2 t WC ADDRESS t AW t CW WE t AS t WP t WR Dout t CLZ t WHZ t DW t DH Din Note: *2. During write cycle that is controlled by, Output Buffer is in high impedance state, whether OE level is H or L MEM-
9 Write Cycle (2) (WE Control)*3 ADDRESS WE Dout Din t AS t WC t AW t WP t WHZ t DW t WR t DH t OW Note: *3. During write cycle that is controlled by WE, Output Buffer is in high impedance state if OE is H level MEM- 65
10 DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (VSS = 0V, Ta = 25 to 85 C) Parameter Symbol Conditions Min Typ* Max Unit Data retention supply voltage VDDR V Data retention current IDDR VDD = 3V VDD 0.2V (2**) µa Chip select data hold tcdr 0 ns Operation recovery tr 5 ns * Typical values are measured at 25 C ** Typical values are measured at 40 C Data Retention Timing V DD Data hold mode 2.7V 2.7V V DDR 2.0V t CDR V IH V DD 0.2V t R V IH *Note: During standby mode in which the data is retentive, the supply voltage (VDD) can be in low voltage until VDD = VDDR. At this mode, data reading and writing are impossible MEM-
11 FUNCTIONS Truth Table OE WE A0 to A14 Data I/O Mode IDD H X X Hi-Z Standby IDDS, IDDS1 L X L Stable DIN Write IDDA, IDDA1 L L H Stable DOUT Read IDDA, IDDA1 L H H Stable Hi-Z Output disable IDDA, IDDA1 X: H or L : H, L, or Hi-Z Read Mode The data appear when the address is set while holding = L, OE = L and WE = H. When OE = H, DATA I/O terminals are in high impedance state, that makes circuit design and bus control easy. Write Mode There are the following 3 ways of writing data into memory: (1) Hold = L and WE = L, set address (2) Hold = L then set address and give L pulse to WE. (3) After setting addresses, give L pulse to both and WE. In case the above data on the DATA I/O terminals is latched up into the chip when or WE is in positive-going. Since DATA I/O terminals are high impedance when or OE = H, bus contention between data driver and memory outputs can be avoided. Standby Mode When is H, the chip is in the standby mode. In this mode, DATA I/O terminals are high impedance and all inputs of addresses, WE and data can be any H or L. When is over VDD 0.2V, the chip is in the data retention battery backup mode. In this case, there is a small current in the chip which flows through the high resistances of the memory cells MEM- 67
12 PACKAGE DIMENSIONS Plastic DIP-28 pin Unit: mm (inch) Max 36.7 ± ± ± ± ± Min 0.46 ± ~16.64 Plastic TSOP (I)-28 pin Unit: mm (inch) 13.4 ± ± Index ± ± Max 0 ~ ± ± MEM-
13 Plastic TSOP (I)-28 pin-r1 Unit: mm (inch) 13.4 ± ± Index ± ± Max 0 ~ ± ± 0.1 Plastic SOP2-28 pin Unit: mm (inch) Max 17.8 ± ± ± ± ± ± MEM- 69
14 CHARACTERISTIC CURVES Normalized I DDA Ta 5V 3V Normalized I DDA Frequency 5V 3V Normalized I DDA V DD 5V 3V Ta ( C) Ta ( C) V DD (V) Ta = 25 C Normalized I DDS1 Ta 5V 3V Ta ( C) Normalized I DDS1 V DD Normalized I OH V OH V 3V V DD (V) Ta = 25 C V OH (V) Ta = 25 C Normalized I OL V OL 5V 3V V DD (V) Ta = 25 C Normalized t ACC, t A V DD Normalized t ACC t A V 1.2 3V V DD (V) Ta ( C) Ta = 25 C MEM-
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TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55YEM216ABXN is a 4,194,304-bit static random access memory (SRAM) organized
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DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES High-speed access times: 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
1Mb Ultra-Low Power Asynchronous CMOS SRAM. Features. Power Supply (Vcc) Operating Temperature A 0 -A 16 I/O 0 -I/O 7
1Mb Ultra-Low Power Asynchronous CMOS SRAM 128K 8 bit N01L83W2A Overview The N01L83W2A is an integrated memory device containing a 1 Mbit Static Random Access Memory organized as 131,072 words by 8 bits.
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C64 8K x 8 LOW POR CMOS STATIC RAM FEATURES CMOS low power operation 400 mw (max.) operating 25 mw (max.) standby Automatic power-down when chip is deselected TTL compatible interface levels Single
DECODER I/O DATA CONTROL CIRCUIT
1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2006 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation: 36 mw (typical) operating 12 µw (typical) CMOS standby TTL compatible
P4C164LL. VERY LOW POWER 8Kx8 STATIC CMOS RAM FEATURES DESCRIPTION V CC. Current (Commercial/Industrial) Operating: 55 ma CMOS Standby: 3 µa
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DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JULY 2006 FEATURES High-speed access time: 10, 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS stand-by
SRAM AS5C K x 8 SRAM Ultra Low Power SRAM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATION FEATURES GENERAL DESCRIPTION
512K x 8 Ultra Low Power AVAILABLE AS MILITARY SPECIFICATION SMD 5962-95613 1,2 MIL STD-883 1 FEATURES Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby) Fully Static, No
IS65LV256AL IS62LV256AL
32K x 8 LOW VOLTAGE CMOS STATIC RAM MAY 2012 FEATURES High-speed access time: 20, 45 ns Automatic power-down when chip is deselected CMOS low power operation 17 µw (typical) CMOS standby 50 mw (typical)
Very Low Power CMOS SRAM 64K X 16 bit. Pb-Free and Green package materials are compliant to RoHS. STANDBY (ICCSB1, Max) V CC=3.0V
Very Low Power CMOS SRAM 64K X 16 bit Pb-Free and Green package materials are compliant to RoHS BS616LV1010 FEATURES Wide operation voltage : 24V ~ 55V Very low power consumption : = 30V Operation current
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
32M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr. 26,2017
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 26,2017 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 33,578,432-bit high-speed Static Random Access Memory organized as 4M(2M) words
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005 FEATURES IS61C6416AL and High-speed access time: 12 ns, 15ns Low Active Power: 175 mw (typical) Low Standby Power: 1 mw (typical) CMOS standby and High-speed
Item Previous Current 8ns 110mA 80mA. 10ns 90mA 65mA 12ns 80mA 55mA 15ns 70mA 45mA 8ns 130mA 100mA
Document Title 256Kx16 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial release with
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
IS61C1024AL IS64C1024AL
IS61C1024AL IS64C1024AL 128K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2015 FEATURES High-speed access time: 12, 15 ns Low active power: 160 mw (typical) Low standby power: 1000 µw (typical) CMOS standby Output
IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
IS62C10248AL IS65C10248AL
IS62C10248AL IS65C10248AL 1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POR ASYNCHRONOUS CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
P4C1256L LOW POWER 32K X 8 STATIC CMOS RAM FEATURES DESCRIPTION V CC. Current (Commercial/Industrial) Operating: 70mA/85mA CMOS Standby: 100µA/100µA
FEATURES Current (Commercial/Industrial) Operating: 70mA/85mA CMOS Standby: 100µA/100µA Access Times 55/70/85 Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM AUGUST 2009 FEATURES High-speed access time: 10, 12, 15, 20 ns Low active power: 400 mw (typical) Low standby power 250 µw (typical) CMOS standby 55 mw (typical) TTL
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION APRIL 2008 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center
IS61C25616AL IS61C25616AS IS64C25616AL IS64C25616AS
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) High-speed access time: 10ns, 12 ns Low Active Power: 150 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby LOW POR:
IS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM August 2016 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
IS63LV1024 IS63LV1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT FEATURES High-speed access times: 8, 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise
1M Words By 8 bit. Rev. No. History Issue Date Remark 1.0 Initial issue Aug.17,2016
Revision History Rev. No. History Issue Date Remark 1.0 Initial issue Aug.17,2016 i Rev. 1.0 PRODUCT DESCRIPTION... 1 FEATURES... 1 PRODUCT FAMILY... 1 PIN CONFIGURATIONS... 2 FUNCTIONAL BLOCK DIAGRAM...
IS62WV102416GALL/BLL IS65WV102416GALL/BLL. 1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM. FUNCTIONAL Block Diagram NOVEMBER 2017
1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM NOVEMBER 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
IS61WV10248ALL IS61WV10248BLL IS64WV10248BLL
1M x 8 HIGH-SPEED CMOS STATIC RAM MARCH 2017 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
IS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
IS61/64WV5128EFALL IS61/64WV5128EFBLL. 512Kx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
512Kx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC APRIL 2018 KEY FEATURES A0 A17 A18 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV5128EFALL) 2.4V-3.6V () Error Detection
IS62C25616EL, IS65C25616EL
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM AUGUST 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 5.0uA
5V 128K X 8 HIGH SPEED CMOS SRAM
5V 128K X 8 HIGH SPEED CMOS SRAM Revision History AS7C1024B Revision Details Date Rev 1.0 Preliminary datasheet prior to 2004 Rev 1.1 Die Revision A to B March 2004 Rev 2.0 PCN issued yield issues with
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM DEMBER 00 FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical)
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
64K x 16 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible