2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023

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Gladys Dorothy Maxwell
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1 FEATURES: SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo ROM + SRAM SST30VR021: 256K x8 ROM + 128K x8 SRAM SST30VR022: 256K x8 ROM + 256K x8 SRAM SST30VR023: 256K x8 ROM + 32K x8 SRAM ROM/RAM combo on a monolithic chip Equivalent ComboMemory (Flash + SRAM): SST31LF021E for code development and pre-production Wide Operating Voltage Range: V Chip Access Time SST30VR ns SST30VR021/ ns Low Power Dissipation: Standby: 3 µw (Typical) Operating: 10 mw (Typical) Fully Static Operation No clock or refresh required Three state Outputs Packages Available 32-pin TSOP (8mm x14mm) PRODUCT DESCRIPTION The SST30VR021/022/023 are ROM/RAM combo chips consisting of 2 Mbit Read Only Memory organized as 256 KBytes and Static Random Access Memory organized as 128, 256, and 32 KBytes. The device is fabricated using SST s advanced CMOS low power process technology. The SST30VR021/022/023 has an output enable input for precise control of the data outputs. It also has two (2) separate chip enable inputs for selection of either RAM or ROM and for minimizing current drain during power-down mode. The SST30VR021/022/023 is particularly well suited for use in low voltage ( V) supplies such as pagers, organizers and other handheld applications. FUNCTIONAL BLOCK DIAGRAM RAMCS# RAMCS# ROMCS# WE# Control Circuit WE# A MS -A 0 Address Buffer RAM ROMCS# ROM Data Buffer DQ 7 -DQ 0 Note: A MS = Most Significant Address 380 ILL B Silicon Storage Technology, Inc. S / The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.

2 A11 A9 A8 A13 A14 A17 RAMCS# V DD WE# A16 A15 A12 A7 A6 A5 A Standard Pinout Top View Die Up A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A0 A1 A2 A3 380 ILL F01.0 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP TABLE Symbol A 1 MS -A 0 WE# RAMCS# ROMCS# DQ 7 -DQ 0 V DD V SS 1: PIN DESCRIPTION Pin Name Address Inputs, for ROM: A MS = A 17, for RAM: A MS =A 16 for SST30VR021 A 17 for SST30VR022 A 14 for SST30VR023 Write Enable Input Output Enable RAM Enable Input ROM Enable Input Data Input/Output Power Supply Ground 1. A MS = Most significant address T

3 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature C to +85 C Storage Temperature C to +150 C Voltage on Any Pin Relative to V SS V to V DD + 0.5V Voltage on V DD Supply Relative to V SS V to 4.0V Power Dissipation W Soldering Temperature (10 Seconds Lead Only) C OPERATING RANGE Range Ambient Temp V DD Commercial 0 C to +70 C V Extended -20 C to +85 C V AC CONDITIONS OF TEST Input Pulse Level V DD Input & Output Timing Reference Levels V DD /2 Input Rise/Fall Time ns Output Load C L = 30 pf for 70 ns Output Load C L = 100 pf for 500 ns TABLE 2: RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min Max Units V DD Supply Voltage V V SS Ground 0 0 V V IH Input High Voltage 2.4 V DD V V IL Input Low Voltage V T TABLE 3: DC OPERATING CHARACTERISTICS V DD = 3.0 ± 0.3V Symbol Parameter Min Max Units Test Conditions I DD1 ROM Operating Supply Current (f) 1 ma ROMCS#=V IL, RAMCS#=V IH, V IN =V IH or V IL, I I/O =Opens I DD2 RAM Operating Supply Current 2.5+1(f) 1 ma ROMCS#=V IH, RAMCS#=V IL, I I/O =Opens I SB Standby V DD Current 10 µa ROMCS# V DD -0.2V, RAMCS# V DD -0.2V V IN V DD -0.2V or V IN 0.2V I LI Input Leakage Current -1 1 µa V IN =V SS to V DD I LO Output Leakage Current -1 1 µa ROMCS#=RAMCS#=V IH or =V IH or WE#=V IL, V I/O =V SS to V DD V OL Output Low Voltage 0.4 V I OL = 1.0 ma V OH Output High Voltage 2.2 V I OH = -0.5 ma 1. f = Frequency of operation (MHz) = 1/cycle time T

4 TABLE 4: CAPACITANCE (Ta = 25 C, f=1 Mhz) 2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM Parameter Description Test Condition Maximum C 1 I/O I/O Pin Capacitance V I/O = 0V 8 pf C 1 IN Input Capacitance V IN = 0V 6 pf 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. T V IHT INPUT V IT REFERENCE POINTS V OT OUTPUT V ILT 380 ILL F08.0 AC test inputs are driven at V IHT (0.9 V DD ) for a logic 1 and V ILT (0.1 V DD ) for a logic 0. Measurement reference points for inputs and outputs are V IT (0.5 V DD ) and V OT (0.5 V DD ). Input rise and fall times (10% 90%) are <5 ns. Note: V IT - V INPUT Test V OT - V OUTPUT Test V IHT - V INPUT HIGH Test V ILT - V INPUT LOW Test FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 380 ILL F09.0 FIGURE 3: A TEST LOAD EXAMPLE 4

5 AC CHARACTERISTICS I. ROM Operation TABLE 5: READ CYCLE TIMING PARAMETERS V DD = 3.0V±0.3 SST30VR SST30VR021/ Symbol Parameter Min Max Min Max Units T RC Read Cycle Time ns T AA Address Access Time ns T CO Chip Select to Output ns T OE Output Enable to Valid Output ns T LZ Chip Select to Low-Z Output 0 25 ns T OLZ Output Enable to Low-Z Output 0 25 ns T HZ Chip Disable to High-Z Output ns T OHZ Output Disable to High-Z Output ns T OH Output Hold from Address Change ns T TRC Address TOH TAA Data Out Previous Data Valid Data Valid 380 ILL F02.0 FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = = V IL ) 5

6 T RC Address T AA T HZ(1,2) ROMCS# T CO T LZ(2) T OHZ(1) T OE Data Out High-Z T OLZ Data Valid T OH Notes: 1. T HZ and T OHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the V OH or V OL. 2. At any given temperature and voltage condition T HZ (max) is less than T LZ (min) both for a given device and from device to device. 380 ILL F03.0 FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & CONTROLLED) 6

7 II. SRAM Operation (ROMCS# = V IH ) TABLE 6: READ CYCLE TIMING PARAMETERS V DD = 3.0V±0.3 SST30VR SST30VR021/ Symbol Parameter Min Max Min Max Units T RC Read Cycle Time ns T AA Address Access Time ns T CO Chip Select to Output ns T OE Output Enable to Valid Output ns T LZ Chip Select to Low-Z Output 0 25 ns T HZ Chip Disable to High-Z Output ns T OHZ Output Disable to High-Z Output ns T OH Output Hold from Address Change ns T TABLE 7: WRITE CYCLE TIMING PARAMETERS V DD = 3.0V±0.3 SST30VR SST30VR021/ Symbol Parameter Min Max Min Max Units T WC Write Cycle Time ns T CW Chip Select to End-of-Write ns T AW Address Valid to End-of-Write ns T AS Address Set-up Time 0 0 ns T WP Write Pulse Width ns T WR Write Recovery Time 0 0 ns T WHZ Write to Output High-Z ns T DW Data to Write Time Overlap ns T DH Data Hold from Write Time 0 0 ns T OW End Write to Output Low-Z 0 15 ns T

8 T RC Address T AA T OH Data Out Previous Data Valid Data Valid 380 ILL F04.0 FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) ( = RAMCS# = V IL, WE# = V IH ) TRC Address TAA TOE TOHZ(1) RAMCS# T CO T HZ (1,2) Data Out High-Z T LZ(2) Data Valid T OH Notes: 1. T HZ and T OHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the V OH or V OL. 2. At any given temperature and voltage condition T HZ (max) is less than T LZ (min) both for a given device and from device to device. 3. WE# is high for Read cycle. 4. Address valid prior to coincidence with RAMCS# transition low. 380 ILL F05.0 FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM ( OR RAMCS# CONTROLLED) 8

9 Address T WC T AW TCW(2) T WR(4) RAMCS# T AS(3) T WP(1) T OH WE# Data In High-Z TDW Data Valid TDH TWHZ(5) TOW Data Out High-Z (6) (7) (8) 380 ILL F07.0 Notes: 1. A write occurs during the overlap (T WP ) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, T WP is measured from the beginning of write to the end of write. 2. T CW is measured from the later of RAMCS# going low to the end of write. 3. T AS is measured from the address valid to the beginning of write. 4. T WR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. D OUT is the same phase of the latest written data in this write cycle. 8. D OUT is the read data of new address 9. ROMCS# = V IH FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE Address Inputs ROMCS# 1 RAMCS# 1 WE# DQ 0 -DQ 7 X H H X 2 X 2 Z Standby A 17 -A 0 L H X 2 H Z Output Floating A 17 -A 0 L H X 2 L Dout ROM Read Only A 3 MS -A 0 are valid 4 H L H H Z Output Floating Only A 3 MS -A 0 are valid 4 H L H L Dout RAM Read Only A 3 MS -A 0 are valid 4 H L L H Din RAM Write 1. If is forbidden for ROMCS# pin and RAMCS# pin to be 0 at the same time 2. X means Don t Care. 3. A MS = A 16 for SST30VR021, A 17 for SST30VR022, and A 14 for SST30VR For SST30VR021: A 17 must be fixed to L or H For SST30VR023: A 15, A 16, and A 17 must be fixed to L or H T

10 Device Speed Suffix1 Suffix2 SST30VR023 - XXX - X - XX - RXXXX C-Spec Number Package Modifier H = 32 leads Numeric = Die modifier Package Type W = TSOP (8mm x 14mm) U = Die only Temperature Range C = Commercial = 0 C to +70 C E = Extended = -20 C to +85 C Read Access Speed 70 = 70 ns 500 = 500 ns Device Density 021 = 2 Mbit ROM + 1 Mbit SRAM 022 = 2 Mbit ROM + 2 Mbit SRAM 023 = 2 Mbit ROM Kbit SRAM Voltage Range V = V Device Family 30 = SST30VR021 Valid combinations SST30VR C-WH SST30VR C-U1 SST30VR E-WH SST30VR022 Valid combinations SST30VR C-WH SST30VR C-U1 SST30VR E-WH SST30VR023 Valid combinations SST30VR C-WH SST30VR C-U1 SST30VR E-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. 10

11 PACKAGING DIAGRAMS Pin # 1 Identifier BSC TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH 11

12 Silicon Storage Technology, Inc Sonora Court Sunnyvale, CA Telephone Fax or 12

2M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014

2M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014 Revision History Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 2,097,152-bit high-speed Static Random Access Memory organized as 128K(256) words