I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

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1 Features High speed t AA = 12 ns Low active power 1320 mw (max.) Low CMOS standby power (Commercial L version) 2.75 mw (max.) 2.0V Data Retention (400 µw at 2.0V retention) Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with and OE features Available in Pb-free and non Pb-free 36-Lead (400-Mil) Molded SOJ Logic Block Diagram Functional Description [1] 512K x 8 Static RAM The CY7C1049B is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable () and Write Enable () inputs LOW. Data on the eight I/O pins (I/O 0 through I/O 7 ) is then written into the location specified on the address pins (A 0 through A 18 ). Reading from the device is accomplished by taking Chip Enable () and Output Enable (OE) LOW while forcing Write Enable () HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O 0 through I/O 7 ) are placed in a high-impedance state when the device is deselected ( HIGH), the outputs are disabled (OE HIGH), or during a write operation ( LOW, and LOW). The CY7C1049B is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. Pin Configuration SOJ Top View A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 ROW DECODER INPUT BUFFER 512K x 8 ARRAY SENSE AMPS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 A 0 A 1 A 2 A 3 A 4 I/O 0 I/O 1 GND I/O 2 I/O3 A 5 A 6 A 7 A 8 A NC A 18 A 17 A 16 A 15 OE I/O 7 I/O 6 GND I/O 5 I/O 4 A 14 A 13 A 12 A 11 A 10 NC COLUMN DECODER POR DOWN I/O 6 I/O 7 OE A11 A12 A13 A 14 A 15 A16 A17 A18 Note: 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: Rev. *B Revised August 31, 2006

2 Selection Guide Maximum Access Time (ns) Maximum Operating Current (ma) Maximum CMOS Standby Commercial Current (ma) Industrial Commercial L Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage on to Relative GND [2] V to +7.0V DC Voltage Applied to Outputs in High Z State [2] V to + 0.5V DC Input Voltage [2] V to + 0.5V Current into Outputs (LOW) ma Static Discharge Voltage... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current... >200 ma Operating Range Ambient Range Temperature Commercial 0 C to +70 C 4.5V 5.5V Industrial 40 C to +85 C Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit V OH Output HIGH Voltage = Min., I OH = 4.0 ma V V OL Output LOW Voltage = Min., I OL = 8.0 ma V V IH Input HIGH Voltage V IL Input LOW Voltage [2] V I IX Input Leakage Current GND < V I < µa I OZ Output Leakage Current GND < V OUT <, Output Disabled µa I CC I SB1 I SB2 Operating Supply Current Automatic Power-Down Current TTL Inputs Automatic Power-Down Current CMOS Inputs = Max., ma f = f MAX = 1/t RC Max., > V IH V IN > V IH or V IN < V IL, f = f MAX Max., > 0.3V, V IN > 0.3V, or V IN < 0.3V, f = ma Com l ma Com l L ma Ind l ma V Note: 2. Minimum voltage is 2.0V for pulse durations of less than 20 ns. Document #: Rev. *B Page 2 of 9

3 Capacitance [3] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 8 pf C OUT I/O Capacitance = 5.0V 8 pf AC Test Loads and Waveforms R1 481Ω 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE (a) R1 481 Ω 5V OUTPUT R2 5 pf 255Ω INCLUDING JIG AND SCOPE (b) R2 255Ω 3.0V GND 3 ns 10% ALL INPUT PULSES 90% 90% 10% 3 ns Equivalent to: THÉ VENIN EQUIVALENT 167Ω OUTPUT 1.73V Note: 3. Tested initially and after any design or process changes that may affect these parameters. Document #: Rev. *B Page 3 of 9

4 Switching Characteristics Over the Operating Range [4] CY7C1049B Parameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle t power (typical) to the First Access [5] ms t RC Read Cycle Time ns t AA Address to Data Valid ns t OHA Data Hold from Address Change ns t A LOW to Data Valid ns t DOE OE LOW to Data Valid ns t LZOE OE LOW to Low Z [7] ns t HZOE OE HIGH to High Z [6, 7] ns t LZ LOW to Low Z [7] ns t HZ HIGH to High Z [6, 7] ns t PU LOW to Power-Up ns t PD HIGH to Power-Down ns [8, 9] Write Cycle t WC Write Cycle Time ns t S LOW to Write End ns t AW Address Set-Up to Write End ns t HA Address Hold from Write End ns t SA Address Set-Up to Write Start ns t P Pulse Width ns t SD Data Set-Up to Write End ns t HD Data Hold from Write End ns t LZ HIGH to Low Z [7] ns t HZ LOW to High Z [6, 7] ns Data Retention Characteristics Over the Operating Range Parameter Description Conditions [11] Min. Max. Unit V DR for Data Retention 2.0 V I CCDR Data Retention Current Com l L = V DR = 2.0V, 200 µa [3] > 0.3V t CDR Chip Deselect to Data Retention Time 0 ns V IN > 0.3V or V IN < 0.3V [10] t R Operation Recovery Time t RC ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t power time has to be provided initially before a read/write operation is started. 6. t HZOE, t HZ, and t HZ are specified with a load capacitance of 5 pf as in part (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 7. At any given temperature and voltage condition, t HZ is less than t LZ, t HZOE is less than t LZOE, and t HZ is less than t LZ for any given device. 8. The internal write time of the memory is defined by the overlap of LOW, and LOW. and must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 ( controlled, OE LOW) is the sum of t HZ and t SD. 10. t r < 3 ns for all the speeds 11. No input may exceed + 0.5V. Document #: Rev. *B Page 4 of 9

5 Data Retention Waveform 3.0V DATA RETENTION MODE V DR > 2V 3.0V t CDR t R Switching Waveforms Read Cycle No. 1 [12, 13] t RC t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID [13, 14] Read Cycle No. 2 (OE Controlled) t RC t A OE t HZOE thz t DOE DATA OUT t LZOE HIGH IMPEDAN DATA VALID HIGH IMPEDAN SUPPLY CURRENT t LZ t PU 50% t PD 50% I CC I SB Notes: 12. Device is continuously selected. OE, = V IL. 13. is HIGH for read cycle. 14. Address valid prior to or coincident with transition LOW. Document #: Rev. *B Page 5 of 9

6 Switching Waveforms (continued) Write Cycle No. 1 ( Controlled) [15, 16] t WC t S t SA t AW t P t S t HA t SD t HD DATA I/O DATA VALID [15, 16] Write Cycle No. 2 ( Controlled, OE HIGH During Write) t WC t S t AW t HA t SA t P OE t SD t HD DATA I/O NOTE 17 DATA IN VALID t HZOE Notes: 15. Data I/O is high impedance if OE = V IH. 16. If goes HIGH simultaneously with going HIGH, the output remains in a high-impedance state. 17. During this period the I/Os are in the output state and input signals should not be applied. Document #: Rev. *B Page 6 of 9

7 Switching Waveforms (continued) Write Cycle No. 3 ( Controlled, OE LOW) [16] t WC t S t AW t HA t SA t P t SD t HD DATA I/O NOTE 17 DATA VALID t HZ t LZ Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 12 CY7C1049B-12VC Lead (400-Mil) Molded SOJ Commercial CY7C1049B-12VXC 36-Lead (400-Mil) Molded SOJ (Pb-free) 15 CY7C1049B-15VC 36-Lead (400-Mil) Molded SOJ CY7C1049B-15VXC 36-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1049B-15VI 36-Lead (400-Mil) Molded SOJ Industrial CY7C1049B-15VXI 36-Lead (400-Mil) Molded SOJ (Pb-free) 17 CY7C1049BL-17VC 36-Lead (400-Mil) Molded SOJ Commercial Document #: Rev. *B Page 7 of 9

8 Package Diagram 36-lead (400-Mil) Molded SOJ ( ) *B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: Rev. *B Page 8 of 9 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Document History Page Document Title: CY7C1049B 512K x 8 Static RAM Document Number: 38-05169 REV. ECN NO. Issue Date Orig.

9 Document History Page Document Title: CY7C1049B 512K x 8 Static RAM Document Number: REV. ECN NO. Issue Date Orig. of Change Description of Change ** /02/01 SZV Change from Spec number: to *A /16/02 A Add applications foot note to data sheet, page 1 *B See ECN NXR Removed 20 ns and 25 ns speed bin Changed the description of I IX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table Document #: Rev. *B Page 9 of 9

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7 A 15 7

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7 A 15 7 Features High speed t AA = 12 ns Low active power 495 mw (max.) Low CMOS standby power 11 mw (max.) (L Version) 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs