2K x 8 Dual-Port Static RAM

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2K x 8 Dual-Port Static RAM Features True dual-ported memory cells that enable simultaneous reads of the same memory location 2K x 8 organization 0.

1 2K x 8 Dual-Port Static RAM Features True dual-ported memory cells that enable simultaneous reads of the same memory location 2K x 8 organization 0.65 micron CMOS for optimum speed and power High speed access: 15 ns ow operating power: I CC = 110 ma (maximum) Fully asynchronous operation Automatic power down Master CY7C132/CY7C136/CY7C136A [1] easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146 BUSY output flag on CY7C132/CY7C136/CY7C136A; BUSY input on CY7C142/CY7C146 INT flag for port to port communication (52-Pin PCC/PQFP versions) CY7C136, CY7C136A, and CY7C146 available in 52-pin PCC and 52-pin PQFP packages Pb-free packages available Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM, in conjunction with the CY7C142/CY7C146 SAVE dual-port device. They are used in systems that require 16-bit or greater word widths. This is the solution to applications that require shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PCC version, INT is an interrupt flag indicating that data is placed in an unique location (7FF for the left port and 7FE for the right port). An automatic power down feature is controlled independently on each port by the chip enable (CE) pins. ogic Block Diagram R/W CE OE R/W R OE R 7 0 [2] BUSY CONTRO CONTRO 7R 0R [2] BUSY R A 10 A 0 ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER A 10R A 0R CE OE ARBITRATION OGIC (7C132/7C136 ONY) AND INTERRUPTOGIC (7C136/7C146ONY) OE R R/W R/W R INT [3] [3] INT R Notes 1. CY7C136 and CY7C136A are functionally identical. 2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 3. Open drain outputs; pull up resistor required. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: Rev. *E Revised March 24, 2009

2 Pinouts Figure Pin PCC (Top View) Figure Pin PQFP (Top View) A 0 OE A 10 INT BUSY R/W CE V CC R/W R A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC 7R NC GND 0R 1R 2R 3R 4R 5R 6R BUSY INT R A 10R R A 0 OE A 10 INT BUSY R/W CE V CC R/W R BUSY INT R R 7C136/7C136A 7C146 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC 7R NC GND 0R 1R 2R 3R 4R 5R 6R A 10R 7C136/7C136A 7C146 Selection Guide Specification 7C [4] 7C C [4] 7C C C C C C C C C C C C C C C C C C136A-55 7C C Maximum Access Time ns Maximum Operating Current Com l/ind ma Maximum Standby Current Com l/ind ma Shaded areas contain preliminary information. Unit Note: ns and 25 ns version available in PQFP and PCC packages only. Document #: Rev. *E Page 2 of 15

3 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage to Ground Potential (Pin 48 to Pin 24) V to +7.0V DC Voltage Applied to Outputs in High Z State V to +7.0V DC Input Voltage V to +7.0V Output Current into Outputs (OW) ma Static Discharge Voltage... > 2001V (per MI-STD-883, Method 3015) atch up Current... > 200 ma Operating Range Range Ambient Temperature V CC Commercial 0 C to +70 C 5V ± 10% Industrial 40 C to +85 C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions V OH V O V IH V I Output HIGH voltage Output OW voltage Input HIGH voltage Input OW voltage 7C [4] 7C C [4] 7C136-25, 30 7C C146-25, 30 7C132-35,45 7C136-35,45 7C142-35,45 7C146-35,45 7C C C136A-55 7C C Min Max Min Max Min Max Min Max V CC = Min., I OH = 4.0 ma V I O = 4.0 ma V I O = 16.0 ma [5] V Notes 5. BUSY and INT pins only. 6. Duration of the short circuit should not exceed 30 seconds. 7. At f = f MAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/t rc and using AC Test Waveforms input levels of GND to 3V. Unit V I IX Input load current GND < V I < V CC μa I OZ Output leakage GND < V O < V CC, Output Disabled μa current I OS Output short circuit current [6] V CC = Max., V OUT = GND ma I CC V CC Operating Supply Current CE = V I, Outputs Open, [7] f = f MAX Com l/ Ind l ma I SB1 I SB2 I SB3 I SB4 Standby current both ports, TT Inputs Standby Current One Port, TT Inputs Standby Current Both Ports, CMOS Inputs Standby Current One Port, CMOS Inputs Shaded areas contain preliminary information. CE and > V IH, f = f MAX [7] CE or > V IH, Active Port Outputs Open, f = f MAX [7] Both Ports CE and > V CC 0.2V, V IN > V CC 0.2V or V IN < 0.2V, f = 0 One Port CE or > V CC 0.2V, V IN > V CC 0.2V or V IN < 0.2V, Active Port Outputs Open, f = f MAX [7] Com l/ Ind l Com l/ Ind l Com l/ Ind l Com l/ Ind l ma ma ma ma Document #: Rev. *E Page 3 of 15

4 Capacitance This parameter is guaranteed but not tested. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, V CC = 5.0V 15 pf C OUT Output Capacitance 10 pf 5V OUTPUT 30 pf INCUDING JIG AND SCOPE Equivalent to: R1 893Ω (a) R2 347Ω TH ÉVENIN EQUIVAENT Figure 3. AC Test oads and Waveforms 5V OUTPUT 250Ω OUTPUT 1.4V 5pF INCUDING JIG AND SCOPE 3.0V R1 893Ω (b) R2 347Ω 10% GND <5ns BUSY OR INT 5V <5ns 281Ω 30 pf BUSY Output oad (CY7C132/CY7C136 Only) A INPUT PUSES 90% 90% 10% Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) [8] Parameter Description 7C [4] 7C C [4] 7C C C C C C C Min Max Min Max Min Max Read Cycle t RC Read Cycle Time ns t AA Address to Data Valid [9] ns t OHA Data Hold from Address Change ns t ACE CE OW to Data Valid [9] ns t DOE OE OW to Data Valid [9] ns t ZOE OE OW to ow Z [7, 10] ns t HZOE OE HIGH to High Z [7, 10, 11] ns t ZCE CE OW to ow Z [7, 10] ns t HZCE CE HIGH to High Z [7, 10, 11] ns t PU CE OW to Power Up [7] ns t PD CE HIGH to Power Down [7] ns Shaded areas contain preliminary information. Notes 8. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified I O /I OH, and 30 pf load capacitance. 9. AC test conditions use V OH = 1.6V and V O = 1.4V. 10. At any given temperature and voltage condition for any given device, t HZCE is less than t ZCE and t HZOE is less than t ZOE. 11. t ZCE, t ZWE, t HZOE, t ZOE, t HZCE, and t HZWE are tested with C = 5pF as in (b) of AC Test oads and Waveforms. Transition is measured ± 500 mv from steady state voltage. Unit Document #: Rev. *E Page 4 of 15

5 Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) [8] (continued) Parameter Write Cycle [12] t WC Write Cycle Time ns t SCE CE OW to Write End ns t AW Address Setup to Write End ns t HA Address Hold from Write End ns t SA Address Setup to Write Start ns t PWE R/W Pulse Width ns t SD Data Setup to Write End ns t HD Data Hold from Write End ns t HZWE R/W OW to High Z [7] ns t ZWE R/W HIGH to ow Z [7] ns Busy/Interrupt Timing t BA BUSY OW from Address Match ns t BHA BUSY HIGH from Address Mismatch [13] ns t BC BUSY OW from CE OW ns t BHC BUSY HIGH from CE HIGH [13] ns t PS Port Set Up for Priority ns t WB R/W OW after BUSY OW [14] ns t WH R/W HIGH after BUSY HIGH ns t BDD BUSY HIGH to Valid Data ns t DDD Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns t WDD Write Pulse to Data Delay Note 15 Note 15 Note 15 ns Interrupt Timing [16] t WINS R/W to INTERRUPT Set Time ns t EINS CE to INTERRUPT Set Time ns t INS Address to INTERRUPT Set Time ns t OINR OE to INTERRUPT Reset Time [13] ns t EINR CE to INTERRUPT Reset Time [13] ns t INR Address to INTERRUPT Reset Time [13] ns Shaded areas contain preliminary information. Description 7C [4] 7C C [4] 7C C C C C C C Min Max Min Max Min Max Notes 12. The internal write time of the memory is defined by the overlap of CE OW and R/W OW. Both signals must be OW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. 13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 14. CY7C142/CY7C146 only. 15. A write operation on Port A, where Port A has priority, leaves the data on Port B s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B s address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read pin PCC and PQFP versions only. Unit Document #: Rev. *E Page 5 of 15

6 Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) [8] Parameter Description 7C C C C C C C C C C C136A-55 7C C Min Max Min Max Min Max Read Cycle t RC Read Cycle Time ns t AA Address to Data Valid [9] ns t OHA Data Hold from Address Change ns t ACE CE OW to Data Valid [9] ns t DOE OE OW to Data Valid [9] ns t ZOE OE OW to ow Z [7, 10] ns t HZOE OE HIGH to High Z [7, 10, 11] ns t ZCE CE OW to ow Z [7, 10] ns t HZCE CE HIGH to High Z [7, 10, 11] ns t PU CE OW to Power Up [7] ns t PD CE HIGH to Power Down [7] ns Write Cycle [12] t WC Write Cycle Time ns t SCE CE OW to Write End ns t AW Address Setup to Write End ns t HA Address Hold from Write End ns t SA Address Setup to Write Start ns t PWE R/W Pulse Width ns t SD Data Setup to Write End ns t HD Data Hold from Write End ns t HZWE R/W OW to High Z [7] ns t ZWE R/W HIGH to ow Z [7] ns Busy/Interrupt Timing t BA BUSY OW from Address Match ns t BHA BUSY HIGH from Address Mismatch [13] ns t BC BUSY OW from CE OW ns t BHC BUSY HIGH from CE HIGH [13] ns t PS Port Set Up for Priority ns t WB R/W OW after BUSY OW [14] ns t WH R/W HIGH after BUSY HIGH ns t BDD BUSY HIGH to Valid Data ns t DDD Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns t WDD Write Pulse to Data Delay Note 15 Note 15 Note 15 ns Unit Document #: Rev. *E Page 6 of 15

7 Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) [8] (continued) Parameter Interrupt Timing [16] Description 7C C C C C C C C C C C136A-55 7C C Min Max Min Max Min Max t WINS R/W to INTERRUPT Set Time ns t EINS CE to INTERRUPT Set Time ns t INS Address to INTERRUPT Set Time ns t OINR OE to INTERRUPT Reset Time [13] ns t EINR CE to INTERRUPT Reset Time [13] ns t INR Address to INTERRUPT Reset Time [13] ns Unit Switching Waveforms [17, 18] Figure 4. Read Cycle No. 1 (Either Port-Address Access) t RC ADDRESS t OHA t AA DATA OUT PREVIOUS DATA VAID DATA VAID Figure 5. Read Cycle No. 2 (Either Port-CE/OE )[17, 19] CE OE t ACE t ZOE t DOE t HZOE t HZCE t ZCE DATA OUT DATA VAID I CC t PU t PD I SB Notes 17. R/W is HIGH for read cycle. 18. Device is continuously selected, CE = V I and OE = V I. 19. Address valid prior to or coincident with CE transition OW. Document #: Rev. *E Page 7 of 15

8 Switching Waveforms (continued) Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A) t RC ADDRESS R R/W R ADDRESS MATCH t PWE D INR VAID t PS ADDRESS ADDRESS MATCH BUSY t BHA t BA t BDD DOUT VAID t WDD t DDD [12, 20] Figure 7. Write Cycle No.1 (OE Three-States Data s Either Port) t WC ADDRESS CE t SCE R/W t SA t AW t PWE t HA t SD t HD DATA IN DATA VAID OE D OUT t HZOE HIGH IMPEDANCE Note 20. If OE is OW during a R/W controlled write cycle, the write pulse width must be the larger of t PWE or t HZWE + t SD to allow the data pins to enter high impedance and for data to be placed on the bus for the required t SD. Document #: Rev. *E Page 8 of 15

9 Switching Waveforms (continued) Figure 8. Write Cycle No. 2 (R/W Three-States Data s Either Port) [12, 21] ADDRESS t WC t SCE t HA CE R/W t SA t AW t PWE t SD t HD DATA IN DATA VAID D OUT t HZWE t ZWE HIGH IMPEDANCE Figure 9. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: ADDRESS,R ADDRESS MATCH CE t PS t BC t BHC BUSY R Valid First: ADDRESS,R ADDRESS MATCH CE t PS t BC t BHC BUSY Note 21. If the CE OW transition occurs simultaneously with or after the R/W OW transition, the outputs remain in a high impedance state. Document #: Rev. *E Page 9 of 15

10 Switching Waveforms (continued) Figure 10. Busy Timing Diagram No. 2 (Address Arbitration) eft Address Valid First: ADDRESS t PS t RC or t WC ADDRESS MATCH ADDRESS MISMATCH ADDRESS R BUSY R Right Address Valid First: ADDRESS R t BA t RC or t WC ADDRESS MATCH t PS t BHA ADDRESS MISMATCH ADDRESS BUSY t BA t BHA Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146) CE R/W t PWE BUSY t WB t WH Document #: Rev. *E Page 10 of 15

11 Switching Waveforms (continued) Interrupt Timing Diagrams [16] Figure 12. eft Side Sets INT R t WC ADDRESS WRITE 7FF CE t INS t HA R/W t EINS INT R t SA t WINS Figure 13. Right Side Clears INT R t RC ADDRESS R t HA t INR READ 7FF t EINR R/W R OE R t OINR INT R Figure 14. Right Side Sets INT t WC ADDRESS R WRITE 7FE t INS t HA R/W R t EINS INT t SA twins Figure 15. Right Side Clears INT t RC ADDRESS CE t HA t INR READ 7FE t EINR R/W OE t OINR INT Document #: Rev. *E Page 11 of 15

12 NORMAIZED I CC, I SB NORMAIZED t AA NORMAIZED t PC NORMAIZED SUPPY CURRENT vs. SUPPY VOTAGE I CC Figure 16. Typical DC and AC Characteristics SUPPY VOTAGE (V) NORMAIZED ACCESS TIME vs. SUPPY VOTAGE SUPPY VOTAGE (V) TYPICA POWER-ON CURRENT vs. SUPPY VOTAGE NORMAIZED t AA I SB3 0.2 T A = 25 C NORMAIZED I CC, I SB DETA t AA (ns) NORMAIZED SUPPY CURRENT vs. AMBIENT TEMPERATURE I CC OUTPUT SOURCE CURRENT (ma) OUTPUT SOURCE CURRENT vs. OUTPUT VOTAGE V CC = 5.0V V CC = 5.0V V IN = 5.0V T A = 25 C 40 AMBIENT TEMPERATURE ( C) NORMAIZED ACCESS TIME vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE ( C) TYPICA ACCESS TIME CHANGE vs. OUTPUT OADING SUPPY VOTAGE (V) CAPACITANCE (pf) I SB3 V CC = 5.0V V CC = 4.5V T A = 25 C OUTPUT SINK CURRENT (ma) NORMAIZED I CC OUTPUT VOTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOTAGE V CC = 5.0V T A = 25 C OUTPUT VOTAGE (V) NORMAIZED I CC vs. CYCE TIME 1.25 V CC = 5.0V T A = 25 C V IN = 0.5V CYCE FREQUENCY (MHz) Document #: Rev. *E Page 12 of 15

13 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 15 CY7C136-15JC Pin Plastic eaded Chip Carrier Commercial CY7C136-15NC Pin Plastic Quad Flatpack 25 CY7C136-25JC Pin Plastic eaded Chip Carrier Commercial CY7C136-25JXC 52-Pin Plastic eaded Chip Carrier (Pb-Free) CY7C136-25NC Pin Plastic Quad Flatpack CY7C136-25NXC 52-Pin Plastic Quad Flatpack (Pb-Free) CY7C136-25JXI Pin Plastic eaded Chip Carrier (Pb-Free) Industrial 30 CY7C136-30JC Pin Plastic eaded Chip Carrier Commercial CY7C136-30NC Pin Plastic Quad Flatpack CY7C136-30JI Pin Plastic eaded Chip Carrier Industrial 35 CY7C136-35JC Pin Plastic eaded Chip Carrier Commercial CY7C136-35NC Pin Plastic Quad Flatpack CY7C136-35JI Pin Plastic eaded Chip Carrier Industrial 45 CY7C136-45JC Pin Plastic eaded Chip Carrier Commercial CY7C136-45NC Pin Plastic Quad Flatpack CY7C136-45JI Pin Plastic eaded Chip Carrier Industrial 55 CY7C136-55JC Pin Plastic eaded Chip Carrier Commercial CY7C136-55JXC 52-Pin Plastic eaded Chip Carrier (Pb-Free) CY7C136-55NC Pin Plastic Quad Flatpack CY7C136-55NXC 52-Pin Plastic Quad Flatpack (Pb-Free) CY7C136-55JI Pin Plastic eaded Chip Carrier Industrial CY7C136A-55JXI 52-Pin Plastic eaded Chip Carrier (Pb-Free) CY7C136-55NI Pin Plastic Quad Flatpack CY7C136A-55NXI 52-Pin Plastic Quad Flatpack (Pb-Free) 15 CY7C146-15JC Pin Plastic eaded Chip Carrier Commercial CY7C146-15NC Pin Plastic Quad Flatpack 25 CY7C146-25JC Pin Plastic eaded Chip Carrier Commercial CY7C146-25JXC 52-Pin Plastic eaded Chip Carrier (Pb-Free) CY7C146-25NC Pin Plastic Quad Flatpack 30 CY7C146-30JC Pin Plastic eaded Chip Carrier Commercial CY7C146-30NC Pin Plastic Quad Flatpack CY7C146-30JI Pin Plastic eaded Chip Carrier Industrial 35 CY7C146-35JC Pin Plastic eaded Chip Carrier Commercial CY7C146-35NC Pin Plastic Quad Flatpack CY7C146-35JI Pin Plastic eaded Chip Carrier Industrial 45 CY7C146-45JC Pin Plastic eaded Chip Carrier Commercial CY7C146-45NC Pin Plastic Quad Flatpack CY7C146-45JI Pin Plastic eaded Chip Carrier Industrial 55 CY7C146-55JC Pin Plastic eaded Chip Carrier Commercial CY7C146-55JXC 52-Pin Plastic eaded Chip Carrier (Pb-Free) CY7C146-55NC Pin Plastic Quad Flatpack CY7C146-55JI Pin Plastic eaded Chip Carrier Industrial Document #: Rev. *E Page 13 of 15

14 Package Diagrams Figure Pin Plastic eaded Chip Carrier, *A Figure Pin Plastic Quad Flatpack, ** Document #: Rev. *E Page 14 of 15

Document History Page Document Title: CY7C132, CY7C136, 2K x 8 Dual-Port Static RAM Document Number: 38-06031 Revision Sales, Solutions, and egal Information Worldwide Sales and Design Support

15 Document History Page Document Title: CY7C132, CY7C136, 2K x 8 Dual-Port Static RAM Document Number: Revision Sales, Solutions, and egal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products ECN PSoC Clocks & Buffers Wireless Memories Image Sensors Submission Date Orig. of Change psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions Description of Change ** /21/01 SZV Change from Spec number: *A /03/03 JFU Added CY7C136-55NI to Order Information *B See ECN YDT Removed cross information from features section *C See ECN YIM Added Pb-Free ogo Added Pb-Free parts to ordering information: CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC, CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC *D /17/08 VKN/PYRS Added CY7C136-25JXI part Removed CY7C132/142 from the Ordering information table Removed 48-Pin DIP and 52-Pin Square CC package from the data sheet *E /24/2009 VKN/AESA Added CY7C136A-55JXI, and CY7C136A-55NXI parts. General psoc.cypress.com/solutions ow Power/ow Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog CD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPIED, WITH REGARD TO THIS MATERIA, INCUDING, BUT NOT IMITED TO, THE IMPIED WARRANTIES OF MERCHANTABIITY AND FITNESS FOR A PARTICUAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: Rev. *E Revised March 24, 2009 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders.

1K x 8 Dual-Port Static RAM

1K x 8 Dual-Port Static RAM Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power High-speed access: 15 ns ow operating power: