1K x 8 Dual-Port Static RAM

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1 Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power High-speed access: 15 ns ow operating power: I CC = 110 ma (max.) Fully asynchronous operation Automatic power-down Master CY7C130/CY7C131 easily expands data bus width to 16 or more bits using slave BUSY output flag on CY7C130/CY7C131; BUSY input on INT flag for port-to-port communication Available in 48-pin DIP (CY7C130/140), 52-pin PCC, 52-Pin TQFP. Pb-Free packages available ogic Block Diagram 1K x 8 Dual-Port Static RAM Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C130 and CY7C140 are available in 48-pin DIP. The CY7C131 and CY7C141 are available in 52-pin PCC, 52-pin Pb-free PCC, 52-pin PQFP and 52-pin Pb-free PQFP. Pin Configurations R/W CE OE R/W R CE R OE R DIP Top View 7 0 [1] BUSY A 9 A 0 ADDRESS DECODER CE OE R/W CONTRO MEMORY ARRAY ARBITRATION OGIC (7C130/7C131 ONY) AND INTERRUPT OGIC CONTRO ADDRESS DECODER CE R OE R R/W R 7R 0R BUSY R [2] [2] INT INT R A 9R A 0R CE R/W BUSY INT OE A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A GND C C V CC CE R R/W R BUSY R INT R OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R 7R 6R 5R 4R 3R 2R 1R 0R Note: 1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor (Slave): BUSY is input. 2. Open drain outputs: pull-up resistor required. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: Rev. *D Revised August 29, 2005

2 Pin Configuration (continued) PCC Top View PQFP Top View A 0 OE NC INT BUSY R/W CE V CC CE R R/W R BUSY INT R NC A 0 OE NC INT BUSY R/W CE V CC CE R R/W R BUSY INT R NC R R A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A NC GND 7C131 7C141 0R 1R 2R 3R 4R 5R 6R OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC 7R A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A C131 7C OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC 7R NC GND 0R 1R 2R 3R 4R 5R 6R Pin Definitions eft Port Right Port Description CE CE R Chip Enable R/W R/W R Read/Write Enable OE OE R Output Enable A 0 A 11/12 A 0R A 11/12R Address 0 15/17 0R 15/17R Data Bus Input/Output INT INT R Interrupt Flag BUSY BUSY R Busy Flag V CC Power GND Ground Selection Guide 7C [3] 7C C [3] 7C C C C C C C C C C C C C C C C C Unit Maximum Access Time ns Maximum Operating Com l/ind ma Current Military Maximum Standby Com l/ind ma Current Military Shaded areas contain preliminary information. Note: and 25-ns version available only in PCC/PQFP packages. Document #: Rev. *D Page 2 of 19

3 Maximum Ratings [4] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage to Ground Potential (Pin 48 to Pin 24) V to +7.0V DC Voltage Applied to Outputs in High Z State V to +7.0V DC Input Voltage V to +7.0V Output Current into Outputs (OW)...20 ma Static Discharge Voltage... >2001V (per MI-STD-883, Method 3015) atch-up Current... >200 ma Operating Range Range Ambient Temperature V CC Commercial 0 C to +70 C 5V ± 10% Industrial 40 C to +85 C 5V ± 10% Military [5] 55 C to +125 C 5V ± 10% Electrical Characteristics Over the Operating Range [6] 7C [3] 7C C [3] 7C131-25,30 7C C141-25,30 7C130-35,45 7C131-35,45 7C140-35,45 7C141-35,45 7C C C C Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit V OH Output HIGH V CC = Min., I OH = 4.0 ma V Voltage V O Output OW I O = 4.0 ma V Voltage I O = 16.0 ma [7] V IH Input HIGH Voltage V V I Input OW Voltage V I IX Input eakage GND < V I < V CC µa Current I OZ I OS I CC I SB1 I SB2 I SB3 Output eakage Current Output Short V [8, 9] Circuit Current V CC Operating Supply Current Standby Current Both Ports, TT Inputs Standby Current One Port, TT Inputs Standby Current Both Ports, CMOS Inputs Shaded areas contain preliminary information. GND < V O < V CC, Output Disabled CC = Max., V OUT = GND CE = V I, Outputs Open, f = f MAX [10] CE and CE R > V IH, f = f MAX [10] CE or CE R > V IH, Active Port Outputs Open, f = f [10] MAX Both Ports CE and CE R > V CC 0.2V, V IN > V CC 0.2V or V IN < 0.2V, f = µa ma Com l ma Mil Com l ma Mil Com l ma Mil Com l ma Mil Note: 4. The Voltage on any input or pin cannot exceed the power pin during power-up. 5. T A is the instant on case temperature 6. See the last page of this specification for Group A subgroup testing information. 7. BUSY and INT pins only. 8. Duration of the short circuit should not exceed 30 seconds. 9. This parameter is guaranteed but not tested. 10. At f = f MAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/t RC and using AC Test Waveforms input levels of GND to 3V. Document #: Rev. *D Page 3 of 19

4 Electrical Characteristics Over the Operating Range [6] (continued) Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit I SB4 Standby Current One Port CE or Com l ma One Port, CMOS Inputs CE R > V CC 0.2V, Mil V IN > V CC 0.2V or V IN < 0.2V, Active Port Outputs Open, [10] f = f MAX Capacitance [9] 7C [3] 7C C [3] 7C131-25,30 7C C141-25,30 7C130-35,45 7C131-35,45 7C140-35,45 7C141-35,45 7C C C C Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 15 pf C OUT Output Capacitance V CC = 5.0V 10 pf AC Test oads and Waveforms 5V OUTPUT Equivalent to: 30 pf INCUDING JIGAND SCOPE R1 893Ω (a) R2 347Ω THÉVENIN EQUIVAENT 250Ω OUTPUT 1.40V 5V OUTPUT 5pF INCUDING JIGAND SCOPE R1 893Ω (b) 3.0V R2 347Ω 10% GND 5ns BUSY OR INT BUSY Output oad A INPUT PUSES (CY7C130/CY7C131 ONY) 90% 90% 10% 5ns 5V 281Ω 30 pf Document #: Rev. *D Page 4 of 19

5 Switching Characteristics Over the Operating Range [6, 11] 7C [3] 7C C [3] 7C C C C C C C Parameter Description Min. Max. Min. Max. Min. Max. Unit READ CYCE t RC Read Cycle Time ns t AA Address to Data Valid [12] ns t OHA Data Hold from Address Change ns t ACE CE OW to Data Valid [12] ns t DOE OE OW to Data Valid [12] ns t ZOE OE OW to ow Z [9, 13, 14] ns t HZOE OE HIGH to High Z [9, 13, 14] ns t ZCE CE OW to ow Z [9, 13, 14] ns t HZCE CE HIGH to High Z [9, 13, 14] ns t PU CE OW to Power-Up [9] ns t PD CE HIGH to Power-Down [9] ns WRITE CYCE [15] t WC Write Cycle Time ns t SCE CE OW to Write End ns t AW Address Set-Up to Write End ns t HA Address Hold from Write End ns t SA Address Set-Up to Write Start ns t PWE R/W Pulse Width ns t SD Data Set-Up to Write End ns t HD Data Hold from Write End ns t HZWE R/W OW to High Z [14] ns t ZWE R/W HIGH to ow Z [14] ns Shaded areas contain preliminary information. Note: 11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified I O /I OH, and 30-pF load capacitance. 12. AC Test Conditions use V OH = 1.6V and V O = 1.4V. 13. At any given temperature and voltage condition for any given device, t HZCE is less than t ZCE and t HZOE is less than t ZOE. 14. t ZCE, t ZWE, t HZOE, t ZOE, t HZCE and t HZWE are tested with C = 5pF as in part (b) of AC Test oads. Transition is measured ±500 mv from steady state voltage. 15. The internal write time of the memory is defined by the overlap of CS OW and R/W OW. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: Rev. *D Page 5 of 19

6 Switching Characteristics Over the Operating Range [6, 11] (continued) Parameter BUSY/INTERRUPT TIMING t BA BUSY OW from Address Match ns t BHA BUSY HIGH from Address Mismatch [16] ns t BC BUSY OW from CE OW ns t BHC BUSY HIGH from CE HIGH [16] ns t PS Port Set Up for Priority ns t WB [17] R/W OW after BUSY OW ns t WH R/W HIGH after BUSY HIGH ns t BDD BUSY HIGH to Valid Data ns t DDD Write Data Valid to Read Data Valid Note 18 Note 18 Note 18 ns t WDD Write Pulse to Data Delay Note 18 Note 18 Note 18 ns INTERRUPT TIMING t WINS R/W to INTERRUPT Set Time ns t EINS CE to INTERRUPT Set Time ns t INS Address to INTERRUPT Set Time ns t OINR OE to INTERRUPT Reset Time [16] ns t EINR CE to INTERRUPT Reset Time [16] ns t INR Address to INTERRUPT Reset Time [16] ns Shaded areas contain preliminary information. Description 7C [3] 7C C [3] 7C C C C C C C Min. Max. Min. Max. Min. Max. Note: 16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 17. only. 18. A write operation on Port A, where Port A has priority, leaves the data on Port B s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B s address is toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. Unit Switching Characteristics Over the Operating Range [6,11] 7C C C C C C C C C C C C Parameter Description Min. Max. Min. Max. Min. Max. Unit READ CYCE t RC Read Cycle Time ns t AA Address to Data Valid [12] ns t OHA Data Hold from Address Change ns t ACE CE OW to Data Valid [12] ns t DOE OE OW to Data Valid [12] ns t ZOE OE OW to ow Z [9, 13, 14] ns t HZOE OE HIGH to High Z [9, 13, 14] ns t ZCE CE OW to ow Z [9, 13, 14] ns Document #: Rev. *D Page 6 of 19

7 Switching Characteristics Over the Operating Range [6,11] (continued) Parameter t HZCE CE HIGH to High Z [9, 13, 14] ns t PU CE OW to Power-Up [9] ns t PD CE HIGH to Power-Down [9] ns WRITE CYCE [15] t WC Write Cycle Time ns t SCE CE OW to Write End ns t AW Address Set-Up to Write End ns t HA Address Hold from Write End ns t SA Address Set-Up to Write Start ns t PWE R/W Pulse Width ns t SD Data Set-Up to Write End ns t HD Data Hold from Write End ns t HZWE R/W OW to High Z [14] ns t ZWE R/W HIGH to ow Z [14] ns BUSY/INTERRUPT TIMING t BA BUSY OW from Address Match ns t BHA BUSY HIGH from Address Mismatch [16] ns t BC BUSY OW from CE OW ns t BHC BUSY HIGH from CE HIGH [16] ns t PS Port Set Up for Priority ns t WB [17] R/W OW after BUSY OW ns t WH R/W HIGH after BUSY HIGH ns t BDD BUSY HIGH to Valid Data ns t DDD Write Data Valid to Read Data Valid Note 18 t WDD Write Pulse to Data Delay Note 18 INTERRUPT TIMING Description 7C C C C C C C C t WINS R/W to INTERRUPT Set Time ns t EINS CE to INTERRUPT Set Time ns t INS Address to INTERRUPT Set Time ns t OINR OE to INTERRUPT Reset Time [16] ns t EINR CE to INTERRUPT Reset Time [16] ns t INR Address to INTERRUPT Reset Time [16] ns Note 18 Note 18 7C C C C Min. Max. Min. Max. Min. Max. Note 18 Note 18 Unit ns ns Document #: Rev. *D Page 7 of 19

8 Switching Waveforms Read Cycle No. 1 [19, 20] Either Port Address Access t RC ADDRESS DATA OUT t OHA PREVIOUS DATAVAID t AA DATA VAID [19, 21] Read Cycle No. 2 CE OE t ACE Either Port CE/OE Access t HZCE DATA OUT t ZCE t ZOE t DOE t HZOE DATA VAID I CC t PU t PD I SB Read Cycle No. 3 [20] Read with BUSY, Master: CY7C130 and CY7C131 t RC ADDRESS R R/W R ADDRESS MATCH t PWE t HD D INR VAID ADDRESS ADDRESS MATCH t PS BUSY t BHA t BA t BDD DOUT VAID t WDD t DDD Notes: 19. R/W is HIGH for read cycle. 20. Device is continuously selected, CE = V I and OE = V I. 21. Address valid prior to or coincident with CE transition OW. Document #: Rev. *D Page 8 of 19

9 Switching Waveforms (continued) Write Cycle No. 1 (OE Three-States Data s Either Port [15, 22] Either Port t WC ADDRESS CE t SCE R/W t SA t AW t PWE t HA t SD t HD DATA IN DATA VAID OE D OUT t HZOE HIGH IMPEDANCE [16, 23] Write Cycle No. 2 (R/W Three-States Data s Either Port) ADDRESS t WC t SCE t HA CE R/W t SA t AW t PWE t SD t HD DATA IN DATA VAID DATA OUT t HZWE t ZWE HIGH IMPEDANCE Notes: 22. If OE is OW during a R/W controlled write cycle, the write pulse width must be the larger of t PWE or t HZWE + t SD to allow the data pins to enter high impedance and for data to be placed on the bus for the required t SD. 23. If the CE OW transition occurs simultaneously with or after the R/W OW transition, the outputs remain in the high-impedance state. Document #: Rev. *D Page 9 of 19

10 Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: ADDRESS,R ADDRESS MATCH CE CE R t PS t BC t BHC BUSY R CE R Valid First: ADDRESS,R ADDRESS MATCH CE R CE t PS t BC t BHC BUSY Busy Timing Diagram No. 2 (Address Arbitration) eft Address Valid First: ADDRESS t PS t RC or t WC ADDRESS MATCH ADDRESS MISMATCH ADDRESS R BUSY R t BA t BHA Right Address Valid First: ADDRESS R t PS t RC or t WC ADDRESS MATCH ADDRESS MISMATCH ADDRESS BUSY t BA t BHA Document #: Rev. *D Page 10 of 19

11 Switching Waveforms (continued) Busy Timing Diagram No. 3 Write with BUSY (Slave:) CE R/W t PWE BUSY t WB t WH Document #: Rev. *D Page 11 of 19

12 Switching Waveforms (continued) Interrupt Timing Diagrams eft Side Sets INT R ADDR t WC WRITE 3FF t INS t HA CE t EINS R/W t SA t WINS INT R Right Side Clears INT R t RC ADDR R CE R t HA t INT READ 3FF t EINR R/W R OE R t OINR INT R Right Side Sets INT t WC ADDR R WRITE 3FE t INS t HA CE R t EINS R/W R INT t SA twins eft Side Clears INT ADDR R t RC READ 3FE CE t HA t INR t EINR R/W OE t OINR INT Document #: Rev. *D Page 12 of 19

13 Typical DC and AC Characteristics NORMAIZED I CC, I SB NORMAIZED SUPPY CURRENT vs. SUPPY VOTAGE I CC SUPPY VOTAGE (V) NORMAIZED I CC, I SB I SB3 0.2 NORMAIZED SUPPY CURRENT vs. AMBIENT TEMPERATURE I CC V CC = 5.0V V IN = 5.0V I SB3 AMBIENT TEMPERATURE ( C) OUTPUT SOURCE CURRENT (ma) OUTPUT SOURCE CURRENT vs. OUTPUT VOTAGE V CC = 5.0V T A = 25 C OUTPUT VOTAGE (V) NORMAIZED t AA NORMAIZED ACCESS TIME vs. SUPPY VOTAGE T A = 25 C SUPPY VOTAGE (V) NORMAIZED t AA NORMAIZED ACCESS TIME vs. AMBIENT TEMPERATURE V CC = 5.0V AMBIENT TEMPERATURE ( C) OUTPUT SINK CURRENT (ma) OUTPUT SINK CURRENT vs. OUTPUT VOTAGE V CC = 5.0V T A = 25 C OUTPUT VOTAGE (V) NORMAIZED t PC TYPICA POWER-ON CURRENT TYPICA ACCESS TIME CHANGE vs. SUPPY VOTAGE vs. OUTPUT OADING V CC = 4.5V T A = 25 C DETA t AA (ns) SUPPY VOTAGE (V) CAPACITANCE (pf) NORMAIZED I CC NORMAIZED I CC vs. CYCE TIME 1.25 V CC = 4.5V T A = 25 C V IN = 0.5V CYCE FREQUENCY (MHz) Document #: Rev. *D Page 13 of 19

14 Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 30 CY7C130-30PC P25 48-ead (600-Mil) Molded DIP Commercial CY7C130-30PI P25 48-ead (600-Mil) Molded DIP Industrial 35 CY7C130-35PC P25 48-ead (600-Mil) Molded DIP Commercial CY7C130-35PI P25 48-ead (600-Mil) Molded DIP Industrial CY7C130-35DMB D26 48-ead (600-Mil) Sidebraze DIP Military 45 CY7C130-45PC P25 48-ead (600-Mil) Molded DIP Commercial CY7C130-45PI P25 48-ead (600-Mil) Molded DIP Industrial CY7C130-45DMB D26 48-ead (600-Mil) Sidebraze DIP Military 55 CY7C130-55PC P25 48-ead (600-Mil) Molded DIP Commercial CY7C130-55PI P25 48-ead (600-Mil) Molded DIP Industrial CY7C130-55DMB D26 48-ead (600-Mil) Sidebraze DIP Military 15 CY7C131-15JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C131-15JXC J69 52-ead Pb-Free Plastic eaded Chip Carrier CY7C131-15NC N52 52-Pin Plastic Quad Flatpack CY7C131-15JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C131-15JXI J69 52-ead Pb-Free Plastic eaded Chip Carrier 25 CY7C131-25JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C131-25JXC J69 52-ead Pb-Free Plastic eaded Chip Carrier CY7C131-25NC N52 52-Pin Plastic Quad Flatpack CY7C131-25NXC N52 52-Pin Pb-Free Plastic Quad Flatpack CY7C131-25JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C131-25NI N52 52-Pin Plastic Quad Flatpack 30 CY7C131-30JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C131-30NC N52 52-Pin Plastic Quad Flatpack CY7C131-30JI J69 52-ead Plastic eaded Chip Carrier Industrial 35 CY7C131-35JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C131-35NC N52 52-Pin Plastic Quad Flatpack CY7C131-35JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C131-35NI N52 52-Pin Plastic Quad Flatpack 45 CY7C131-45JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C131-45NC N52 52-Pin Plastic Quad Flatpack CY7C131-45JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C131-45NI N52 52-Pin Plastic Quad Flatpack 55 CY7C131-55JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C131-55JXC J69 52-ead Pb-Free Plastic eaded Chip Carrier CY7C131-55NC N52 52-Pin Plastic Quad Flatpack CY7C131-55NXC N52 52-Pin Pb-Free Plastic Quad Flatpack CY7C131-55JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C131-55JXI J69 52-ead Pb-Free Plastic eaded Chip Carrier CY7C131-55NI N52 52-Pin Plastic Quad Flatpack Document #: Rev. *D Page 14 of 19

15 Ordering Information (continued) Speed (ns) Ordering Code Package Name Package Type 30 CY7C140-30PC P25 48-ead (600-Mil) Molded DIP Commercial CY7C140-30PI P25 48-ead (600-Mil) Molded DIP Industrial 35 CY7C140-35PC P25 48-ead (600-Mil) Molded DIP Commercial CY7C140-35PI P25 48-ead (600-Mil) Molded DIP Industrial CY7C140-35DMB D26 48-ead (600-Mil) Sidebraze DIP Military 45 CY7C140-45PC P25 48-ead (600-Mil) Molded DIP Commercial CY7C140-45PI P25 48-ead (600-Mil) Molded DIP Industrial CY7C140-45DMB D26 48-ead (600-Mil) Sidebraze DIP Military 55 CY7C140-55PC P25 48-ead (600-Mil) Molded DIP Commercial CY7C140-55PI P25 48-ead (600-Mil) Molded DIP Industrial CY7C140-55DMB D26 48-ead (600-Mil) Sidebraze DIP Military 15 CY7C141-15JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C141-15NC N52 52-Pin Plastic Quad Flatpack 25 CY7C141-25JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C141-25JXC J69 52-ead Pb-Free Plastic eaded Chip Carrier CY7C141-25NC N52 52-Pin Plastic Quad Flatpack CY7C141-25JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C141-25NI N52 52-Pin Plastic Quad Flatpack 30 CY7C141-30JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C141-30NC N52 52-Pin Plastic Quad Flatpack CY7C141-30JI J69 52-ead Plastic eaded Chip Carrier Industrial 35 CY7C141-35JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C141-35NC N52 52-Pin Plastic Quad Flatpack CY7C141-35JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C141-35NI N52 52-Pin Plastic Quad Flatpack 45 CY7C141-45JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C141-45NC N52 52-Pin Plastic Quad Flatpack CY7C141-45JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C141-45NI N52 52-Pin Plastic Quad Flatpack 55 CY7C141-55JC J69 52-ead Plastic eaded Chip Carrier Commercial CY7C141-55NC N52 52-Pin Plastic Quad Flatpack CY7C141-55JI J69 52-ead Plastic eaded Chip Carrier Industrial CY7C141-55NI N52 52-Pin Plastic Quad Flatpack Operating Range Document #: Rev. *D Page 15 of 19

16 MIITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups V OH 1, 2, 3 V O 1, 2, 3 V IH 1, 2, 3 V I Max. 1, 2, 3 I IX 1, 2, 3 I OZ 1, 2, 3 I CC 1, 2, 3 I SB1 1, 2, 3 I SB2 1, 2, 3 I SB3 1, 2, 3 I SB4 1, 2, 3 Switching Characteristics Parameter Subgroups READ CYCE t RC 7, 8, 9, 10, 11 t AA 7, 8, 9, 10, 11 t ACE 7, 8, 9, 10, 11 t DOE 7, 8, 9, 10, 11 WRITE CYCE t WC 7, 8, 9, 10, 11 t SCE 7, 8, 9, 10, 11 t AW 7, 8, 9, 10, 11 t HA 7, 8, 9, 10, 11 t SA 7, 8, 9, 10, 11 t PWE 7, 8, 9, 10, 11 t SD 7, 8, 9, 10, 11 t HD 7, 8, 9, 10, 11 BUSY/INTERRUPT TIMING t BA 7, 8, 9, 10, 11 t BHA 7, 8, 9, 10, 11 t BC 7, 8, 9, 10, 11 t BHC 7, 8, 9, 10, 11 t PS 7, 8, 9, 10, 11 t WINS 7, 8, 9, 10, 11 t EINS 7, 8, 9, 10, 11 t INS 7, 8, 9, 10, 11 t OINR 7, 8, 9, 10, 11 t EINR 7, 8, 9, 10, 11 t INR 7, 8, 9, 10, 11 BUSY TIMING t [24] WB 7, 8, 9, 10, 11 t WH 7, 8, 9, 10, 11 t BDD 7, 8, 9, 10, 11 Note: 24. only. Document #: Rev. *D Page 16 of 19

17 Package Diagrams 48-ead (600-Mil) Sidebraze DIP D26 MI-STD-1835 D-14 Config. C ** 52-ead Plastic eaded Chip Carrier J69 52-ead Pb-Free Plastic eaded Chip Carrier J69 DIMENSIONS IN INCHES MIN. MAX. PIN #1 ID SEATING PANE MIN *A Document #: Rev. *D Page 17 of 19

Package Diagrams (continued) 48-ead (600-Mil) Molded DIP P25 51-85020-*A 52-ead Plastic Quad Flatpack N52 52-ead Pb-Free Plastic Quad Flatpack N52 51-85042-** All products and company names mentioned

18 Package Diagrams (continued) 48-ead (600-Mil) Molded DIP P *A 52-ead Plastic Quad Flatpack N52 52-ead Pb-Free Plastic Quad Flatpack N ** All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: Rev. *D Page 18 of 19 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

19 Document History Page Document Title: CY7C130/CY7C131/ 1K x 8 Dual-Port Static RAM Document Number: REV. ECN NO. Issue Date Orig. of Change Description of Change ** /29/01 SZV Change from Spec number: to *A /26/02 RBI Power up requirements added to Maximum Ratings Information *B See ECN YDT Removed cross information from features section *C See ECN RUY Added pin definitions table, 52-pin PQFP package diagram and Pb-free information *D See ECN YIM Added CY7C131-15JI to ordering information Added Pb-Free parts to ordering information: CY7C131-15JXI Document #: Rev. *D Page 19 of 19

2Kx8 Dual-Port Static RAM

2Kx8 Dual-Port Static RAM 1CY 7C13 2/ CY7C1 36 fax id: 5201 CY7C132/CY7C136 Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location 2K x 8 organization 0.65-micron CMOS for optimum speed/power