PRELIMINARY C106A 1. 7C106A 12 7C106A 15 7C106A 20 7C106A 25 7C106A 35 Maximum Access Time (ns) Maximum Operating
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1 1CY 7C10 6A Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 910 mw Low standby power 275 mw 2.0V data retention (optional) 100 µw Automatic power-down when deselected TTL-compatible inputs and outputs Functional Description The is a high-performance CMOS static RAM organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable (), an active LOW PRELIMINARY 256K x 4 Static RAM output enable (OE), and three-state drivers. The device has an automatic power-down feature that reduces power consumption by more than 65% when deselected. Writing to the device is accomplished by taking chip enable () and write enable (WE) inputs LOW. Data on the four I/O pins (I/O 0 through I/O 3 ) is then written into the location specified on the address pins (A 0 through A 17 ). Reading from the device is accomplished by taking chip enable () and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. The four input/output pins (I/O 0 through I/O 3 ) are placed in a high-impedance state when the device is deselected ( HIGH), the outputs are disabled (OE HIGH), or during a write operation ( and WE LOW). The is available in standard 400-mil-wide DIPs and SOJs. Logic Block Diagram Pin Configuration DIP/SOJ Top View A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 INPUT BUFFER 512 x 512 x 4 ARRAY I/O 3 I/O 2 I/O 1 I/O 0 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 OE GND V CC A 17 A 16 A 15 A 14 A 13 A 12 A 11 NC I/O 3 I/O 2 I/O 1 I/O 0 WE C106A 2 COLUMN DECODER POWER DOWN Selection Guide WE OE C106A 1 7C106A 12 7C106A 15 7C106A 20 7C106A 25 7C106A 35 Maximum Access Time (ns) Maximum Operating Commercial Current (ma) Military Maximum Standby Commercial Current (ma) Military Shaded area contains advanced information. Cypress Semiconductor Corporation 3901 North First Street San Jose CA December 1992 Revised February 1996
2 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage on V CC Relative to GND [1] V to +7.0V DC Voltage Applied to Outputs in High Z State [1] V to V CC +0.5V DC Input Voltage [1] V to V CC +0.5V Current into Outputs (LOW) ma Static Discharge Voltage... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current... >200 ma Operating Range Range Ambient Temperature [2] V CC Commercial 0 C to +70 C 5V ± 10% Military 55 C to +125 C 5V ± 10% Electrical Characteristics Over the Operating Range [3] 7C106A 12 7C106A 15 7C106A 20 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit V OH Output HIGH Voltage V CC = Min., I OH = 4.0 ma V V OL Output LOW Voltage V CC = Min., I OL = 8.0 ma V V IH Input HIGH Voltage 2.2 V CC V CC V CC +0.3 V IL Input LOW Voltage [1] V I IX Input Load Current GND < V I < V CC µa I OZ Output Leakage Current GND < V I < V CC, µa Output Disabled I OS Output Short Circuit Current [4] V CC = Max., V OUT = GND ma I CC V CC Operating V CC = Max., Com l ma Supply Current I OUT = 0 ma, f = f MAX = 1/t RC Mil I SB1 Automatic Max. V CC, > V IH, Com l ma Power-Down Current TTL Inputs V IN > V IH or V IN < V IL, f = f MAX Mil I SB2 Automatic Max. V CC, Com l ma Power-Down Current CMOS Inputs > V CC 0.3V, V IN > V CC 0.3V L or V IN < 0.3V, f=0 Mil L 2 2 Shaded area contains advanced information. 1. V IL (min.) = 2.0V for pulse durations of less than 20 ns. 2. T A is the instant on case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. V 2
3 Electrical Characteristics Over the Operating Range [3] (continued) 7C106A 25 7C106A 35 Parameter Description Test Conditions Min. Max. Min. Max. Unit V OH Output HIGH Voltage V CC = Min., I OH = 4.0 ma V V OL Output LOW Voltage V CC = Min., I OL = 8.0 ma V V IH Input HIGH Voltage 2.2 V CC V CC V V IL Input LOW Voltage [1] V I IX Input Load Current GND < V I < V CC µa I OZ Output Leakage Current GND < V I < V CC, µa Output Disabled I OS Output Short Circuit Current [4] V CC = Max., V OUT = GND ma I CC V CC Operating V CC = Max., Com l ma Supply Current I OUT = 0 ma, f = f MAX = 1/t RC Mil I SB1 Automatic Max. V CC, > V IH, Com l ma Power-Down Current TTL Inputs V IN > V IH or V IN < V IL, f = f MAX Mil I SB2 Automatic Max. V CC, Com l ma Power-Down Current CMOS Inputs > V CC 0.3V, V IN > V CC 0.3V L 2 2 or V IN < 0.3V, f=0 Mil L 2 2 Capacitance [5] Parameter Description Test Conditions Max. Unit C IN : Addresses Input Capacitance T A = 25 C, f = 1 MHz, 7 pf C IN : Controls V CC = 5.0V 10 pf C OUT Output Capacitance 10 pf 5. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE (a) R1 480Ω 5V OUTPUT R2 5 pf 255Ω INCLUDING JIG AND SCOPE (b) R1 480Ω R2 255Ω C106A 3 ALL INPUT PULSES 3.0V GND 90% 10% 90% 10% < 3 ns < 3 ns C106A 4 Equivalent to: OUTPUT THÉ VENIN EQUIVALENT 167Ω 1.73V 3
4 Switching Characteristics Over the Operating Range [3,6] 7C106A 12 7C106A 15 7C106A 20 7C106A 25 7C106A 35 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE t RC Read Cycle Time ns t AA Address to Data Valid ns t OHA Data Hold from Address Change ns t A LOW to Data Valid ns t DOE OE LOW to Data Valid ns t LZOE OE LOW to Low Z ns t HZOE OE HIGH to High Z [7,8] ns t LZ LOW to Low Z [8] ns t HZ HIGH to High Z [7,8] ns t PU LOW to Power-Up ns t PD HIGH to Power-Down ns WRITE CYCLE [9,10] t WC Write Cycle Time ns t S LOW to Write End ns t AW Address Set-Up to Write End ns t HA Address Hold from Write End ns t SA Address Set-Up to Write Start ns t PWE WE Pulse Width ns t SD Data Set-Up to Write End ns t HD Data Hold from Write End ns t LZWE WE HIGH to Low Z [8] ns t HZWE WE LOW to High Z [7,8] ns Shaded area contains advanced information. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30 pf load capacitance. 7. t HZOE, t HZ, and t HZWE are specified with a load capacitance of 5 pf as in part (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 8. At any given temperature and voltage condition, t HZ is less than t LZ, t HZOE is less than t LZOE, and t HZWE is less than t LZWE for any given device. 9. The internal write time of the memory is defined by the overlap of and WE LOW. and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD. 4
5 Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Military Parameter Description Conditions [11] Min. Max. Min. Max. Unit V DR V CC for Data Retention V I CCDR Data Retention Current V CC = V DR = 2.0V, µa > V CC 0.3V, t [5] CDR Chip Deselect to Data Retention Time 0 0 ns V IN > V CC 0.3V or t [5] R Operation Recovery Time V IN < 0.3V t RC t RC ns 11. No input may exceed V CC +0.5V. Data Retention Waveform DATARETENTIONMODE V CC 4.5V V DR > 2V 4.5V t CDR t R C106A 5 Switching Waveforms Read Cycle No.1 [12, 13] 1 t RC ADDRESS t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID C106A 6 [13, 14] Read Cycle No. 2 (OE Controlled) ADDRESS t RC t A OE t HZOE thz t DOE DATA OUT t LZOE HIGH IMPEDAN DATA VALID HIGH IMPEDAN V CC SUPPLY CURRENT t PU t LZ 50% t PD 50% ICC ISB C106A Device is continuously selected, OE and = V IL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with transition LOW. 5
6 Switching Waveforms (continued) Write Cycle No. 1 ( Controlled) [15, 16] t WC ADDRESS t SA t S t AW t HA WE t PWE t SD t HD DATA I/O DATA VALID C106A 8 Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [15, 16] t WC ADDRESS t S t AW t HA t SA t PWE WE OE t SD t HD DATA I/O DATA VALID t HZOE C106A If goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. Data I/O is high impedance if OE = V IH. 6
7 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [10, 16] t WC ADDRESS t S t AW t HA t SA t PWE WE t SD t HD DATA I/O DATA VALID t HZWE t LZWE C106A 10 Truth Table OE WE Input/Output Mode Power H X X High Z Power-Down Standby (I SB ) L L H Data Out Read Active (I CC ) L X L Data In Write Active (I CC ) L H H High Z Selected, Outputs Disabled Active (I CC ) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 12 12PC P41 28-Lead (400-Mil) Molded DIP Commercial 12VC V28 28-Lead (400-Mil) Molded SOJ 15 15PC P41 28-Lead (400-Mil) Molded DIP Commercial 15VC V28 28-Lead (400-Mil) Molded SOJ 15DMB D42 28-Lead (400-Mil) CerDIP Military 20 20PC P41 28-Lead (400-Mil) Molded DIP Commercial 20VC V28 28-Lead (400-Mil) Molded SOJ 20DMB D42 28-Lead (400-Mil) CerDIP Military 25 25PC P41 28-Lead (400-Mil) Molded DIP Commercial 25VC V28 28-Lead (400-Mil) Molded SOJ 25DMB D42 28-Lead (400-Mil) CerDIP Military 35 35PC P41 28-Lead (400-Mil) Molded DIP Commercial 35VC V28 28-Lead (400-Mil) Molded SOJ 35DMB D42 28-Lead (400-Mil) CerDIP Military Shaded area contains advanced information. Contact factory for L version availability. 7
8 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups V OH 1, 2, 3 V OL 1, 2, 3 V IH 1, 2, 3 V IL Max. 1, 2, 3 I IX 1, 2, 3 I OZ 1, 2, 3 I CC 1, 2, 3 I SB1 1, 2, 3 I SB2 1, 2, 3 Switching Characteristics Parameter Subgroups READ CYCLE t RC 7, 8, 9, 10, 11 t AA 7, 8, 9, 10, 11 t OHA 7, 8, 9, 10, 11 t A 7, 8, 9, 10, 11 t DOE 7, 8, 9, 10, 11 WRITE CYCLE t WC 7, 8, 9, 10, 11 t S 7, 8, 9, 10, 11 t AW 7, 8, 9, 10, 11 t HA 7, 8, 9, 10, 11 t SA 7, 8, 9, 10, 11 t PWE 7, 8, 9, 10, 11 t SD 7, 8, 9, 10, 11 t HD 7, 8, 9, 10, 11 Document #: B 8
9 Package Diagrams 28-Lead (400-Mil) CerDIP D42 28-Lead (400-Mil) Molded DIP P41 9
10 Package Diagrams (continued) 28-Lead (400-Mil) Molded SOJ V28 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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