64K x 1 Static RAM CY7C187. Features. Functional Description. Logic Block Diagram. Pin Configurations. Selection Guide DIP. SOJ Top View.

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64K x 1 Static RAM Features High speed 15 ns CMOS for optimum speed/power Low active power 495 mw Low standby power 110 mw TTL compatible inputs and outputs Automatic power-down when deselected

1 64K x 1 Static RAM Features High speed 15 ns CMOS for optimum speed/power Low active power 495 mw Low standby power 110 mw TTL compatible inputs and outputs Automatic power-down when deselected Available in Pb-free and non Pb-free 22-pin (300-Mil) Molded DIP and 24-pin (300-Mil) Molded SOJ Functional Description The CY7C187 is a high-performance CMOS static RAM organized as 65,536 words x 1 bit. Easy memory expansion is provided by an active LOW Chip Enable () and tri-state drivers. The CY7C187 has an automatic power-down feature, reducing the power consumption by 56% when deselected. Writing to the device is accomplished when the Chip Enable () and Write Enable (WE) inputs are both LOW. Data on the input pin (D IN ) is written into the memory location specified on the address pins (A 0 through A 15 ). Reading the device is accomplished by taking the Chip Enable () LOW, while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pin will appear on the data output (D OUT ) pin. The output pin stays in high-impedance state when Chip Enable () is HIGH or Write Enable (WE) is LOW. The CY7C187 utilizes a die coat to insure alpha immunity. Logic Block Diagram Pin Configurations DI SOJ Top View DIP Top View A 12 A 13 A 14 A 15 A 0 A 1 A 2 A 3 ROW DECODER INPUT BUFFER 16K x 1 ARRAY COLUMN DECODER SENSE AMPS POWER DOWN DO WE A 0 A 1 A 2 A 3 A 4 A 5 NC A 6 A 7 D OUT WE GND C187 3 V CC A 0 A 15 A 1 A 14 A 2 A 13 A 3 A 12 A 4 NC A 5 A 11 A 6 A 10 A 7 A 9 D OUT A 8 WE D IN GND C187 2 V CC A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 D IN A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 C187 1 Selection Guide Maximum Access Time (ns) Maximum Operating Current (ma) Maximum CMOS Standby Current (ma) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: Rev. *A Revised July 24, 2006

2 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage to Ground Potential (Pin 22 to Pin 11) V to +7.0V DC Voltage Applied to Outputs in High Z State [1] V to +7.0V DC Input Voltage [1] V to +7.0V Output Current into Outputs (LOW) ma Static Discharge Voltage... >2001V (per MIL STD 883, Method 3015) Latch-Up Current... >200 ma Operating Range Range Ambient Temperature V CC Commercial 0 C to +70 C 5V ± 10% Electrical Characteristics Over the Operating Range and -35 Parameter Description Test Conditions Min. Max. Min. Max. Unit V OH Output HIGH Voltage V CC = Min., I OH = 4.0mA V V OL Output LOW Voltage V CC = Min., I OL =12.0 ma V V IH Input HIGH Voltage 2.2 V CC 2.2 V CC V V IL Input LOW Voltage [1] V I IX Input Leakage Current GND < V I < V CC µa I OZ Output Leakage GND < V O < V CC, µa Current Output Disabled I CC I SB1 I SB2 Capacitance [4] V CC Operating Supply Current V CC = Max., I OUT = 0 ma ma Automatic Power- Max. V CC, V IH ma Down Current [3] Automatic Power-Down Current Max. V CC, V CC 0.3V, V IN V CC 0.3V or V IN 0.3V ma Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 10 pf C OUT Output Capacitance V CC = 5.0V 10 pf AC Test Loads and Waveforms 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE R1 329 Ω (a) R2 202 Ω 5V OUTPUT 5 pf INCLUDING JIG AND SCOPE R1 329 Ω (b) R2 202 Ω C V 10% GND 5ns ALL INPUT PULSES 90% 90% 10% 5 ns C187 5 Equivalent to: THÉ VENIN EQUIVALENT 125Ω OUTPUT 1.90V Notes: 1. V IL (min.) = 3.0V for pulse durations less than 30 ns. 2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. A pull-up resistor to V CC on the input is required to keep the device deselected during V CC power-up, otherwise I SB will exceed values given. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: Rev. *A Page 2 of 9

3 Switching Characteristics Over the Operating Range [5] Parameter Description Min. Max. Min. Max. Min. Max. Unit READ CYCLE t RC Read Cycle Time ns t AA Address to Data Valid ns t OHA Output Hold from Address Change ns t A LOW to Data Valid ns t LZ LOW to Low Z [6] ns t HZ HIGH to High Z [6, 7] ns t PU LOW to Power Up ns t PD HIGH to Power Down ns WRITE CYCLE [8] t WC Write Cycle Time ns t S LOW to Write End ns t AW Address Set-Up to Write End ns t HA Address Hold from Write End ns t SA Address Set-Up to Write Start ns t PWE WE Pulse Width ns t SD Data Set-Up to Write End ns t HD Data Hold from Write End ns t LZWE WE HIGH to Low Z ns t HZWE WE LOW to High Z [7] ns Switching Waveforms Read Cycle No. 1 [9, 10] t RC ADDRESS t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID C187 6 Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance. 6. At any given temperature and voltage condition, t HZ is less than t LZ for any given device. 7. t HZ and t HZWE are specified with C L = 5 pf as in part (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. WE is HIGH for read cycle. 10. Device is continuously selected, = V IL. Document #: Rev. *A Page 3 of 9

4 Switching Waveforms Read Cycle No. 2 [9, 11] t RC t A DATA OUT t LZ HIGH IMPEDAN DATA VALID t HZ HIGH IMPEDAN V CC SUPPLY CURRENT t PU 50% t PD 50% ICC ISB C187 7 Write Cycle No. 1(WE Controlled) [11] t WC ADDRESS t S t AW t SA t PWE t HA WE t SD t HD DATA IN DATA VALID t HZWE t LZWE DATA OUT DATA UNDEFINED HIGH IMPEDAN Note: 11. Address valid prior to or coincident with transition LOW. C187 8 Document #: Rev. *A Page 4 of 9

5 Switching Waveforms Write Cycle No. 2( Controlled) [11,13] t WC ADDRESS t SA t S t AW t PWE t HA WE t SD t HD DATA IN DATA VALID DATA OUT Typical DC and AC Characteristics HIGH IMPEDAN C187 9 NORMALIZED I CC, I SB NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE I CC I SB SUPPLY VOLTAGE(V) NORMALIZED I CC, I SB NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE I SB V IN =5.0V I CC AMBIENT TEMPERATURE ( C) OUTPUT SOUR CURRENT (ma) OUTPUT SOUR CURRENT vs. OUTPUT VOLTAGE OUTPUT VOLTAGE (V) NORMALIZED t AA NORMALIZED ACSS TIME vs. SUPPLY VOLTAGE SUPPLY VOLTAGE (V) NORMALIZED t AA NORMALIZED ACSS TIME vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE ( C) OUTPUT SINK CURRENT (ma) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE OUTPUT VOLTAGE (V) Note: 12. If goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: Rev. *A Page 5 of 9

6 Typical DC and AC Characteristics (Continued) NORMALIZED I PO TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE NORMALIZED t AA (ns) TYPICAL ACSS TIME CHANGE vs. OUTPUT LOADING V CC =4.5V NORMALIZED I CC NORMALIZED I CC vs.cycle TIME 1.25 V CC =0.5V SUPPLY VOLTAGE(V) CAPACITAN (pf) CYCLE FREQUENCY (MHz) Address Designators Address Name Truth Table Address Function Pin Number A0 X3 1 A1 X4 2 A2 X5 3 A3 X6 4 A4 X7 5 A5 Y7 6 A6 Y6 7 A7 Y2 8 A8 Y3 14 A9 Y1 15 A10 Y0 16 A11 Y4 17 A12 Y5 18 A13 X0 19 A14 X1 20 A15 X2 21 WE Input/Output Mode H X High Z Deselect/Power-Down L H Data Out Read L L Data In Write Document #: Rev. *A Page 6 of 9

7 Ordering Information CY7C187 Speed (ns) Ordering Code Package Diagram Package Type Operating Range 15 CY7C187-15PXC pin (300-Mil) Molded DIP (Pb-free) Commercial 25 CY7C187-25PC pin (300-Mil) Molded DIP Commercial CY7C187-25VC pin (300-Mil) Molded SOJ CY7C187-25VXC 24-pin (300-Mil) Molded SOJ (Pb-free) 35 CY7C187-35VXC pin (300-Mil) Molded SOJ (Pb-free) Commercial Package Diagrams pin (300-Mil) PDIP ( ) DIMENSIONS IN INCHES MIN. MAX SEATING PLANE MIN *A Document #: Rev. *A Page 7 of 9

8 Package Diagrams (Continued) 24-pin (300-mil) SOJ ( ) PIN 1 ID 12 1 DIMENSIONS IN INCHES[MM] MIN. MAX [7.39] 0.300[7.62] 0.330[8.38] 0.350[8.89] REFEREN JEDEC MO-088 PACKAGE WEIGHT 0.75gms PART # V24.3 STANDARD PKG. VZ24.3 LEAD FREE PKG [15.16] 0.613[15.57] SEATING PLANE 0.120[3.05] 0.140[3.55] 0.007[0.17] 0.013[0.33] 0.050[1.27] TYP [0.33] 0.019[0.48] 0.025[0.63] MIN [0.10] 0.262[6.65] 0.272[6.91] *B All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: Rev. *A Page 8 of 9 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Document History Page Document Title: CY7C187 64K x 1 Static RAM Document Number: 38-05044 REV. ECN NO. Issue Date Orig.

9 Document History Page Document Title: CY7C187 64K x 1 Static RAM Document Number: REV. ECN NO. Issue Date Orig. of Change Description of Change ** /10/01 SZV Change from Spec number: to *A See ECN NXR Removed 20 ns speed bin Changed Low standby power from 220mW to 110mW Changed the description of I IX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table Document #: Rev. *A Page 9 of 9

I/O 1 I/O 2 I/O 3 A 10 6

I/O 1 I/O 2 I/O 3 A 10 6 Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 495 mw (Max, L version) Low standby power 0.275 mw (Max, L version) 2V data retention ( L version only) Easy memory expansion