14-Bit Registered Buffer PC2700-/PC3200-Compliant

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14-Bit Registered Buffer PC2700-/PC3200-Compliant Features Differential Clock Inputs up to 280 MHz Supports LVTTL switching levels on the RESET pin Output drivers have controlled edge rates, so no

1 14-Bit Registered Buffer PC2700-/PC3200-Compliant Features Differential Clock Inputs up to 280 MHz Supports LVTTL switching levels on the RESET pin Output drivers have controlled edge rates, so no external resistors are required Two KV ESD protection Latch-up performance exceeds 100 ma: JESD78, Class II Conforms to JEDEC STD (JESD82-3) for buffered DDR DIMMs 48-pin TSSOP Description This 14-bit registered buffer is designed specifically for 2.3V to 2.7V V DD operation and is characterized for operation from 0 C to + 85 C. All inputs are compatible with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II-compatible. The SSTV16857 operates from a differential clock ( and ). Data is measured at the crossing of going HIGH, and going LOW. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and REF voltage inputs are allowed. In addition, when RESET is LOW, all registers are reset and all outputs force to the LOW state. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR registered DIMM application, RESET is specified to be completely asynchronous with respect to and. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. Block Diagram Pin Configuration RESET VREF D1 1D C1 R To 13 Other Channels Q1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q CY2SSTV D1 D2 VDD D3 D4 D5 D6 D7 VDD VREF RESET D8 D9 D10 D11 D12 VDD D13 D14 Cypress Semiconductor Corporation 3901 North First Street San Jose, CA Document #: Rev. *D Revised January 12, 2005

2 Pin Description Pin Name I/O Type Description 34 RESET I 3,8,13,17,22,27,36,46 Ground Ground. 28, 37, 45 VDD Power 2.5V nominal supply voltage. 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 Q(1:14) O Data outputs, SSTL_2, Class II output. 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48 CY2SSTV16857 D(1:14) I Data input clocked on the crossing of the rising edge of, and the falling edge of. 39, 38, I/I Differential clock input. 4, 8, 12, 16, 21 Power Power supply voltage quiet, 2.5V nominal. 35 VREF I Input reference voltage, 1.25V nominal. Document #: Rev. *D Page 2 of 8

3 Absolute Maximum Conditions [1, 2, 3] This device contains circuitry designed to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, V in and V out should be constrained to the range: V SS < (V in or V out ) < V DD. Unused inputs must always be tied to an appropriate logic voltage level (either V SS or V DD ). Parameter Description Condition Min. Max. Unit V DD Supply Voltage [4] Non-functional VDC V DD Operating Voltage [4] Functional VDC V in Input Voltage Relative to V SS 0 V DD VDC V out Output Voltage Relative to V SS V DDQ VDC I OUT DC Output Current ±50 ma I IK Continuous Clamp Current V I < 0 or V I > V SS ±50 ma I OK Continuous Clamp Current V O < 0 50 ma I DD/ I SS Continuous current through each V DD or V SS ±100 ma LU I Latch Up Immunity Exceeds spec of 100 ma R PS Power Supply Ripple Ripple Frequency < 100 khz 150 mvp-p T s Temperature, Storage Non-functional C T a Temperature, Operating Ambient Functional C T j Temperature, Junction Functional 165 C Ø Jc Dissipation, Junction to Case Mil-Spec 883E Method C/W Ø JA Dissipation, Junction to Ambient JEDEC (JESD 51) C/W UL FL Flammability By design and verification V 0 Grade MSL Moisture Sensitivity By design and verification MSL 1 Grade ESD h ESD Protection (Human Body Model) 2000 V Table 1. DC Electrical Specifications (V DD = Temperature = 0 C to +85 C) Parameter Description Condition Min. Typ. Max. Unit V DD Supply Voltage PC1600,2100,2700 PC V V DDQ Output Supply Voltage PC1600,2100,2700 PC V V REF Reference voltage (V REF = V DDQ /2) PC1600,2100,2700 PC V V TT Termination voltage V REF 40 mv V REF V REF +4 0 mv V IH Input Voltage, High RESET 1.7 V V IL Input Voltage, Low RESET 0.7 V V OL Output Voltage, Low V DD /V DDQ = 2.3V to 2.7V, I OL = 0.2 V 100 µa, V DD = 2.3 to 2.7V V DD /V DDQ = 2.3V, I OL = 16 ma, V DD =2.3V 0.35 Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 3. All terminals except V DD. 4. V DD /V DDQ terminals. V Document #: Rev. *D Page 3 of 8

4 Table 1. DC Electrical Specifications (V DD = Temperature = 0 C to +85 C) (continued) Parameter Description Condition Min. Typ. Max. Unit V OH Output Voltage, High V DD /V DDQ = 2.3V to 2.7V, I OH = 100 µa, V DD =2.3 to 2.7V I IL Input Current Data Inputs, V DD 0.2 V DD /V DDQ = 2.3V, I OH = 16 ma 1.95 V I = 1.7V or 0.8V, V REF = 1.15V or ±5 µa 1.35V, V DD = 2.7V V I = 2.7V or 0,V REF = 1.15V or ± 5 µa 1.35V, V DD = 2.7V V I = 1.7V or 0.8V, V REF = 1.15V or ± 5 µa 1.35V, V DD = 3.6V V I = 2.7V or 0 ± 5 µa V I = 1.7V or 0.8V, V REF = 1.15V or ±1 µa 1.35V V I = 2.7V or 0, V REF = 1.15V or ± 1 µa 1.35V, V dd = 2.7V RESET V I = V DD or V SS, V DD = 2.7V ± 5 µa VREF V I = 1.5V or 1.35V, V DD = 2.7 ±5 µa I IH Input Current, High Data inputs only ma. I DD Dynamic Supply Current V I = 1.7V or 0.8V, I O = 0, V DD = 90 ma 2.7V V I = 2.7V or 0, I O = 0, V DD = 2.7V 90 ma C in Input pin capacitance RESET V I = 1.7V or 0.8V, I O = 0, V DD = 2.7V 3 pf Clock and Data Inputs pf L pin Pin Inductance All nh Table 2. AC Input Electrical Specifications (V DD = 2.5 VDC ± 5%, Temperature = 0 C to +85 C) V DD = 2.5V ± 0.2V Parameter Description Condition Min. Max. Unit F IN Input Clock Frequency, 200 MHz P W Pulse Duration, HIGH or LOW 3.3 ns T ACT Differential Inputs Active Time Data inputs must be LOW after RESET HIGH 22 ns T INACT Differential Inputs Inactive Time Data and clock inputs must be held at valid levels (not 22 ns floating) after RESET LOW T SET Set-up Time Fast slew rate, (see notes 5 and 7), Data before, 0.75 ns Slow slew rate, (see notes 6 and 7), Data before, 0.9 ns T HOLD Hold Time Fast slew rate, (see notes 5 and 7), Data after, 0.75 ns Slow slew rate (see notes 6 and 7), Data after, 0.9 ns I Vpp Input Voltage, Pk Pk 360 mv Notes: 5. For data signal input slew rate > 1 V/ns. 6. For data signal input slew rate > 0.5 V/ns and < 1 V/ns. 7., signals input slew rates are > 1 V/ns. V Document #: Rev. *D Page 4 of 8

5 Table 3. AC Output Electrical Specifications (V DD = 2.5V VDC ± 5%, Temperature = 0 C to +85 C) Output Buffer Characteristics CY2SSTV16857 V DD = 2.5V ± 0.2V Parameter Description Condition Min. Max. Unit F MAX 280 T DEL Propagation Delay from / Q ns to Q T PHL RESET Q 4.3 ns T R Rise Time Any Q V/ns T F Fall time Any Q V/ns Table 4. Output Buffer Voltage vs. Current (V/I) Characteristics Pull-Down Pull-Up Voltage (V) Min I (ma) Max I (ma) Min I (ma) Max I (ma) Document #: Rev. *D Page 5 of 8

6 Slew Rate The following table describes output-buffer slew-rate characteristics that are sufficient to meet the requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these rates is not mandatory if it can be adequately demonstrated that alternate characteristics meet the requirements of the registered DDR DIMM application. This information does not necessarily have to appear in the device data sheet. Obtain rise and fall time measurements by using the same procedure for obtaining Ramp data according to the current WIA IBIS specification. In particular it is very important to note that the following slew rates are specified at the output of the die, without package parasitics in the power, ground or output paths. The measurement points are at 20% and 80%. The slew-rate test load shall be a 50-ohm resistor to GND for Rise and a 50-ohm resistor to V DDQ for fall. The dv/dt ratio is reduced to V/ns. Table 5. Output Buffer Slew-Rate Characteristics dv/dt Min. Max. Rise 0.85 V/ns 4 V/ns Fall 1.00 V/ns 4 V/ns LVCMOS RESET Input IDD t inact VDD/2 VDD/2 t act 10% 90% VDD 0 V IDDH IDDL Figure 2. Voltage Waveforms Enable and Disable Times Low- and High-level Enabling [11] Input Output t PLH VICR VTT VICR t PHL VI(PP) VOH VTT VOL Figure 3. Voltage Waveforms Propagation Delay Times [12] [9, 10] Test Configurations V DD = 2.5V ±0.2V Timing Diagrams Timing Input t su VICR t h VI(PP) LVCMOS RESET Input VDD/2 t PHL VIH VIL Output VOH VTT VOL Figure 4. Voltage Waveforms Propagation Delay Times [11 Data Input VREF* VREF* VIH** VIL*** Figure 1. Voltage Waveforms Set-up and Hold [11, 13, 14] Times From Output Under Test VTT RL = 50 Ohm Test Point CL = 30 pf Figure 5. Load Circuit [8] t w Input VREF* VREF* VIH** VIL*** Figure 6. Voltage Waveforms Pulse Duration Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or, and IO = 0 ma. 10. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 50 ohm input slew rate = 1 V/ns ±20% (unless otherwise specified). 11. the outputs are measured one at a time with one transition per measurement. 12. *VTT = VREF = / **VIH = VREF mv (AC voltage levels). 14. ***VIL = VREF 350 mv (AC voltage levels). [13, 14] Document #: Rev. *D Page 6 of 8

7 Ordering Information Part Number Package Type Product Flow CY2SSTV16857ZC 48-pin TSSOP Commercial, 0 to 70 C CY2SSTV16857ZCT 48-pin TSSOP Tape and Reel Commercial, 0 to 70 C CY2SSTV16857ZI 48-pin TSSOP Industrial, 40 to 85 C CY2SSTV16857ZIT 48-pin TSSOP Tape and Reel Industrial, 40 to 85 C Lead-Free CY2SSTV16857ZXC 48-pin TSSOP Commercial, 0 to 70 C CY2SSTV16857ZXCT 48-pin TSSOP Tape and Reel Commercial, 0 to 70 C CY2SSTV16857ZXI 48-pin TSSOP Industrial, 40 to 85 C CY2SSTV16857ZXIT 48-pin TSSOP Tape and Reel Industrial, 40 to 85 C Package Diagram 48-lead (240-mil) TSSOP II Z [0.019] 24 1 DIMENSIONS IN MM[INCHES] MIN. MAX [0.236] 6.198[0.244] 7.950[0.313] 8.255[0.325] REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG [0.488] [0.496] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0.20[0.008] SEATING PLANE [0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008] *C All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: Rev. *D Page 7 of 8 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

8 Document History Page Document Title: CY2SSTV Bit Registered Buffer PC2700-/PC3200-Compliant Document Number: Rev. ECN No. Issue Date Orig. of Change Description of Change ** /21/02 HWT New Data Sheet *A /18/02 RBI Add power-up requirements to maximum ratings information *B /20/03 RGL Changed the Supply voltage (V DD ) and Output supply voltage (V DDQ ) values from 2.3/2.5/2.7 to 2.5/2.6/2.7Volts in the DC Electrical Specs. table Changed the Reference voltage (V REF ) values from 1.15/1.25/1.35 to 1.25/1.3/1.35V in the DC Electrical Specs. table Moved the FMAX value from Min to Max in the AC Output Electrical Spec. table Changed the T R /T F max values from 15.9 to 4V/ns Added Industrial Temp. range in the ordering information Added PC2700-/PC3200-Compliant to the title *C /03/03 IJA Removed last Features bullet and second-to-last TVSOP package availability Kept only 48-pin TSSOP *D See ECN RGL Added Lead Free Devices Document #: Rev. *D Page 8 of 8

ICSSSTV DDR 24-Bit to 48-Bit Registered Buffer. Integrated Circuit Systems, Inc. Pin Configuration. Truth Table 1.

ICSSSTV DDR 24-Bit to 48-Bit Registered Buffer. Integrated Circuit Systems, Inc. Pin Configuration. Truth Table 1. Integrated Circuit Systems, Inc. ICSSSTV32852 DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: DDR Memory Modules Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 SSTL_2