128K x 8 Static RAM CY7C1019B CY7C10191B. Features. Functional Description. Logic Block Diagram. Pin Configurations

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1 128K x 8 Static RAM Features High speed t AA = 10, 12, 15 ns CMOS for optimum speed/power Center power/ground pinout Automatic power-down when deselected Easy memory expansion with and OE options Functionally equivalent to CY7C1019 Functional Description The /10191B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Logic Block Diagram Writing to the device is accomplished by taking Chip Enable () and Write Enable () inputs LOW. Data on the eight I/O pins (I/O 0 through I/O 7 ) is then written into the location specified on the address pins (A 0 through A 16 ). Reading from the device is accomplished by taking Chip Enable () and Output Enable (OE) LOW while forcing Write Enable () HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O 0 through I/O 7 ) are placed in a high-impedance state when the device is deselected ( HIGH), the outputs are disabled (OE HIGH), or during a write operation ( LOW, and LOW). The /10191B is available in standard 32-pin TSOP Type II and 400-mil-wide SOJ packages. Customers should use part number when ordering parts with 10 ns t AA, and when ordering 12 and 15 ns t AA. Pin Configurations SOJ / TSOPII Top View A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 ROW DECODER INPUT BUFFER 512 x 256 x 8 ARRAY COLUMN DECODER SENSE AMPS POR DOWN I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A 0 A 1 A 2 A 3 I/O 0 I/O 1 V SS I/O 2 I/O 3 A 4 A 5 A 6 A A 16 A 15 A 14 A 13 OE I/O 7 I/O 6 V SS I/O 5 I/O 4 A 12 A 11 A 10 A 9 A 8 OE A9 A 10 A 11 A A 14 A 15 A 16 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: Rev. *B Revised October 6, 2005

2 Selection Guide 7C10191B-10 7C1019B-12 7C1019B-15 Unit Maximum Access Time ns Maximum Operating Current ma Maximum Standby Current ma L 1 1 ma Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage on to Relative GND [1] V to +7.0V DC Voltage Applied to Outputs in High Z State [1] V to + 0.5V DC Input Voltage [1] V to + 0.5V Current into Outputs (LOW) ma Static Discharge Voltage... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current... >200 ma Operating Range Ambient Range Temperature [2] Commercial 0 C to +70 C 5V ± 10% Industrial 40 C to +85 C 5V ± 10% Electrical Characteristics Over the Operating Range 7C10191B-10 7C1019B-12 7C1019B-15 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit V OH Output HIGH Voltage = Min., V I OH = 4.0 ma V OL Output LOW Voltage = Min., V I OL = 8.0 ma V IH Input HIGH Voltage V V IL Input LOW Voltage [1] V I IX Input Load Current GND < V I < μa I OZ Output Leakage Current GND < V I <, Output Disabled μa I CC I SB1 I SB2 Capacitance [3] Operating Supply Current Automatic Power-Down Current TTL Inputs Automatic Power-Down Current CMOS Inputs = Max., I OUT = 0 ma, f = f MAX = 1/t RC Max., > V IH V IN > V IH or V IN < V IL, f = f MAX Max., > 0.3V, V IN > 0.3V, or V IN < 0.3V, f = ma ma L ma L 1 1 Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 6 pf C OUT Output Capacitance = 5.0V 8 pf Notes: 1. V IL (min.) = 2.0V for pulse durations of less than 20 ns. 2. T A is the Instant On case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: Rev. *B Page 2 of 8

3 AC Test Loads and Waveforms R1 480Ω 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE (a) R1 480Ω 5V OUTPUT R2 5 pf 255Ω INCLUDING JIG AND SCOPE (b) R2 255Ω 3.0V GND 3 ns 10% ALL INPUT PULSES 90% 90% 10% 3 ns Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics [4] Over the Operating Range 7C10191B-10 7C1019B-12 7C1019B-15 Parameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle t RC Read Cycle Time ns t AA Address to Data Valid ns t OHA Data Hold from Address Change ns t A LOW to Data Valid ns t DOE OE LOW to Data Valid ns t LZOE OE LOW to Low Z ns t HZOE OE HIGH to High Z [5, 6] ns t LZ LOW to Low Z [6] ns t HZ HIGH to High Z [5, 6] ns t PU LOW to Power-Up ns t PD HIGH to Power-Down ns [7, 8] Write Cycle t WC Write Cycle Time ns t S LOW to Write End ns t AW Address Set-Up to Write End ns t HA Address Hold from Write End ns t SA Address Set-Up to Write Start ns t P Pulse Width ns t SD Data Set-Up to Write End ns t HD Data Hold from Write End ns t LZ HIGH to Low Z [6] ns t HZ LOW to High Z [5, 6] ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance. 5. t HZOE, t HZ, and t HZ are specified with a load capacitance of 5 pf as in part (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 6. At any given temperature and voltage condition, t HZ is less than t LZ, t HZOE is less than t LZOE, and t HZ is less than t LZ for any given device. 7. The internal write time of the memory is defined by the overlap of LOW and LOW. and must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 ( controlled, OE LOW) is the sum of t HZ and t SD. Document #: Rev. *B Page 3 of 8

4 Data Retention Characteristics Over the Operating Range (L Version Only) Parameter Description Conditions Min. Max. Unit V DR for Data Retention No input may exceed + 0.5V 2.0 V = V DR = 2.0V, I CCDR Data Retention Current 300 μa > 0.3V, [3] t CDR Chip Deselect to Data Retention Time V IN > 0.3V or V IN < 0.3V 0 ns t R Operation Recovery Time 200 μs Data Retention Waveform 3.0V DATA RETENTION MODE V DR > 2V 3.0V t CDR t R Switching Waveforms Read Cycle No. 1 [9, 10] t RC t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID [10, 11] Read Cycle No. 2 (OE Controlled) t RC t A OE t HZOE thz t DOE DATA OUT t LZOE HIGH IMPEDAN DATA VALID HIGH IMPEDAN SUPPLY CURRENT t LZ t PU 50% t PD 50% ICC ISB Notes: 9. Device is continuously selected. OE, = V IL. 10. is HIGH for read cycle. 11. Address valid prior to or coincident with transition LOW. Document #: Rev. *B Page 4 of 8

5 Switching Waveforms (continued) Write Cycle No. 1 ( Controlled) [12, 13] t WC t S t SA t AW t P t S t HA t SD t HD DATA I/O DATA VALID [12, 13] Write Cycle No. 2 ( Controlled, OE HIGH During Write) t WC t S t AW t HA t SA t P OE t SD t HD DATA I/O NOTE 14 DATA IN VALID t HZOE Notes: 12. Data I/O is high impedance if OE = V IH. 13. If goes HIGH simultaneously with going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. Document #: Rev. *B Page 5 of 8

6 Switching Waveforms (continued) Write Cycle No. 3 ( Controlled, OE LOW) [13] t WC t S t AW t HA t SA t P t SD t HD DATA I/O NOTE 14 DATA VALID t HZ t LZ Truth Table OE I/O 0 I/O 7 Mode Power H X X High Z Power-Down Standby (I SB ) X X X High Z Power-Down Standby (I SB ) L L H Data Out Read Active (I CC ) L X L Data In Write Active (I CC ) L H H High Z Selected, Outputs Disabled Active (I CC ) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 12-12VC V33 32-Lead 400-Mil Molded SOJ Commercial -12ZC ZS32 32-Lead TSOP Type II -12ZXC ZS32 32-Lead TSOP Type II (Pb -Free ) 15-15VC V33 32-Lead 400-Mil Molded SOJ Commercial -15VI V33 32-Lead 400-Mil Molded SOJ Industrial -15ZC ZS32 32-Lead TSOP Type II Commercial -15ZXC ZS32 32-Lead TSOP Type II (Pb -Free) -15ZI ZS32 32-Lead TSOP Type II Industrial Please contact local sales representative regarding availability of parts Document #: Rev. *B Page 6 of 8

7 Package Diagrams 32-Lead (400-mil) Molded SOJ V A *B 32-Lead TSOP II ZS ** All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: Rev. *B Page 7 of 8 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

8 Document History Page Document Title: / 128K x 8 Static RAM Document Number: Orig. of REV. ECN NO. Issue Date Change Description of Change ** /25/01 SZV Change from Spec number: to *A /14/02 HGK 1. SOJ (400-mil) package outline replacing incorrect SOJ package 2. Pin for pin compatible with CY7C Industrial packages added to Ordering Information *B See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from 3901 North First Street to 198 Champion Court Updated the Ordering Information Table on page # 6. Document #: Rev. *B Page 8 of 8

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Features High speed t AA = 12 ns Low active power 1320 mw (max.) Low CMOS standby power (Commercial L version) 2.75 mw (max.) 2.0V Data Retention (400 µw at 2.0V retention) Automatic power-down when deselected