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1 TOSHIBA TC551001BPL/BFL/BFTL/BTRL-70L/85L SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM Description The TC551001BPL is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits using CMOS technology, and operated from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating current of 5mA/MHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2µA typically. The TC551001BPL has three control inputs. Chip Enable inputs (CE1, CE2) allow for device selection and data retention control, while an Output Enable input (OE) provides fast memory access. The TC551001BPL is suitable for use in microprocessor application systems where high speed, low power, and battery backup are required. The TC551001BPL is offered in a standard dual-in-line 32-pin plastic package, a small outline plastic package, and a thin small outline plastic package (forward, reverse type). Features Low power dissipation: 27.5mW/MHz (typ.) Standby current: 4µA (max.) at Ta = 25 C 5V single power supply Access time (max.) TC551001BPL/BFL/BFTL/BTRL -70L -85L Access Time 70ns 85ns CE1 Access Time 70ns 85ns CE2 Access Time 70ns 85ns OE Access Time 35ns 45ns Power down feature: CE1, CE2 Data retention supply voltage: 2.0 ~ 5.5V Inputs and outputs directly TTL compatible Package TC551001BPL : DIP32-P-600 TC551001BFL : SOP32-P-525 TC551001BFTL : TSOP32-P-0820 TC551001BTRL : TSOP32-P-0820A Pin Names A0 ~ A16 R/W OE CE1, CE2 I/O1 ~ I/O8 V DD GND N.C. Address Inputs Read/Write Control Input Output Enable Input Chip Enable Inputs Data Input/Output Power (+5V) Ground No Connection Pin Connection (Top View) TSOP Pinout PIN NO PIN NAME A 11 A 9 A 8 A 13 R/W CE2 A 15 V DD NC A 16 A 14 A 12 A 7 A 6 A 5 A 4 PIN NO PIN NAME A 3 A 2 A 1 A 0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A 10 OE TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 1
2 TC551001BPL/BFL/BFTL/BTRL-70L/85L Static RAM SR Block Diagram Operating Mode OPERATION MODE CE1 CE2 OE R/W I/O1 ~ I/O8 POWER Read L H L H D OUT I DDO Write L H * L D IN I DDO Output Deselect L H H H High-Z I DDO Standby H * * * High-Z I DDS * L * * High-Z I DDS * H or L Maximum Ratings SYMBOL ITEM RATING UNIT V DD Power Supply Voltage -0.3 ~ 7.0 V V IN Input Voltage -0.3* ~ 7.0 V V I/O Input and Output Voltage -0.5 ~ V DD V P D Power Dissipation 1.0/0.6** W T SOLDER Soldering Temperature (10s) 260 C T STRG Storage Temperature -55 ~ 150 C T OPR Operating Temperature 0 ~ 70 C * -3.0V at pulse width of 50ns Max ** SOP 2 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
3 SR Static RAM TC551001BPL/BFL/BFTL/BTRL-70L/85L DC Recommended Operating Conditions SYMBOL PARAMETER MIN. TYP. MAX. UNIT V DD Power Supply Voltage V IH Input High Voltage 2.2 V DD V IL Input Low Voltage -0.3* 0.8 V DH Data Retention Supply Voltage V * -3.0V at pulse width of 50ns Max. DC and Operating Characteristics (Ta = 0 ~ 70ºC, V DD = 5V±10%) SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT I LI Input Leakage Current V IN = 0 ~ V DD ±1.0 µa I LO Output Leakage Current CE1 = V IH or CE2 = V IL or R/W = V IL or OE = V IH, V OUT = 0 ~ V DD ±1.0 µa I OH Output High Current V OH = 2.4V -1.0 ma I OL Output Low Current V OL = 0.4V 4.0 ma I DDO1 I DDO2 I DDS1 I DDS2 (1) Operating Current Standby Current CE1 = V IL and CE2 = V IH and R/W = V IH, I OUT = 0mA Other Inputs = V IH /V IL Note: (1) In standby mode with CE1 V DD - 0.2V, these specification limits are guaranteed under the condition of CE2 V DD - 0.2V or CE2 0.2V. Capacitance (Ta = 25ºC, f = 1MHz) CE1 = 0.2V and CE2 = V DD - 0.2V R/W = V DD - 0.2V I OUT = 0mA Other Inputs = V DD - 0.2V/0.2V t cycle t cycle Min. 70 1µs 20 Min. 60 1µs 10 CE1 = V IH or CE2 = V IL 3 ma CE1 = V DD - 0.2V or CE2 = 0.2V V DD = 2.0V ~ 5.5V Ta = 0 ~ 70 C 30 Ta = 25 C 2 4 SYMBOL PARAMETER TEST CONDITION MAX. UNIT ma µa C IN Input Capacitance V IN = GND 10 C OUT Output Capacitance V OUT = GND 10 pf Note: This parameter is periodically sampled and is not 100% tested. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 3
4 TC551001BPL/BFL/BFTL/BTRL-70L/85L Static RAM SR AC Characteristics (Ta = 0 ~ 70 C, V DD = 5V±10%) Read Cycle TC551001BPL/BFL/BFTL/BTRL SYMBOL PARAMETER -70L -85L UNIT MIN. MAX. MIN. MAX. t RC Read Cycle Time t ACC Address Access Time t CO1 CE1 Access Time t CO2 CE2 Access Time t OE Output Enable to Output in Valid t COE Chip Enable (CE1, CE2) to Output in Low-Z t OEE Output Enable to Output in Low-Z 5 5 t OD Chip Enable (CE1, CE2) to Output in High-Z t ODO Output Enable to Output in High-Z t OH Output Data Hold Time ns Write Cycle TC551001BPL/BFL/BFTL/BTRL SYMBOL PARAMETER -70L -85L UNIT MIN. MAX. MIN. MAX. t WC Write Cycle Time t WP Write Pulse Width t CW Chip Selection to End of Write t AS Address Setup Time 0 0 t WR Write Recovery Time 0 0 t ODW R/W to Output in High-Z t OEW R/W to Output in Low-Z 5 5 t DS Data Setup Time t DH Data Hold Time 0 0 ns AC Test Conditions Input Pulse Levels 2.4V/0.6V Input Pulse Rise and Fall Time 5ns Input Timing Measurement Reference Level 1.5V Output Timing Measurement Reference Level 1.5V Output Load 1 TTL Gate and C L = 100pF 4 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
5 SR Static RAM TC551001BPL/BFL/BFTL/BTRL-70L/85L Timing Waveforms Read Cycle (1) Write Cycle 1 (4) (R/W Controlled Write) TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 5
6 TC551001BPL/BFL/BFTL/BTRL-70L/85L Static RAM SR Write Cycle 2 (4) (CE1 Controlled Write) Write Cycle 3 (4) (CE2 Controlled Write) 6 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
7 SR Static RAM TC551001BPL/BFL/BFTL/BTRL-70L/85L Notes: 1. R/W is High for Read Cycle. 2. Assuming that CE1 Low transition or CE2 High transition occurs coincident with or after the R/W low transition, Outputs remain in a high impedance state. 3. Assuming that CE1 High transition or CE2 Low transition occurs coincident with or prior to the R/W high transition, Outputs remain in a high impedance state. 4. Assuming that OE is High for a Write Cycle, Outputs are in a high impedance state during this period. 5. The I/O may be in the output state during this time, input signals of opposite phase must not be applied. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 7
8 TC551001BPL/BFL/BFTL/BTRL-70L/85L Static RAM SR Data Retention Characteristics (Ta = 0 ~ 70 C) SYMBOL PARAMETER MIN. TYP. MAX. UNIT V DH Data Retention Supply Voltage V I DDS2 Standby Current V DD = 3.0V 15* V DD = 5.5V 30 µa t CDR Chip Deselect to Data Retention Mode 0 ns t R Recovery Time 5 ms *3µA (max.) Ta = 0 ~ 40 C CE1 Controlled Data Retention Mode (1) CE2 Controlled Data Retention Mode (3) Notes: 1. In the CE1 controlled data retention mode, minimum standby current is achieved under the condition CE2 0.2V or CE2 V DD - 0.2V. 2. If the V IH of CE1 is 2.2V in operation, during the period that the V DD voltage is going down from 4.5V to 2.4V, I DDS1 current flows. 3. In the CE2 controlled data retention mode, minimum standby current is achieved under the condition CE2 0.2V. 8 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
9 SR Static RAM TC551001BPL/BFL/BFTL/BTRL-70L/85L Outline Drawing DIP32-P-600 Unit in mm TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 9
10 TC551001BPL/BFL/BFTL/BTRL-70L/85L Static RAM SR Outline Drawing SOP32-P-525 Unit in mm 10 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
11 SR Static RAM TC551001BPL/BFL/BFTL/BTRL-70L/85L Outline Drawing TSOP32-P-0820 Unit in mm TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 11
12 TC551001BPL/BFL/BFTL/BTRL-70L/85L Static RAM SR Outline Drawing TSOP32-P-0820A Unit in mm 1. This technical data may be controlled under U.S. Export Administration Regulations and may be subject to the approval of the U.S. Department of Commerce prior to export. Any export or re-export, directly or indirectly, in contravention of the U.S. Export Administration Regulations is strictly prohibited. 2. LIFE SUPPORT POLICY Toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate officer of Toshiba America, Inc. Life support systems are either systems intended for surgical implant in the body or systems which sustain life. A critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness. 3. The information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. All information in this data book is subject to change without prior notice. Furthermore, Toshiba cannot assume responsibility for the use of any license under the patent rights of Toshiba or any third parties. 12 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
13 Back to Memory
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I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7
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I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7 A 15 7
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I/O 1 I/O 2 I/O 3 A 10 6
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524,288-Word x 16-Bit or 1,048,576-Word x 8-Bit One Time PROM
Semiconductor 524,288Word x 16Bit or 1,048,576Word x 8Bit One Time PROM 1A DESCRIPTION The is a 8Mbit electrically Programmable ReadOnly Memory whose configuration can be electrically switched between
MM74HC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
I/O 1 I/O 2 I/O 3 A 10 6
Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 495 mw (Max, L version) Low standby power 0.275 mw (Max, L version) 2V data retention ( L version only) Easy memory expansion
CD4541BC Programmable Timer
CD4541BC Programmable Timer General Description The CD4541BC Programmable Timer is designed with a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors,
A 4 A 3 A 2 ROW DECODER 64K x 16 RAM Array I/O 1 I/O X 2048 I/O 9 I/O 16
021 CY7C1021 Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 1320 mw (max.) Automatic power-down when deselected Independent Control of Upper and Lower bits Available in
28C010T. 1 Megabit (128K x 8-Bit) EEPROM. Memory FEATURES: DESCRIPTION: Logic Diagram
28C1T 1 Megabit (128K x 8-Bit) EEPROM FEATURES: 128k x 8-bit EEPROM RAD-PAK radiation-hardened agait natural space radiation Total dose hardness: - > 1 krad (Si), depending upon space mission Excellent
1-Megabit (128K x 8) Unregulated Battery-Voltage OTP EPROM AT27BV010
Features Fast Read Access Time 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power
64K x V Static RAM Module
831V33 Features High-density 3.3V 2-megabit SRAM module High-speed SRAMs Access time of 12 ns Low active power 1.512W (max.) at 12 ns 64 pins Available in ZIP format Functional Description CYM1831V33 64K
IS62/65WV102416EALL IS62/65WV102416EBLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating (typical): - 10.8mW (1.8V), 18mW (3.0V) CMOS Standby (typical): - 48
4-Megabit (512K x 8) OTP EPROM AT27C040
Features Fast Read Access Time 70 ns Low Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 32-lead PDIP 32-lead PLCC 32-lead TSOP 5V ± 10% Supply High Reliability
MM74C911 4-Digit Expandable Segment Display Controller
4-Digit Expandable Segment Display Controller General Description The display controller is an interface element with memory that drives a 4-digit, 8-segment LED display. The allows individual control
89LV Megabit (512K x 32-Bit) Low Voltage MCM SRAM 89LV1632 FEATURES: DESCRIPTION: Logic Diagram. 16 Megabit (512k x 32-bit) SRAM MCM
89LV1632 16 Megabit (512K x 32Bit) Low Voltage MCM SRAM 16 Megabit (512k x 32bit) SRAM MCM CS 14 Address OE, WE 89LV1632 Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM Ground MCM FEATURES: I/O 7 I/O 815 I/O
CD4069UBC Inverter Circuits
CD4069UBC Inverter Circuits General Description The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating range, low power
256K (32K x 8) Static RAM
256K (32K x 8) Static RAM Features Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Automotive-E: 40 C to 125 C Speed: 70 ns Low Voltage Range: 2.7V to 3.6V
EEPROM AS58LC K x 8 EEPROM Radiation Tolerant. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535
128K x 8 EEPROM Radiation Tolerant AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535 FEATURES High speed: 250ns and 300ns Data Retention: 10 Years Low power dissipation, active current (20mW/MHz (TYP)),
A13 A12 A11 A10 ROW DECODER DQ0 INPUT DATA CONTROL WE OE DESCRIPTION: DDC s 32C408B high-speed 4 Megabit SRAM
32C48B 4 Megabit (12K x 8-Bit) SRAM A13 A A1 A2 A3 A4 CS 1 36 NC A18 A17 A16 A1 OE A12 A11 A1 A9 A8 A7 A6 A A4 ROW DECODER MEMORY MATRIX 124 ROWS x 496 COLUMNS I/O1 I/O8 I/O2 Vcc Vss I/O3 32C48B I/O7 Vss
DESCRIPTION ECC. Array 1Mx5
1Mx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES High-speed access time: 10ns, 12ns A0 A19 Single power supply 2.4V-3.6V Error Detection and Correction with optional ERR1/ERR2 output
8K x 8 Static RAM CY6264. Features. Functional Description
8K x 8 Static RAM Features 55, 70 ns access times CMOS for optimum speed/power Easy memory expansion with CE 1, CE 2, and OE features TTL-compatible inputs and outputs Automatic power-down when deselected
1 Mbit (128K x 8) Static RAM
1 Mbit (128K x 8) Static RAM Features Temperature Ranges Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Pin and Function compatible with CY7C1019BV33 High Speed t AA = 10 ns CMOS for optimum Speed
UNISONIC TECHNOLOGIES CO., LTD CD4069
UNISONIC TECHNOLOGIES CO., LTD CD4069 INVERTER CIRCUITS DESCRIPTION The UTC CD4069 consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating
FST32X Bit Bus Switch
FST32X245 16-Bit Bus Switch General Description The Fairchild Switch FST32X245 provides 16-bits of high speed CMOS TTL-compatible bus switching in a standard flow-through mode. The low On Resistance of
28LV Megabit (128K x 8-Bit) EEPROM. Memory DESCRIPTION: FEATURES: 28LV011A. Logic Diagram
28LV11 1 Megabit (128K x 8-Bit) EEPROM V CC V SS High Voltage Generator I/O I/O7 RDY/Busy RES OE I/O Buffer and Input Latch CE WE RES Control Logic Timing 28LV11A A A6 Y Decoder Y Gating A7 Address Buffer
P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM
ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 1/1/15//5 (Commercial) 15//5/35 (Military) Low Power Operation 715 mw Active 1 (Commercial)
TC4011BP,TC4011BF,TC4011BFN,TC4011BFT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4011BP/BF/BFN/BFT TC4011BP,TC4011BF,TC4011BFN,TC4011BFT TC4011B Quad 2 Input NAND Gate The TC4011B is 2-input positive logic NAND gate respectively.
NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package
NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package Description: The NTE74S188 Schottky PROM memory is organized in the popular 32 words by 8 bits configuration. A memory
MM5452/MM5453 Liquid Crystal Display Drivers
MM5452/MM5453 Liquid Crystal Display Drivers General Description The MM5452 is a monolithic integrated circuit utilizing CMOS metal gate, low threshold enhancement mode devices. It is available in a 40-pin
DM74ALS174 DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Hex/Quad D-Type Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
FST Bit Bus Switch
24-Bit Bus Switch General Description The Fairchild Switch FST16211 provides 24-bits of highspeed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to
UNISONIC TECHNOLOGIES CO., LTD CD4541
UNISONIC TECHNOLOGIES CO., LTD CD4541 PROGRAMMABLE TIMER DESCRIPTION The CD4541 programmable timer comprise a 16-stage binary counter, an integrated oscillator for use with an external capacitor and two
SOIC (SOP) NC A8 A9 A10 A11 A12 A13 A14 A15 A16 NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 BYTE/VPP GND O15/A-1 GND O7 O14 O6 O13 O5 O12 O4 VCC
Features Read Access Time - 100 ns Word-wide or Byte-wide Configurable 8-Megabit Flash and Mask ROM Compatable Low Power CMOS Operation -100 µa Maximum Standby - 50 ma Maximum Active at 5 MHz Wide Selection
CD4538BC Dual Precision Monostable
CD4538BC Dual Precision Monostable General Description The CD4538BC is a dual, precision monostable multivibrator with independent trigger and reset controls. The device is retriggerable and resettable,
NM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE Bus Interface)
NM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE Bus Interface) General Description The NM93C56 devices are 2048 bits of CMOS non-volatile electrically erasable memory divided into 28 6-bit registers. They
PSRAM 2-Mbit (128K x 16)
PSRAM 2-Mbit (128K x 16) Features Wide voltage range: 2.7V 3.6V Access Time: 55 ns, 70 ns Ultra-low active power Typical active current: 1mA @ f = 1 MHz Typical active current: 14 ma @ f = fmax (For 55-ns)
256K (32K x 8) OTP EPROM AT27C256R
Features Fast Read Access Time 45 ns Low-Power CMOS Operation 100 µa Max Standby 20 ma Max Active at 5 MHz JEDEC Standard Packages 28-lead PDIP 32-lead PLCC 28-lead TSOP and SOIC 5V ± 10% Supply High Reliability
4-Mbit (512K words 8 bit) Static RAM with Error-Correcting Code (ECC)
4-Mbit (512K words 8 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (512K words 8 bit) Static RAM with Error-Correcting Code (ECC) Features High speed t AA = 10 ns Embedded ECC for single-bit
PART TEMP RANGE PIN-PACKAGE SPEED
Rev 0; 8/06 General Description The is a 16Mb reflowable nonvolatile (NV) SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These
SENSE AMPS POWER DOWN
185 CY7C185 8K x 8 Static RAM Features High speed 15 ns Fast t DOE Low active power 715 mw Low standby power 220 mw CMOS for optimum speed/power Easy memory expansion with,, and OE features TTL-compatible
74AC574 74ACT574 Octal D-Type Flip-Flop with 3-STATE Outputs
Octal D-Type Flip-Flop with 3-STATE Outputs General Description The AC/ACT574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The
CD4047BC Low Power Monostable/Astable Multivibrator
Low Power Monostable/Astable Multivibrator General Description The CD4047B is capable of operating in either the monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
Rev. No. History Issue Date Remark
8K X 8 BIT CMOS SRAM Document Title 8K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 9, 2004 Preliminary 1.0 Remove non-pb-free package type July 3, 2006
TC74ACT74P,TC74ACT74F,TC74ACT74FN,TC74ACT74FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT74P/F/FN/FT TC74ACT74P,TC74ACT74F,TC74ACT74FN,TC74ACT74FT Dual D-Type Flip Flop with Preset and Clear The TC74ACT74 is an advanced high