Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) BLOCK DIAGRAM

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1 Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable FEATURES DESCRIPTION Very low operation voltage : 45 ~ 55V Very low power consumption : = 50V C-grade: 40mA (Max) operating current I -grade: 45mA (Max) operating current 06uA (Typ) CMOS standby current High speed access time : ns (Max) at = 50V ns (Max) at = 50V Automatic power down when chip is deselected Three state outputs and TTL compatible Fully static operation Data retention supply voltage as low as 15V Easy expansion with, CE2 and OE options I/O Configuration x8/x16 selectable by CIO, LB and UB pin The is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits or 262,144 bytes by 8 bits selectable by CIO pin and operates from a wide range of 45V to 55V supply voltage Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 06uA and maximum access time of 70/55 ns in 5V operation Easy memory expansion is provided by active HIGH chip enable2(ce2), active LOW chip enable1(), active LOW output enable(oe) and three-state output drivers The has an automatic power down feature, reducing the power consumption significantly when chip is deselected The is available in DICE form and 48-pin BGA type PRODUCT FAMILY PRODUCT FAMILY DC AC DI AI OPERATING TEMPERATURE RANGE SPEED ( ns ) STANDBY ( ICCSB1, Max ) POWER DISSIPATION Operating ( ICC, Max ) =50V =50V =50V +0 O C to +70 O C 45V ~ 55V 70 / 55 6uA 40mA -40 O C to +85 O C 45V ~ 55V 70 / 55 25uA 45mA PKG TYPE DICE BGA DICE BGA PIN CONFIGURATION BLOCK DIAGRAM A15 A14 A13 A12 A11 A10 A9 A8 Address Input Buffer 20 Row Decoder 1024 Memory Array 1024 x 2048 A7 A6 D0 D15 16(8) 16(8) Data Input Buffer 16(8) Data Output Buffer 16(8) 2048 Column I/O Write Driver Sense Amp 128(256) Column Decoder CE2 WE OE UB LB CIO Control 14(16) Address Input Buffer A16 A0 A1 A2 A3 A4 A5 (SAE) Vdd Vss Brilliance Semiconductor Inc reserves the right to modify document contents without notice 1

2 PIN DESCRIPTIONS Name A0-A16 Address Input Function These 17 address inputs select one of the 131,072 x 16-bit words in the RAM SAE Address Input CIO x8/x16 select input Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input OE Output Enable Input LB and UB Data Byte Control Input D0 - D15 Data Input/Output Ports This address input incorporates with the above 17 address input select one of the 262,144 x 8-bit bytes in the RAM if the CIO is LOW Don't use when CIO is HIGH This input selects the organization of the SRAM 131,072 x 16-bit words configuration is selected if CIO is HIGH 262,144 x 8-bit bytes configuration is selected if CIO is LOW is active LOW and CE2 is active HIGH Both chip enables must be active to read from or write to the device If either chip enable is not active, the device is deselected and is in a standby power mode The DQ pins will be in the high impedance state when the device is deselected The write enable input is active LOW and controls read and write operations With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location The output enable input is active LOW If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled The DQ pins will be in the high impedance state when OE is inactive Lower byte and upper byte data input/output control pins The chip is deselected when both LB and UB pins are HIGH These 16 bi-directional ports are used to read data from or write data into the RAM Power Supply Gnd Ground 2

3 TRUTH TABLE MODE CE2 OE WE CIO LB UB SAE D0~7 D8~15 VCC Current Fully Standby H X X X X X X X L X X X High-Z High-Z I CCSB, I CCSB1 Output Disable L H H H X X X X High-Z High-Z I CC Read from SRAM ( WORD mode ) L H L H H L H Dout High-Z H L X High-Z Dout L L Dout Dout I CC Write to SRAM ( WORD mode ) L H X L H L H Din X H L X X Din L L Din Din I CC Read from SRAM ( BYTE Mode ) Write to SRAM ( BYTE Mode ) L H L H L X X A-1 Dout High-Z I CC L H X L L X X A-1 Din X I CC ABSOLUTE MAXIMUM RATINGS (1) SYMBOL PARAMETER RATING UNITS V TERM Terminal Voltage with Respect to GND -05 to +05 O T BIAS Temperature Under Bias -40 to +125 C O T STG Storage Temperature -60 to +150 C P T Power Dissipation 10 W I OUT DC Output Current 20 ma 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability V OPERATING RANGE RANGE AMBIENT TEMPERATURE Commercial 0 O C to +70 O C 45V ~ 55V Industrial -40 O C to +85 O C 45V ~ 55V CAPACITANCE (1) (TA = 25 o C, f = 10 MHz) SYMBOL PARAMETER CONDITIONS MAX UNIT CIN Input Capacitance VIN=0V 6 pf CDQ Input/Output Capacitance VI/O=0V 8 pf 1 This parameter is guaranteed and not tested 3

4 DC ELECTRICAL CHARACTERISTICS (TA = 0 o C to +70 o C) PARAMETER NAME V IL V IH PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNITS Guaranteed Input Low Voltage (2) =50V V Guaranteed Input High Voltage (2) =50V V I IL Input Leakage Current = Max, VIN = 0V to ua I OL Output Leakage Current = Max, = VIHor CE2=V ILor OE = VIH, VI/O = 0V to ua V OL Output Low Voltage = Max, I OL= 2mA =50V V V OH Output High Voltage = Min, IOH= -1mA =50V V I CC Operating Power Supply Current = Max, = VIL, CE2=VIH =50V IDQ = 0mA, F = Fmax (3) ma I CCSB Standby Current-TTL = Max, = VIH or CE2=VIL IDQ = 0mA =50V ma I CCSB1 Standby Current-CMOS = Max, -02V or CE2 02V, Other inputs - 02V or VIN 02V =50V ua 1 Typical characteristics are at TA = 25 o C 2 These are absolute values with respect to device ground and all overshoots due to system or tester notice are included 3 Fmax = 1/t RC 4

5 DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70 o C ) SYMBOL PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNITS V DR for Data Retention - 02V or CE2 02V or V IN - 02V or V IN 02V V I CCDR Data Retention Current - 02V or CE2 02V V IN - 02V or V IN 02V ua t CDR Chip Deselect to Data Retention Time See Retention Waveform ns t R Operation Recovery Time T RC (2) ns 1 = 15V, T A = + 25 O C 2 t RC = Read Cycle Time LOW V CC DATA RETENTION WAVEFORM (1) ( Controlled ) Data Retention Mode VDR 15V t CDR t R VIH - 02V VIH LOW V CC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode VDR 15V t CDR t R CE2 VIL CE2 02V VIL 5

6 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level /0V 5ns 05 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY AC TEST LOADS AND WAVEFORMS 50V OUTPUT INCLUDING JIG AND SCOPE 1928 Ω 100PF OUTPUT 1020 Ω FIGURE 1A 50V OUTPUT THEVENIN EQUIVALENT 667 Ω ALL INPUT PULSES INCLUDING JIG AND SCOPE 173V 1928 Ω 5PF 1020 Ω FIGURE 1B MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H, DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE OFF STATE GND 10% 90% 90% 10% 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70 o C, = 50V ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION -70 MIN TYP MAX -55 MIN TYP MAX t AVAX t RC Read Cycle Time ns t AVQV t AA Address Access Time ns t E1LQV t ACS1 Chip Select Access Time () ns t E2LQV t ACS2 Chip Select Access Time (CE2) ns t BA t BA Data Byte Control Access Time (LB,UB) ns t GLQV t OE Output Enable to Output Valid ns t ELQX t CLZ Chip Select to Output Low Z (, CE2) ns t BE t BE Data Byte Control to Output Low Z (LB,U B) ns t GLQX t OLZ Output Enable to Output in Low Z ns t EHQZ t CHZ Chip Deselect to Output in High Z (,CE2) ns t BDO t BDO Data Byte Control to Output High Z (LB, UB) ns t GHQZ t OHZ Output Disable to Output in High Z ns t AXOX t OH Output Disable to Address Change ns NOTE : 1 tba is 35ns/30ns (@speed=70ns/55ns) with address toggle tba is 70ns/55ns (@speed=70ns/55ns) without address toggle UNIT 6

7 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t OH t AA t OH D OUT READ CYCLE2 (1,3,4) CE2 t ACS2 t ACS1 t CLZ t CHZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t OE t OH CE2 t ACS2 t OLZ t ACS1 t CLZ t OHZ (1,5) t CHZ LB, UB t BE t BA t BDO D OUT NOTES: 1 WE is high in read Cycle 2 Device is continuously selected when = VIL and CE2 = VIH 3 Address valid prior to or coincident with transition low and CE2 transition high 4 OE = VIL 5 Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B The parameter is guaranteed but not 100% tested 7

8 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70 o C, = 50V ) WRITE CYCLE JEDEC PARAMETER NAME t AVAX PARAMETER NAME DESCRIPTION -70 MIN TYP MAX -55 MIN TYP MAX t WC Write Cycle Time ns t E1LWH t CW Chip Select to End of Write ns t AVWL t AS Address Setup Time ns t AVWH t AW Address Valid to End of Write ns t WLWH t WP Write Pulse Width ns t WHAX t WR Write recovery Time (CE2,,WE) ns t BW t BW Date Byte Control to End of Write (LB,U B) ns t WLQZ t WHZ Write to Output in High Z ns t DVWH t DW Data to Write Time Overlap ns t WHDX t DH Data Hold from Write Time ns t GHQZ t OHZ Output Disable to Output in High Z ns t WHOX t OW End of Write to Output Active ns NOTE : 1 tbw is 30ns/25ns (@speed=70ns/55ns) with address toggle ; tbw is 70ns/55ns (@speed=70ns/55ns) without address toggle SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) ADDRESS t WC (3) t WR UNIT OE CE2 (11) t CW LB,UB t BW WE t AS (4,10) t OHZ t AW t WP (2) (3) D OUT t DH t DW D IN 8

9 WRITE CYCLE2 (1,6) t WC ADDRESS CE2 (11) t CW LB,UB t BW WE t AS t AW (4,10) t WHZ t WP (2) t WR (3) t DH (7) (8) D OUT t DW t DH (8,9) D IN NOTES: 1 WE must be high during address transitions 2 The internal write time of the memory is defined by the overlap of CE2, and WE low All signals must be active to initiate a write and any one signal can terminate a write by going inactive The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write 3 TWR is measured from the earlier of CE2 going low, or or WE going high at the end of write cycle 4 During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied 5 If the CE2 high transition or low transition or LB,UB low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state 6 OE is continuously low (OE = VIL ) 7 DOUT is the same phase of write data of this write cycle 8 DOUT is the read data of next address 9 If CE2 is high or is low during this period, DQ pins are in the output state Then the data input signals of opposite phase to the outputs must not be applied to them 10 Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B The parameter is guaranteed but not 100% tested 11 TCW is measured from the later of CE2 going high or going low to the end of write 9

10 ORDERING INFORMATION X X -- Y Y SPEED 70: 70ns 55: 55ns GRADE C: +0 o C ~ +70 o C I: -40 o C ~ +85 o C PACKAGE A :BGA - 48 PIN(6x8mm) D :DICE PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS 14 Max BALL PITCH e = 075 D E N D1 E D1 E1 e VIEW A 48 mini-bga (6 x 8mm) 10

11 REVISION HISTORY Revision Description Date Note Data Sheet release Apr 15, Modify Standby Current (Typ and Max) 24 Modify some AC parameters Modify 5V ICCSB1_Max(I-grade) from 10uA to 25uA Jun 29, 2001 April,15,

Very Low Power/Voltage CMOS SRAM 1M X 16 bit DESCRIPTION. SPEED (ns) 55ns : 3.0~3.6V 70ns : 2.7~3.6V BLOCK DIAGRAM

Very Low Power/Voltage CMOS SRAM 1M X 16 bit (Dual CE Pins) FEATURES operation voltage : 27~36V Very low power consumption : = 30V C-grade: 45mA (@55ns) operating current I -grade: 46mA (@55ns) operating