EEPROM AS58LC K x 8 EEPROM Radiation Tolerant. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535

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1 128K x 8 EEPROM Radiation Tolerant AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF FEATURES High speed: 250ns and 300ns Data Retention: 10 Years Low power dissipation, active current (20mW/MHz (TYP)), standby current (100μW(MAX)) Single +3.3V +.3V power supply Data Polling and Ready/Busy Signals Erase/Write Endurance (10,000 cycles in a page mode) Software Data protection Algorithm Data Protection Circuitry during power on/off Hardware Data Protection with RES pin Automatic Programming: Automatic Page Write: 15ms (MAX) 128 Byte page size OPTIONS MARKINGS Timing 250ns access ns access -30 Packages Ceramic Flat Pack F No. 306 Radiation Shielded Ceramic FP* SF No. 305 Ceramic SOJ DCJ No. 508 Operating Temperature Ranges -Military (-55 o C to +125 o C) XT -Industrial (-40 o C to +85 o C) IT -Full Military Processing (-55 o C to +125 o C) 883C *NOTE: Package lid is connected to ground (Vss). 2-sided shielding provided via a Tungsten lid and a Tungsten slug on the underside of package. 6.5X typ. TID boost due to shielding. (Geostationary orbit) Proven typ. total dose 40K to 100K RADS. Contact factory for more information. Micross can perform TID lot testing. PIN ASSIGNMENT (Top View) 32-Pin CFP (F & SF), 32-Pin CSOJ (DCJ) RDY/BUSY\ A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 Vss GENERAL DESCRIPTION The is a 1 Megabit CMOS Electrically Erasable Programmable Read Only Memory (EEPROM) organized as 131, 072 x 8 bits. The is capable or in system electrical Byte and Page reprogrammability. The achieves high speed access, low power consumption, and a high level of reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology and CMOS process and circuitry technology. This device has a 128-Byte Page Programming function to make its erase and write operations faster. The features Data Polling and a Ready/Busy signal to indicate completion of erase and programming operations. This EEPROM provides several levels of data protection. Hardware data protection is provided with the RES pin, in addition to noise protection on the WE signal and write inhibit during power on and off. Software data protection is implemented using JEDEC Optional Standard algorithm. The is designed for high reliability in the most demanding applications. Data retention is specified for 10 years and erase/write endurance is guaranteed to a minimum of 10,000 cycles in the Page Mode Vcc A15 RES\ A13 A8 A9 A11 OE\ A10 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 For more products and information please visit our web site at 1

2 FUNCTIONAL BLOCK DIAGRAM Vcc I/O0 I/O7 Ready/Busy High Voltage Generator Vss OE\ I/O Buffer and Input Latch RES\ Control Logic and Timing A0 A6 Y Decoder Y Gating Buffer and Latch A7 A16 X Decoder Memory Array Data Latch MODE SELECTION MODE OE\ RES\ RDY/BUSY\ 1 I/O READ V IL V IL V IH V H High-Z D OUT STANDBY V IH X X X High-Z High-Z WRITE V IL V IH V IL V H High-Z to V OL D IN DESELECT V IL V IH V IH V H High-Z High-Z WRITE INHIBIT X X V IH X X V IL X X DATA Data Out POLLING V IL V IL V IH V H V OL (I/O7) PROGRAM X X X V IL High-Z High-Z 2

3 FUNCTIONAL DESCRIPTION AUTOMATIC PAGE WRITE The Page Write feature allows 1 to 128 Bytes of data to be written into the EEPROM in a single cycle and allows the undefined data within 128 Bytes to be written corresponding to the undefined address (A 0 to A 6 ). Loading the first Byte of data, the data load window of 30μs opens for the second. In the same manner each additional Byte of data can be loaded within 30μs. In case and are kept high for 100μs after data input, the EEPROM enters erase and write automatically and only the input data can be written into the EEPROM. In Page mode the data can be written and accessed 10 4 times per page, and in Byte mode 10 3 times per Byte. DATA PROTECTION To protect the data during operation and power on/off, the AS58C1001 has: 1. Data protection against Noise on Control Pins (, OE\, ) during Operation. During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, the has a noise cancellation function that cuts noise if its width is 20ns or less in programming mode. Be careful not to allow noise of a width of more than 20ns on the control pins. DATA\ POLLING Data\ Polling allows the status of the EEPROM to be determined. If the EEPROM is set to Read mode during a Write cycle, and inversion of the last Byte of data to be loaded outputs from I/O, to indicate that the EEPROM is performing a Write operation. WRITE PROTECTION (1) Noise protection: Noise on a write cycle will not act as a trigger with a pulse of less than 20ns. (2) Write inhibit: Holding OE\ low, high or high inhibits a write cycle during power on/off. AND PIN OPERATION During a write cycle, addresses are latched by the falling edge of or, and data is latched by the rising edge of or. WRITE/ERASE ENDURANCE AND DATA RETENTION The endurance with page programming is 10 4 cycles (1% cumulative failure rate) and the data retention time is more than 10 years when a device is programmed less than 10 4 cycles. 3

4 (EXAMPLE) Vcc RES\ *unprogrammable *unprogrammable FUNCTIONAL DESCRIPTION (continued) DATA PROTECTION (continued) 2. Data protection at Vcc on/off. When RES\ is low, the EEPROM cannot be erased and programmed. Therefore, data can be protected by keeping RES\ low when Vcc is switched. RES\ should be high during programming because it does not provide a latch function. When Vcc is turned on or off, noise on the control pins generated by external circuits (CPU, etc.) may turn the EEPROM to programming mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable, standby or readout state by using a CPU reset signal to RES\ pin. In addition, when RES\ is kept high at Vcc on/off timing, the input level of control pins (, OE\, ) must be held as =Vcc or OE\=LOW or =Vcc level. 3. Software Data Protection To protect against unintentional programming caused by noise generated by external circuits, has a Software data protection function. To initate Software data protection mode, 3 bytes of data must be input, followed by a dummy write cycle of any address and any data byte. This exact sequence switches the device into protection mode. Write The Software data protection mode can be cancelled by inputting the following 6 Bytes. This changes the to the Non-Protection mode, for normal operation. Data 5555 AA 2AAA AA Write Data (Normal Data Input) 5555 AA 2AAA A0 2AAA

5 ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss V to +7.0V 1 Voltage on any pin Relative to Vss V to +7.0V 1 Storage Temperature C to +150 C Operating Temperature Range o C to +125 o C Soldering Temperature Range o C Maximum Junction Temperature** C Power Dissipation...1.0W *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55 o C < T A < 125 o C; Vcc = 3.3V +.3V) PARAMETER CONDITION SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage V IH 2.2 V CC + 0.3V V 9 Input Low (Logic 0) Voltage 3 V IL V 2 Input Voltage (RES\ Pin) V H Vcc-0.5 V CC +0.3 V Input Leakage Current 4 OV < V IN < Vcc I LI -2 2 μ 4 Input Leakage (RES\ Pin) RES\ = Vcc = 3.6V I LI μ Output Leakage Current Output(s) disabled, OV < V OUT < Vcc I LO -2 2 μ Output High Voltage I OH = -400 μa V OH 2.4 V Output Low Voltage I OL = 2.1 ma V OL 0.5 V PARAMETER MAX CONDITIONS SYM UNITS NOTES Power Supply Current: Operating I OUT =OmA, Vcc = 3.6V Cycle=1μS, Duty=100% I OUT =OmA, Vcc = 3.6V Cycle=MIN, Duty=100% I CC ma Power Supply Current: Standby =Vcc, Vcc = 3.6V I CC μa =V IH, Vcc = 3.6V I CC ma CAPACITANCE PARAMETER CONDITIONS SYMBOL MAX UNITS NOTES Input Capacitance T A = 25 o C, f = 1MHz C IN 6 pf Output Capactiance V IN = 0 Co 12 pf 5

6 AC ELECTRICAL CHARACTERISTICS FOR READ OPERATION (-55 o C < T C < 125 o C; Vcc = +3.3V +/- 0.3V) Test Conditions Input Pulse Levels: 0.0V to 3.0V Input rise and fall times: < 20ns Output Load: 1 TTL Gate +100pF (including scope and jig) Reference levels for measuring timing: 1.5V, 1.5V ITEM DESCRIPTION TEST CONDITION SYMBOL MIN MAX MIN MAX UNITS Access Time =OE\=V IL =V IH t ACC ns Chip Enable Access Time OE\=V IL =V IH t CE ns Output Enable Acess Time =V IL =V IH t OE ns Output Hold to Change =OE\=V IL =V IH t OH ns Output Disable to High-Z =V IL =V IH t DF ns =OE\=V IL =V IH t DFR ns RES\ to Output Delay =OE\=V IL =V IH t RR ns AC ELECTRICAL CHARACTERISTICS FOR SOFTWARE DATA PROTECTION CYCLE OPERATION PARAMETER Byte Load Cycle Time Write Cycle Time SYMBOL MIN MAX UNITS t BLC S t WC ms AC ELECTRICAL CHARACTERISTICS FOR DATA\ POLLING OPERATION PARAMETER Output Enable Hold Time Output Enable to Write Setup Time Write Start Time Write Cycle Time SYMBOL MIN MAX UNITS t OEH ns t OES ns t DW ns t WC ms 6

7 AC ELECTRICAL CHARACTERISTICS FOR PAGE ERASE AND PAGE WRITE OPERATIONS PARAMETER Setup Time Write Enable to Write Setup Time Chip Enable to Write Setup Time Write Pulse Width Hold Time Data Setup Time Data Hold Time Write Enable Hold Time Chip Enable Hold Time Out Enable to Write Setup Time Output Enable Hold Time Data Latch Time Write Cycle Time Byte Load Window Byte Load Cycle Time to Device Busy RES\ to Write Setup Time Vcc to RES\ Setup Time SYMBOL MIN MAX UNITS t AS ns 8 t WS 7 t CS 7 t WP 8 t CW ns ns ns ns t AH ns t DS ns t DH ns 8 t WH 7 t CH ns ns t OES ns t OEH ns t DL ns t WC ms t BL s t BLC 1 30 s t DB ns t RP s t RES s 7

8 AC ELECTRICAL CHARACTERISTICS FOR BYTE ERASE AND BYTE WRITE OPERATIONS PARAMETER Setup Time Chip Enable to Write Setup Time Write Pulse Width Hold Time Data Setup Time Data Hold Time Chip Enable Hold Time Out Enable to Write Setup Time Output Enable Hold Time Write Cycle Time Byte Load Window Time to Device Busy RES\ to Write Setup Time Vcc to RES\ Setup Time SYMBOL MIN MAX UNITS t AS ns 7 t CS 8 t CW 7 t WP ns ns ns t AH ns t DS ns t DH ns t CH ns t OES ns t OEH ns t WC ms t BL μs t DB ns t RP μs t RES μs AC TEST CONDITIONS Input Pulse Levels...0V to 3V Input Rise and Fall Times...<20ns Input Timing Reference Level...1.5V Output Reference Level...1.5V Output Load...See Figure 1 Q 100pF 1 TTL GATE EQ. NOTES: 1. Relative to Vss 2. V IN min = -3.0V for pulse widths <50ns 3. V IL min = -1.0V for pulse widths <50ns 4. I IL on RES\ = 100ua MAX 5. t OF is defined as the time at which E the output becomes and open circuit and data is no longer driven. 6. Use this device in longer cycle than this value 7. controlled operation 8. controlled operation 9. RES\ pin V IH is V H 10. Reference only, not tested Figure 1 OUTPUT LOAD EQUIVALENT 8

9 READ TIMING WAVEFORM OE\ t ACC t CE t OH High-Z t OE t DF t RR Data Out Data Out Valid RES\ t DFR SOFTWARE DATA PROTECTION TIMING WAVEFORM (protection mode) Vcc t BLC t WC Data 5555 AA AAAA or 2AAA A0 { Write Write Data SOFTWARE DATA PROTECTION TIMING WAVEFORM (non-protection mode) Vcc t WC Normal active mode Data 5555 AA AAAA or 2AAA AA AAAA or 2AAA

10 DATA\ POLLING TIMING WAVEFORM An An t CE t OES OE\ t DW I/O7 D IN X t OE D OUT D OUT X t WC TOGGLE BIT WAVEFORM Next Mode t CE OE\ t OE t OES D IN I/O7 D OUT D OUT D OUT D OUT t WC t DW In transition from HI to LOW or LOW to HI. 10

11 PAGE WRITE TIMING WAVEFORM ( CONTROLLED) A7 - A16 A0 - A6 t AS t AH t WP tdl t BL t CS t CH t BLC t WC OE\ t OES t DH t DS D IN RDY/Busy\ High-Z t DB t DW High-Z t RP t RES V CC In transition from HI to LOW or LOW to HI. 11

12 PAGE WRITE TIMING WAVEFORM ( CONTROLLED) A0 to A16 t AS t AH t CW t DL t BL t WS t WH t BLC t WC OE\ t OES t DH t DS D IN RDY/Busy\ High-Z t DB t DW High-Z t RP t RES V CC In transition from HI to LOW or LOW to HI. 12

13 BYTE WRITE TIMING WAVEFORM ( CONTROLLED) t WC t CS t AH t CH t AS t WP t BL t OES t OEH OE\ t DS t DH D IN RDY/Busy\ High-Z t DB t DW High-Z t RP t RES V CC In transition from HI to LOW or LOW to HI. 13

14 BYTE WRITE TIMING WAVEFORM ( CONTROLLED) t WS t AH t BL t WC t CW t AS t WH OE\ t OES t OEH t DS t DH D IN RDY/Busy\ High-Z t DB t DW High-Z t RP t RES V CC In transition from HI to LOW or LOW to HI. 14

15 MECHANICAL DEFINITIONS* Micross Case #305 (Package Designator SF) L E e b D H Top View c E1 Q A A1 D2 D1 *All measurements are in inches. SMD SPECIFICATIONS SYMBOL MIN MAX A A b c D D D E E e H L Q

16 MECHANICAL DEFINITIONS* Micross Case #306 (Package Designator F) L E e b D H Top View A1 D2 c E1 Q A SMD SPECIFICATIONS SYMBOL MIN MAX A A b c D D E E e H L Q NOTE: All drawings are per the SMD. Micross package dimensional limits may differ, but they will be within the SMD limits. *All measurements are in inches. 16

17 MECHANICAL DEFINITIONS* Micross Case #508 (Package Designator DCJ) A A1 e D1 D b B E2 E1 A2 E MICROSS PACKAGE SPECIFICATIONS SYMBOL MIN MAX A A A B b D D E E E e *All measurements are in inches. 17

18 ORDERING INFORMATION EXAMPLE: SF-15/IT EXAMPLE: F-25/883C Device Number Package Type Speed ns Process Device Number Package Type Speed ns Process SF -25 /* F -25 /* SF -30 /* F -30 /* EXAMPLE: DCJ-20/IT Device Number Package Speed Type ns Process DCJ -25 /* DCJ -30 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing -40 o C to +85 o C -55 o C to +125 o C -55 o C to +125 o C 18

19 DOCUMENT TITLE 128K x 8 EEPROM Radiation Tolerant Rev # History Release Date Status 1.0 Removed ECA Package December 2008 Release 1.1 Updated AC ELECTRICAL October 2009 Release CHARACTERISTICS on page 6 to reference 3.3V 1.5 removed SOP Package (DG) November 2009 Release 1.6 removed 5962 references November 2009 Release 1.7 Updated Micross Information January 2010 Release 1.8 Updated Military Specifi cations, added November 2010 Release Full Military Processing temp range and updated note on page 1 19

EEPROM AS8ER128K32 FUNCTIONAL BLOCK DIAGRAM. 128K x 32 Radiation Tolerant EEPROM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS

EEPROM AS8ER128K32 FUNCTIONAL BLOCK DIAGRAM. 128K x 32 Radiation Tolerant EEPROM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS 128K x 32 Radiation Tolerant EEPROM AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38534 FEATURES Access time of 150ns, 200ns, 250ns Operation with single 5V + 10% supply Power Dissipation: Active: 1.43