8K x 8 Power-Switched and Reprogrammable PROM
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1 8K x 8 Power-Switched and Reprogrammable PROM Features CMOS for optimum speed/power Windowed for reprogrammability High speed 20 ns (commercial) 25 ns (military) Low power 660 mw (commercial) 770 mw (military) Super low standby power (7C261) Less than 220 mw when deselected Fast access: 20 ns EPROM technology 100% programmable Slim 300-mil or standard 600-mil packaging available 5V ± 10% V CC, commercial and military Capable of withstanding greater than 2001V static discharge TTL-compatible I/O Direct replacement for bipolar PROMs Functional Description The CY7C261, CY7C263, and CY7C264 are high-performance 8192-word by 8-bit CMOS PROMs. When deselected, the 7C261 automatically powers down into a low-power standby mode. It is packaged in a 300-mil-wide package. The 7C263 and 7C264 are packaged in 300-mil-wide and 600-mil-wide packages respectively, and do not power down when deselected. The reprogrammable packages are equipped with an erasure window; when exposed to UV light, these PROMs are erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. The CY7C261, CY7C263, and CY7C264 are plug-in replacements for bipolar devices and offer the advantages of lower power, superior performance and programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming the product will meet DC and AC specification limits. Read is accomplished by placing an active LOW signal on CS. The contents of the memory location addressed by the address line (A 0 A 12 ) will become available on the output lines (O 0 O 7 ). Logic Block Diagram Pin Configurations A 0 O 7 A 1 DIP/Flatpack A 2 PROGRAM COLUMN Top View ROW MABLE MULTI A 3 O ADDRESS 6 ARRAY PLEXER A V CC Top View A 4 A A 8 A 5 O 5 A A 9 A 6 A 4 21 A ADDRESS A CS A 5 25 A 4 10 A 7 DECODER O 4 A A A CS A 2 7 7C A 11 A 8 A A 12 A A 7C A 9 O A 0 8 7C O 7 A NC 7C263 O O 6 NC O 7 7C264 A 10 O O O O 6 COLUMN A 11 ADDRESS O 2 O O 4 A 12 GND O 3 O 1 C261-2 C261-3 POWER DOWN (7C261) O 0 LCC/PLCC (Opaque Only) A5 A6 A7 NC V CC A8 A9 O 1 O 2 GND NC O 3 O 4 O 5 CS C261-1 For an 8K x 8 Registered PROM, see thecy7c265. Cypress Semiconductor Corporation 3901 North First Street San Jose CA March 1986 Revised December 1994
2 Selection Guide Maximum Ratings 7C C C C C C C C C CY7C261 7C C C C C C Maximum Access Time (ns) Maximum Operating Commercial Current (ma) Military Maximum Standby Commercial Current (ma) (7C261 only) Military (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperaturesy C to+150 C Ambient Temperature with Power Applied C to+125 C Supply Voltage to Ground Potential (Pin 24 to Pin 12) V to+7.0v DC Voltage Applied to Outputs in High Z State V to+7.0v DC Input Voltage V to + 7.0V DC Program Voltage (Pin 19 DIP, Pin 23 LCC) V Static Discharge Voltage...>2001V (per MIL-STD-883, Method 3015) Latch-Up Current... >200 ma UV Exposure Wsec/cm 2 Operating Range Ambient Range Temperature V CC Commercial 0 C to + 70 C 5V ± 10% Industrial [1] 40 C to + 85 C 5V ± 10% Military [2] 55 C to C 5V ± 10% Notes: 1. See the Ordering Information section regarding industrial teperature range specifcation. 2. T A is the instant on case temperature. 2
3 ]] Electrical Characteristics Over the Operating Range [3,4] 7C261-20, 25 7C263-20, 25 7C264-20, 25 7C261-35, 45, 55 7C263-35, 45, 55 7C264-35, 45, 55 Parameter Description Test Conditions Min. Max. Min. Max. Unit V OH Output HIGH Voltage V CC = Min., I OH = 2.0 ma 2.4 V V OH Output HIGH Voltage V CC = Min., I OH = 4.0 ma 2.4 V V OL Output LOW Voltage V CC = Min., I OL = 8 ma 0.4 V (6 ma Mil) V OL Output LOW Voltage V CC = Min., I OL = 16 ma 0.4 V V IH Input HIGH Level V V IL Input LOW Level V I IX Input Current GND < V IN < V CC µa V CD Input Diode Clamp Voltage Note 4 Note 4 I OZ Output Leakage Current GND <V OUT < V CC Com l µa Output Disabled Mil µa I OS Output Short Circuit Current [5] V CC = Max., V OUT = GND ma I CC Power Supply Current V CC = Max., Com l ma f = Max. I OUT = 0 ma Mil I SB Standby Supply Current (7C261) V CC = Max., Com l ma CS > V IH Mil V PP Programming Supply Voltage V I PP Programming Supply Current ma V IHP Input HIGH Programming Voltage V V ILP Input LOW Programming Voltage V Notes: 3. See the last page of this specification for Group A subgroup testing information. 4. See the Introduction to CMOS PROMs section of the Cypress Data Book for general information on testing. 5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.] Capacitance [4] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 10 pf C OUT Output Capacitance V CC = 5.0V 10 pf 3
4 AC Test Loads and Waveforms [4] Test Load for 20 through 30 speeds 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE R1 500 (658Ω MIL) (a) Normal Load R2 333Ω (403Ω MIL) 5V OUTPUT 5pF INCLUDING JIG AND SCOPE R1 500Ω (658Ω MIL) (b) HighZ Load R2 333Ω (403Ω MIL) C V GND 5ns 90% 10% 90% 10% 5 ns C261-5 Equivalent to: THÉVENIN EQUIVALENT R TH 200Ω (250Ω MIL) OUTPUT 2.0V(1.9VMIL) Test Load for 35 through 55 speeds R1250 Ω 5V 5V OUTPUT OUTPUT R1 250Ω 30pF R2167 Ω 5pF R2167 Ω INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE (c) Normal Load (d) HighZ Load C261-6 Equivalent to: THÉ VENIN EQUIVALENT R TH 100Ω OUTPUT 2.0V Switching Characteristics Over the Operating Range [2,3,4 ] 7C C C C C C C C C C C C C C C Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit t AA Address to Output Valid ns t HZCS1 Chip Select Inactive to High Z ns (7C263 and 7C264) t HZCS2 Chip Select Inactive to High Z ns (7C261) t ACS1 Chip Select Active to Output Valid ns (7C263 and 7C264) t ACS2 Chip Select Active to Output Valid ns (7C261) t PU Chip Select Active to Power-Up ns (7C261) t PD Chip Select Inactive to Power-Down (7C261) ns 4
5 Switching Waveforms [4] V CC SUPPLY CURRENT t PD t PU 50% 50% A 0 - A 12 ADDRESS CS t AA t HZCS t ACS O 0 - O 7 C261-7 Erasure Characteristics Wavelengths of light less than 4000 angstroms begin to erase the devices in the windowed package. For this reason, an opaque label should be placed over the window if the PROM is exposed to sunlight or fluorescent lighting for extended periods of time. The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mw/cm 2 power rating, the exposure time wouldbe approximately 35 minutes. The 7C261 or 7C263 needs to be within 1 inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended period of time Wsec/cm 2 is the recommended maximum dosage. Operating Modes Read Read is the normal operating mode for programmed device. In this mode, all signals are normal TTL levels. The PROM is addressed with a 13-bit field, a chip select, (active LOW), is applied to the CS pin, and the contents of the addressed location appear on the data out pins. Program, Program Inhibit, Program Verify These modes are entered by placing a high voltage V PP on pin 19, with pins 18 and 20 set to V ILP. In this state, pin 21 becomes a latch signal, allowing the upper 5 address bits to be latched into an onboard register, pin 22 becomes an active LOW program (PGM) signal and pin 23 becomes an active LOW verify (VFY) signal. Pins 22 and 23 should never be active LOW at the same time. The PRO- GRAM mode exists when PGM is LOW, and VFY is HIGH. The verify mode exists when the reverse is true, PGM HIGH and VFY LOW and the program inhibit mode is entered with both PGM and VFY HIGH. Program inhibit is specifically provided to allow data to be placed on and removed from the data pins without conflict Table 1. Mode Selection [6, 7] Pin Function Read or Output Disable A 12 A 11 A 10 A 9 A 8 CS O 7 - O 0 Mode Program NA V PP LATCH PGM VFY CS D 7 - D 0 Read A 12 A 11 A 10 A 9 A 8 V IL O 7 - O 0 Output Disable A 12 A 11 A 10 A 9 A 8 V IH High Z Program V ILP V PP V ILP V ILP V IHP V ILP D 7 - D 0 Program Inhibit V ILP V PP V ILP V IHP V IHP V ILP High Z Program Verify V ILP V PP V ILP V IHP V ILP V ILP O 7 - O 0 Blank Check V ILP V PP V ILP V IHP V ILP V ILP O 7 - O 0 Notes: 6. X = don t care but not to exceed V CC ±5%. 7. Addresses A 8 -A 12 must be latched through lines A 0 -A 4 in programming modes. 5
6 DIP/Flatpack Top View LCC/PLCC (Opaque only) Top View A 7 A 6 A 5 A 4 /A 12 A 3 /A 11 A 2 /A 10 A 1 /A 9 A 0 /A 8 D 0 D 1 D C C C GND V CC VFY PGM LATCH CS V PP NA D 7 D 6 D 5 D 4 D 3 A5 A 6 A7 NC V CC A 4 /A A 3 /A A 7C261 2 /A A 1 /A A 0 /A NC 10 7C D D 1 D 2 GND VFY PGM NC D 3 D 4 D 5 LATCH CS V PP NA NC D 7 D 6 C261-9 C261-8 Programming Information Figure 1. Programming Pinouts. Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. 6
7 Typical DC and AC Characteristics NORMALIZED I CC NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = 25 C f= f MAX SUPPLY VOLTAGE(V) NORMALIZED I CC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE( C) ACCESS TIME NORMALIZED NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE T A = 25 C SUPPLY VOLTAGE(V) NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME vs. TEMPERATURE AMBIENT TEMPERATURE( C) OUTPUT SOURCE CURRENT (ma) OUTPUT SOURCE CURRENT vs. VOLTAGE OUTPUT VOLTAGE(V) DELTA t AA (ns) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING V CC = 4.5V T A = 25 C CAPACITANCE(pF) OUTPUT SINK CURRENT (ma) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE V CC = 5.0V 50 T A = 25 C OUTPUT VOLTAGE(V) 4.0 NORMALIZED I CC NORMALIZED SUPPLY CURRENT vs. CYCLE PERIOD V CC = 5.5V T A = 25 C CYCLE PERIOD(ns) 7
8 ] Ordering Information [8] Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C261-20JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C261-20PC P13 24-Lead (300-Mil) Molded DIP CY7C261-20WC W14 24-Lead (300-Mil) Windowed CerDIP 25 CY7C261-25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C261-25PC P13 24-Lead (300-Mil) Molded DIP CY7C261-25WC W14 24-Lead (300-Mil) Windowed CerDIP CY7C261-25DMB D14 24-Lead (300-Mil) CerDIP Military CY7C261-25LMB L64 28-Square Leadless Chip Carrier CY7C261-25QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C261-25TMB T73 24-Lead Windowed Cerpack CY7C261-25WMB W14 24-Lead (300-Mil) Windowed CerDIP 35 CY7C261-35JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C261-35PC P13 24-Lead (300-Mil) Molded DIP CY7C261-35WC W14 24-Lead (300-Mil) Windowed CerDIP CY7C261-35DMB D14 24-Lead (300-Mil) CerDIP Military CY7C261-35LMB L64 28-Square Leadless Chip Carrier CY7C261-35QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C261-35TMB T73 24-Lead Windowed Cerpack CY7C261-35WMB W14 24-Lead (300-Mil) Windowed CerDIP 45 CY7C261-45JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C261-45PC P13 24-Lead (300-Mil) Molded DIP CY7C261-45WC W14 24-Lead (300-Mil) Windowed CerDIP CY7C261-45DMB D14 24-Lead (300-Mil) CerDIP Military CY7C261-45LMB L64 28-Square Leadless Chip Carrier CY7C261-45QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C261-45TMB T73 24-Lead Windowed Cerpack CY7C261-45WMB W14 24-Lead (300-Mil) Windowed CerDIP 55 CY7C261-55JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C261-55PC P13 24-Lead (300-Mil) Molded DIP CY7C261-55WC W14 24-Lead (300-Mil) Windowed CerDIP CY7C261-55DMB D14 24-Lead (300-Mil) CerDIP Military CY7C261-55LMB L64 28-Square Leadless Chip Carrier CY7C261-55QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C261-55TMB T73 24-Lead Windowed Cerpack CY7C261-55WMB W14 24-Lead (300-Mil) Windowed CerDIP Note: 8. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product availability. 8
9 Ordering Information [8] (continued) Speed Package Operating (ns) Ordering Code Name Package Type Range 20 CY7C263-20JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C263-20PC P13 24-Lead (300-Mil) Molded DIP CY7C263-20WC W14 24-Lead (300-Mil) Windowed CerDIP 25 CY7C263-25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C263-25PC P13 24-Lead (300-Mil) Molded DIP CY7C263-25WC W14 24-Lead (300-Mil) Windowed CerDIP CY7C263-25DMB D14 24-Lead (300-Mil) CerDIP Military CY7C263-25LMB L64 28-Square Leadless Chip Carrier CY7C263-25QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C263-25TMB T73 24-Lead Windowed Cerpack CY7C263-25WMB W14 24-Lead (300-Mil) Windowed CerDIP 35 CY7C263-35JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C263-35PC P13 24-Lead (300-Mil) Molded DIP CY7C263-35WC W14 24-Lead (300-Mil) Windowed CerDIP CY7C263-35DMB D14 24-Lead (300-Mil) CerDIP Military CY7C263-35LMB L64 28-Square Leadless Chip Carrier CY7C263-35QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C263-35TMB T73 24-Lead Windowed Cerpack CY7C263-35WMB W14 24-Lead (300-Mil) Windowed CerDIP 45 CY7C263-45JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C263-45PC P13 24-Lead (300-Mil) Molded DIP CY7C263-45WC W14 24-Lead (300-Mil) Windowed CerDIP CY7C263-45DMB D14 24-Lead (300-Mil) CerDIP Military CY7C263-45LMB L64 28-Square Leadless Chip Carrier CY7C263-45QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C263-45TMB T73 24-Lead Windowed Cerpack CY7C263-45WMB W14 24-Lead (300-Mil) Windowed CerDIP 55 CY7C263-55JC J64 28-Lead Plastic Leaded Chip Carrier Commercial CY7C263-55PC P13 24-Lead (300-Mil) Molded DIP CY7C263-55WC W14 24-Lead (300-Mil) Windowed CerDIP CY7C263-55DMB D14 24-Lead (300-Mil) CerDIP Military CY7C263-55LMB L64 28-Square Leadless Chip Carrier CY7C263-55QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C263-55TMB T73 24-Lead Windowed Cerpack CY7C263-55WMB W14 24-Lead (300-Mil) Windowed CerDIP 9
10 Ordering Information [8] (continued) Speed (ns) Ordering Code Package Name Package Type Operating Range 20 CY7C264-20DC D12 24-Lead (600-Mil) CerDIP Commercial CY7C264-20PC P11 24-Lead (600-Mil) Molded DIP CY7C264-20WC W12 24-Lead (600-Mil) Windowed CerDIP 25 CY7C264-25DC D12 24-Lead (600-Mil) CerDIP Commercial CY7C264-25PC P11 24-Lead (600-Mil) Molded DIP CY7C264-25WC W12 24-Lead (600-Mil) Windowed CerDIP CY7C264-25DMB D12 24-Lead (600-Mil) CerDIP Military CY7C264-25WMB W12 24-Lead (600-Mil) Windowed CerDIP 35 CY7C264-35DC D12 24-Lead (600-Mil) CerDIP Commercial CY7C264-35PC P11 24-Lead (600-Mil) Molded DIP CY7C264-35WC W12 24-Lead (600-Mil) Windowed CerDIP CY7C264-35DMB D12 24-Lead (600-Mil) CerDIP Military CY7C264-35WMB W12 24-Lead (600-Mil) Windowed CerDIP 45 CY7C264-45DC D12 24-Lead (600-Mil) CerDIP Commercial CY7C264-45PC P11 24-Lead (600-Mil) Molded DIP CY7C264-45WC W12 24-Lead (600-Mil) Windowed CerDIP CY7C264-45DMB D12 24-Lead (600-Mil) CerDIP Military CY7C264-45WMB W12 24-Lead (600-Mil) Windowed CerDIP 55 CY7C264-55DC D12 24-Lead (600-Mil) CerDIP Commercial CY7C264-55PC P11 24-Lead (600-Mil) Molded DIP CY7C264-55WC W12 24-Lead (600-Mil) Windowed CerDIP CY7C264-55DMB D12 24-Lead (600-Mil) CerDIP Military CY7C264-55WMB W12 24-Lead (600-Mil) Windowed CerDIP MILITARY SPECIFICATION Group A Subgroup Testing DC Characteristics Parameter Subgroups V OH 1, 2, 3 V OL 1, 2, 3 V IH 1, 2, 3 V IL 1, 2, 3 I IX 1, 2, 3 I OZ 1, 2, 3 I CC 1, 2, 3 [9] I SB 1, 2, 3 Switching Characteristics Parameter Subgroups t AA 7, 8, 9, 10, 11 [10] t ACS1 7, 8, 9, 10, 11 [9] t ACS2 7, 8, 9, 10, 11 Notes: 9. 7C261 only C263 and 7C264 only. Document #: J 10
11 Package Diagrams 24-Lead (600-Mil) CerDIP D12 MIL-STD-1835 D-3 Config. A 28-Lead Plastic Leaded Chip Carrier J64 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D-9 Config. A 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 11
12 Package Diagrams (continued) 28-Pin Windowed Leadless ChipCarrier Q64 MIL-STD-1835 C-4 24-Lead (600-Mil) Molded DIP P11 12
13 Package Diagrams (continued) 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead Windowed Cerpack T73 13
14 Package Diagrams (continued) 24-Lead (600-Mil) WindowedCerDIP W12 MIL-STD-1835 D- 3 Config.A 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D- 9 Config.A ) Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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FINAL Am27C040 4 Megabit (524,288 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS Fast access time 90 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved pinout Plug in upgrade
27C Bit ( x 8) UV Erasable CMOS PROM Military Qualified
27C256 262 144-Bit (32 768 x 8) UV Erasable CMOS PROM Military Qualified General Description The 27C256 is a high-speed 256K UV erasable and electrically reprogrammable CMOS EPROM ideally suited for applications
1 Mbit (128K x 8) Static RAM
1 Mbit (128K x 8) Static RAM Features Temperature Ranges Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Pin and Function compatible with CY7C1019BV33 High Speed t AA = 10 ns CMOS for optimum Speed
P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM
ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 1/1/15//5 (Commercial) 15//5/35 (Military) Low Power Operation 715 mw Active 1 (Commercial)
64-Macrocell MAX EPLD
43B CY7C343B Features 64 MAX macrocells in 4 LABs 8 dedicated inputs, 24 bidirectional pins Programmable interconnect array Advanced 0.65-micron CMOS technology to increase performance Available in 44-pin
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
241/42 fax id: 549 CY7C4421/421/4211/4221 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features High-speed, low-power, first-in, first-out (FIFO) memories 64 x 9 (CY7C4421) 256 x 9 (CY7C421) 512 x 9 (CY7C4211)
256K (32K x 8) Static RAM
256K (32K x 8) Static RAM Features Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Automotive-E: 40 C to 125 C Speed: 70 ns Low Voltage Range: 2.7V to 3.6V
256/512/1K/2K/4K x 9 Asynchronous FIFO
256/512/1K/2K/4K x 9 Asynchronous FIFO CY7C419/21/25/29/33 256/512/1K/2K/4K x 9 Asynchronous FIFO Features Asynchronous first-in first-out (FIFO) buffer memories 256 x 9 (CY7C419) 512 x 9 (CY7C421) 1K
NMC27C32B Bit (4096 x 8) CMOS EPROM
NMC27C32B 32 768-Bit (4096 x 8) CMOS EPROM General Description The NMC27C32B is a 32k UV erasable and electrically reprogrammable CMOS EPROM ideally suited for applications where fast turnaround pattern
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM
NMC27C64 65,536-Bit (8192 x 8) CMOS EPROM General Description The NMC27C64 is a 64K UV erasable, electrically reprogrammable and one-time programmable (OTP) CMOS EPROM ideally suited for applications where
Flash-erasable Reprogrammable CMOS PAL Device
PALCE22V1 is a replacement device for PALC22V1, PALC22V1B, and PALC22V1D. UE ULTRA37 TM FOR ALL NEW DEGN PALCE22V1 Features Low power 9 ma max. commercial (1 ns) 13 ma max. commercial (5 ns) CMO Flash
5V 128K X 8 HIGH SPEED CMOS SRAM
5V 128K X 8 HIGH SPEED CMOS SRAM Revision History AS7C1024B Revision Details Date Rev 1.0 Preliminary datasheet prior to 2004 Rev 1.1 Die Revision A to B March 2004 Rev 2.0 PCN issued yield issues with
P4C1257/P4C1257L. ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES DESCRIPTION. Full CMOS. Separate Data I/O
P4C1257/P4C1257L ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES Full CMOS High Speed (Equal Access and Cycle s) 12/15/20/25 ns (Commercial) 12/15/20/25 ns (Industrial) 25/35/45/55/70 ns (Military)
SOIC (SOP) NC A8 A9 A10 A11 A12 A13 A14 A15 A16 NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 BYTE/VPP GND O15/A-1 GND O7 O14 O6 O13 O5 O12 O4 VCC
Features Read Access Time - 100 ns Word-wide or Byte-wide Configurable 8-Megabit Flash and Mask ROM Compatable Low Power CMOS Operation -100 µa Maximum Standby - 50 ma Maximum Active at 5 MHz Wide Selection
1K x 8 Dual-Port Static RAM
Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power High-speed access: 15 ns ow operating power:
NM27C ,288-Bit (64K x 8) High Performance CMOS EPROM
NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM General Description The NM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM). It is manufactured
P4C1299/P4C1299L. ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM FEATURES DESCRIPTION. Full CMOS, 6T Cell. Data Retention with 2.0V Supply (P4C1299L)
FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 15/20/25/35 ns (Commercial/Industrial) 15/20/25/35/45 ns (Military) Low Power Operation Single 5V±10% Power Supply Output Enable (OE)
P4C1256L LOW POWER 32K X 8 STATIC CMOS RAM FEATURES DESCRIPTION V CC. Current (Commercial/Industrial) Operating: 70mA/85mA CMOS Standby: 100µA/100µA
FEATURES Current (Commercial/Industrial) Operating: 70mA/85mA CMOS Standby: 100µA/100µA Access Times 55/70/85 Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O
CY Features. Logic Block Diagram
Features Temperature Ranges -Commercial:0 to 70 -Industrial: -40 to 85 -Automotive: -40 to 125 High speed: 55ns and 70 ns Voltage range : 4.5V 5.5V operation Low active power (70ns, LL version, Com l and
General Purpose Clock Synthesizer
1CY 290 7 fax id: 3521 CY2907 General Purpose Clock Synthesizer Features Highly configurable single PLL clock synthesizer provides all clocking requirements for numerous applications Compatible with all
NM27P Bit (256k x 8) POP Processor Oriented CMOS EPROM
NM27P020 2 097 152-Bit (256k x 8) POPTM Processor Oriented CMOS EPROM General Description The NM27P020 is a 2 Mbit POP EPROM configured as 256k x 8 It s designed to simplify microprocessor interfacing
FM27C ,144-Bit (32K x 8) High Performance CMOS EPROM
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM General Description The FM27C256 is a 256K Electrically Programmable Read Only Memory. It is manufactured in Fairchild s latest CMOS split gate
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM General Description The NM27C010 is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory. It is organized
NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM General Description The NM27C040 is a high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory. It is organized
Features All output pair skew 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421/421/4211/4221 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Features CY7C4421/421/4211/4221 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs High-speed, low-power, First-In, First-Out (FIFO) memories
256K (32K x 8) Paged Parallel EEPROM AT28C256
Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT29BV040A
Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Software Protected Programming Fast Read Access Time 200 ns Low Power Dissipation 15 ma Active Current 50 µa CMOS Standby
NTE27C D Integrated Circuit 2 Mbit (256Kb x 8) UV EPROM
NTE27C2001 12D Integrated Circuit 2 Mbit (256Kb x 8) UV EPROM Description: The NTE27C2001 12D is an 2 Mbit UV EPROM in a 32 Lead DIP type package ideally suited for applications where fast turn around
NTE27C256 12D, NTE27C256 15D, NTE27C256 70D Integrated Circuit 256 Kbit (32Kb x 8) UV EPROM 28 Lead DIP Type Package
NTE27C256 12D, NTE27C256 15D, NTE27C256 70D Integrated Circuit 256 Kbit (32Kb x 8) UV EPROM 28 Lead DIP Type Package NTE27C256 15P Integrated Circuit 256 Kbit (32Kb x 8) OTP EPROM 28 Lead DIP Type Packag
P4C1041 HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM
HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) 10/12/15/20 ns (Commercial) 12/15/20 ns (Industrial/Military) Low Power Single 5.0V ± 10% Power Supply 2.0V
P4C164LL. VERY LOW POWER 8Kx8 STATIC CMOS RAM FEATURES DESCRIPTION V CC. Current (Commercial/Industrial) Operating: 55 ma CMOS Standby: 3 µa
P4C164LL VERY LOW POWER 8Kx8 STATIC CMOS RAM FEATURES Current (Commercial/Industrial) Operating: 55 ma CMOS Standby: 3 µa Access Times 80/100 (Commercial or Industrial) 90/120 (Military) Single 5 Volts
Philips Semiconductors Programmable Logic Devices
DESCRIPTION The PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce maximum propagation
AS4C256K16E0. 5V 256K 16 CMOS DRAM (EDO) Features. Pin designation. Pin arrangement. Selection guide
5V 256K 16 CMOS DRAM (EDO) Features Organization: 262,144 words 16 bits High speed - 30/35/50 ns access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time Low power consumption
NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package
NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package Description: The NTE74S188 Schottky PROM memory is organized in the popular 32 words by 8 bits configuration. A memory
MM74HC132 Quad 2-Input NAND Schmitt Trigger
Quad 2-Input NAND Schmitt Trigger General Description The utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability
8Mb (1M x 8) One-time Programmable, Read-only Memory
Features Fast read access time 90ns Low-power CMOS operation 100µA max standby 40mA max active at 5MHz JEDEC standard packages 32-lead PLCC 32-lead PDIP 5V 10% supply High-reliability CMOS technology 2,000V
NM27C Bit (64K x 8) High Performance CMOS EPROM
February 1994 NM27C512 524 288-Bit (64K x 8) High Performance CMOS EPROM General Description The NM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM) It is
PSRAM 2-Mbit (128K x 16)
PSRAM 2-Mbit (128K x 16) Features Wide voltage range: 2.7V 3.6V Access Time: 55 ns, 70 ns Ultra-low active power Typical active current: 1mA @ f = 1 MHz Typical active current: 14 ma @ f = fmax (For 55-ns)
Programmable Clock Generator
Features Clock outputs ranging from 391 khz to 100 MHz (TTL levels) or 90 MHz (CMOS levels) 2-wire serial interface facilitates programmable output frequency Phase-Locked Loop oscillator input derived
74ABT bit buffer/line driver, non-inverting (3-State)
INTEGRATED CIRCUITS 0-bit buffer/line driver, non-inverting (3-State) Supersedes data of 995 Sep 06 IC23 Data Handbook 998 Jan 6 FEATURES Ideal where high speed, light loading, or increased fan-in are
SRAM AS5C K x 8 SRAM Ultra Low Power SRAM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATION FEATURES GENERAL DESCRIPTION
512K x 8 Ultra Low Power AVAILABLE AS MILITARY SPECIFICATION SMD 5962-95613 1,2 MIL STD-883 1 FEATURES Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby) Fully Static, No
TMS27C BY 16-BIT UV ERASABLE TMS27PC BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES
Organization... 262144 by 16 Bits Single 5-V Power Supply All Inputs/ Outputs Fully TTL Compatible Static Operations (No Clocks, No Refresh) Max Access/Min Cycle Time V CC ± 10% 27C/ PC240-10 100 ns 27C/
MM74HC132 Quad 2-Input NAND Schmitt Trigger
Quad 2-Input NAND Schmitt Trigger General Description The MM74HC132 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well
TMS27C BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC BIT PROGRAMMABLE READ-ONLY MEMORY
This Data Sheet is Applicable to All TMS27C128s and TMS27PC128s Symbolized with Code B as Described on Page 12. Organization...16K 8 Single 5-V Power Supply Pin Compatible With Existing 128K MOS ROMs,
ELECTROSÓN M27C Mbit (128Kb x8) UV EPROM and OTP EPROM
1 Mbit (128Kb x8) UV PROM and OTP PROM 5V ± 10% SUPPLY VOLTAG in RAD OPRATION ACCSS TIM: 35ns LOW POWR CONSUMPTION: Active Current 30mA at 5Mhz Standby Current 100µA PROGRAMMING VOLTAG: 12.75V ± 0.25V
One-PLL General Purpose Clock Generator
One-PLL General Purpose Clock Generator Features Integrated phase-locked loop Low skew, low jitter, high accuracy outputs Frequency Select Pin 3.3V Operation with 2.5 V Output Option 16-TSSOP Benefits
1-Megabit (128K x 8) Unregulated Battery-Voltage OTP EPROM AT27BV010
Features Fast Read Access Time 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power
DS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line Driver
DS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line Driver General Description The DS26C31 is a quad differential line driver designed for digital data transmission over balanced lines. The DS26C31T
INTEGRATED CIRCUITS. 74ABT125 Quad buffer (3-State) Product specification Supersedes data of 1996 Mar 05 IC23 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1996 Mar 05 IC23 Data Handbook 1998 Jan 16 FEATURES Quad bus interface 3-State buffers Live insertion/extraction permitted Output capability: +64mA/ 32mA Latch-up
4-Mbit (512K words 8 bit) Static RAM with Error-Correcting Code (ECC)
4-Mbit (512K words 8 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (512K words 8 bit) Static RAM with Error-Correcting Code (ECC) Features High speed t AA = 10 ns Embedded ECC for single-bit
MM74HC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
1CY 7C42 25 fax id: 5410 CY7C4425/4205/4215 64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs Features High-speed, low-power, first-in first-out (FIFO) memories 64 x 18 (CY7C4425) 256 x 18 (CY7C4205) 512
MM74HCU04 Hex Inverter
MM74HCU04 Hex Inverter General Description The MM74HCU04 inverters utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
3.3V Zero Delay Buffer
3.3V Zero Delay Buffer Features Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations see Available Configurations table Multiple low-skew outputs 10-MHz
Three-PLL General Purpose EPROM Programmable Clock Generator
Features Three integrated phase-locked loops EPROM programmability Factory-programmable (CY2291) or field-programmable (CY2291F) device optio Low-skew, low-jitter, high-accuracy outputs Power-management
256K (32K x 8) CMOS EPROM TSOP A11 A3 14 V PP A12 A7 A6 A5 A4 A3 PLCC VSOP A13 A14 A Microchip Technology Inc.
This document was created with FrameMaker 44 256K (2K x 8) CMS EPRM 27C256 FEATURES High speed performance - 9 ns access time available CMS Technology for low power consumption - 2 ma Active current -
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Organization...131072 by 8 Bits Single 5-V Power Supply Operationally Compatible
QS54/74FCT373T, 2373T. High-Speed CMOS Bus Interface 8-Bit Latches MDSL QUALITY SEMICONDUCTOR, INC. 1 DECEMBER 28, 1998
Q QUALITY SEMICONDUCTOR, INC. QS54/74FCT373T, 2373T High-Speed CMOS Bus Interface 8-Bit Latches QS54/74FCT373T QS54/74FCT2373T FEATURES/BENEFITS Pin and function compatible to the 74F373 74FCT373 and 74ABT373
INTEGRATED CIRCUITS. 74LVC00A Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 11 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 Aug 11 IC24 Data Handbook 1998 Apr 28 FEATURES Wide supply range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5V CMOS
Ethernet Coax Transceiver Interface
1CY7B8392 Features Compliant with IEEE802.3 10BASE5 and 10BASE2 Pin compatible with the popular 8392 Internal squelch circuit to eliminate input noise Hybrid mode collision detect for extended distance
EEPROM AS58LC K x 8 EEPROM Radiation Tolerant. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535
128K x 8 EEPROM Radiation Tolerant AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535 FEATURES High speed: 250ns and 300ns Data Retention: 10 Years Low power dissipation, active current (20mW/MHz (TYP)),
4-Megabit (512K x 8) OTP EPROM AT27C040
Features Fast Read Access Time 70 ns Low Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 32-lead PDIP 32-lead PLCC 32-lead TSOP 5V ± 10% Supply High Reliability
FST Bit Bus Switch
24-Bit Bus Switch General Description The Fairchild Switch FST16211 provides 24-bits of highspeed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to
INTEGRATED CIRCUITS. 74ABT32 Quad 2-input OR gate. Product specification 1995 Sep 22 IC23 Data Handbook
INTEGRATED CIRCUITS 995 Sep 22 IC23 Data Handbook QUICK REFERENCE DATA SYMBOL t PLH t PHL t OSLH t OSHL C IN I CC PARAMETER Propagation delay An, Bn to Yn Output to Output skew Input capacitance Total
14-Bit Registered Buffer PC2700-/PC3200-Compliant
14-Bit Registered Buffer PC2700-/PC3200-Compliant Features Differential Clock Inputs up to 280 MHz Supports LVTTL switching levels on the RESET pin Output drivers have controlled edge rates, so no external
CD4069UBC Inverter Circuits
CD4069UBC Inverter Circuits General Description The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating range, low power
CBT bit 1-of-2 multiplexer/demultiplexer with precharged outputs and Schottky undershoot protection for live insertion
INTEGRATED CIRCUITS 16-bit 1-of-2 multiplexer/demultiplexer with precharged outputs and Schottky undershoot protection for live insertion 2000 Jul 18 FEATURES 5 Ω typical r on Pull-up on B ports Undershoot
FST32X Bit Bus Switch
FST32X245 16-Bit Bus Switch General Description The Fairchild Switch FST32X245 provides 16-bits of high speed CMOS TTL-compatible bus switching in a standard flow-through mode. The low On Resistance of
256K (32K x 8) OTP EPROM AT27C256R
Features Fast Read Access Time 45 ns Low-Power CMOS Operation 100 µa Max Standby 20 ma Max Active at 5 MHz JEDEC Standard Packages 28-lead PDIP 32-lead PLCC 28-lead TSOP and SOIC 5V ± 10% Supply High Reliability