16Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM IS66WV1M16EALL IS66/67WV1M16EBLL DESCRIPTION. Features FUNCTIONAL BLOCK DIAGRAM JANUARY 2018

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1 IS66WV1M16EA IS66/67WV1M16EB 16Mb OW VOTAGE, JANUARY 2018 UTRA OW POWER PSEUDO CMOS STATIC RAM Features ighspeed access time : 70ns ( IS66WV1M16EA ) 60ns (IS66/67WV1M16EB ) CMOS ower Power Operation Single Power Supply VDD =1.7V~1.95V( IS66WV1M16EA ) VDD =2.5V~3.6V (IS66/67WV1M16EB ) Three State Outputs Data Control for Upper and ower bytes eadfree Available DESCRIPTION The ISSI IS66WV1M16EA and IS66/67WV1M16EB are highspeed,16m bit static RAMs organized as 1M words by 16 bits. It is fabricated using ISSI s high performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When is IG (deselected) or when CS2 is OW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active OW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and ower Byte (B#) access. The IS66WV1M16 EA and IS66/67WV1M16EB are packaged in the JEDEC standard 48ball mini BGA (6mm x 8mm). The device is also available for die sales. FUNCTIONA BOCK DIAGRAM A0~A19 VDD GND I/O0I/O7 ower Byte I/O8I/O15 Address Decode ogic I/O DATA CIRCUIT COUMN I/O 1M 16 DRAM Memory Array Upper Byte CS2 OE# WE# UB# B# Control ogic Copyright 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assu mes no liability arising out of the application oruse of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances SRAM@issi.com 1

2 IS66WV1M16EA IS66/67WV1M16EB PIN CONFIGURATIONS 48Ball minibga (6mm x 8mm) Ball Assignment A B B# OE# A0 I/Q8 UB# A3 A1 A2 CS2 A4 I/Q0 C I/Q9 I/Q10 A5 A6 I/Q1 IQ2 D GND IQ11 A17 A7 I/Q3 VDD E VDD IQ12 NC A16 I/Q4 GND F I/Q14 I/Q13 A14 A15 I/Q5 I/Q6 G I/Q15 A19 A12 A13 WE# I/Q7 A18 A8 A9 A10 A11 NC Notes : 1. TSOP package option is under evaluation. PIN DESCRIPTIONS Symbol Type Description A0~A19 Input Address Inputs I/Q0~I/Q15 Input / Output Data Inputs/Outputs, CS2 Input Chip Enable OE# Input Output Enable WE# Input Write Enable UB# Input Upper Byte select B# Input ower Byte select VDD Power Supply Power GND Power Supply Ground SRAM@issi.com 2

3 IS66WV1M16EA IS66/67WV1M16EB POWER UP INITIAIZATION IS66WV1M16EA and IS66/67WV1M16EB include an onchip voltage sensor used to launch the powerup initialization process. When VDD reaches a stable level at or above the VDD (min) the device will require 50μs to complete its selfinitialization process. During the initialization period, should remain IG. When initializeation is complete, the device is ready for normal operation. VDD( min) 50 us 0V VDD Device Initialization Device for Normal Operation TRUT TABE Mode WE# CS2 OE# B# UB# I/O0 I/O7 I/O8 I/O15 VDD Current Not Selected ighz ighz ighz ighz ISB1,ISB2 ISB1,ISB2 Output Disabled ighz ighz ighz ighz Read DOUT ighz D OUT ighz D OUT D OUT Write Din ighz Din ighz Din Din OPERATING RANGE (VDD) Range Ambient Temperature IS66WV1M16EA (70ns) IS66WV1M16EB (55ns, 70ns) IS66WV1M16EB (55ns, 70ns) Industrial 40 C to +85 C 1.7V 1.95V 2.5V 3.6V motive, A1 40 C to +85 C 2.5V 3.6V motive, A2 40 C to +105 C 2.5V 3.6V SRAM@issi.com 3

4 IS66WV1M16EA IS66/67WV1M16EB ABSOUTE MAIMUM RATINGS Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND 0.2 to VDD V TBIAS Temperature Under BIAS 40 to +85 C VDD VDD Related to GND 0.2 to +3.8 V TSTG Storage Temperature 65 to +150 C PT Power Dissipation 1.0 W Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC EECTRICA CARACTERISTICS (Over Operating Range) VDD = 2.5V3.6V (IS66/67WV1M16EB) Symbol Parameter Test Conditions VDD Min. Max. Unit VO Output IG Voltage Io = 1 ma V 2.2 V VO Output OW Voltage Io = 2.1 ma V 0.4 V VI Input IG Voltage(1) V 2.2 VDD V VI Input OW Voltage(1) V V II Input eakage GND VIN VDD 1 1 μa Io Output eakage GND VOUT VDD, Outputs Disabled 1 1 μa 1. VI (min.) = 2.0V AC (pulse width < 10ns). Not 100% tested. VI (max.) = VDD + 2.0V AC (pulse width < 10ns). Not 100% test DC EECTRICA CARACTERISTICS (Over Operating Range) VDD = 1.7V1.95V(IS66WV1M16EA) Symbol Parameter Test Conditions VDD Min. Max. Unit VO Output IG Voltage IO = 0.1 ma V 1.4 V VO Output Ow Voltage IO = 0.1 ma V 0.2 V VI Input IG Voltage(1) V 1.4 VDD V VI Input Ow Voltage(1) V V II Input eakage GND VIN VDD 1 1 μa Io Output eakage GND VOUT VDD, Outputs Disabled 1 1 μa 1. VI (min.) = 1.0V AC (pulse width < 10ns). Not 100% tested. VI (max.) = VDD + 1.0V AC (pulse width < 10ns). Not 100% test SRAM@issi.com 4

5 IS66WV1M16EA IS66/67WV1M16EB CAPACITANCE Symbol Description Conditions MIN MA Unit C IN Input Capacitance VIN = 0V 8 pf C IO Input/Output Capacitance (DQ) Vout = 0V 10 pf 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter 1.7V 1.95V ( Unit ) 2.5V 3.6V ( Unit ) Input Pulse evel 0.4V to VDD 0.2V 0.4V to VDD 0.3V Input Rise and Fall Time Input and Output Timing and Reference evel 5ns VREF 5ns VREF Output oad See Figures 1 and 2 See Figures 1 and 2 Symbol 1.7V 1.95V 2.5V 3.6V R1(Ω) R2(Ω) VREF 0.9V 1.4V VTM 1.8V 2.8V AC TEST OADS R1 R1 VTM VTM OUTPUT OUTPUT 30 pf Including Jig and scope R2 5 pf Including Jig and scope R2 Figure 1 Figure 2 SRAM@issi.com 5

6 IS66WV1M16EA IS66/67WV1M16EB 1.7V1.95V POWER SUPPY CARACTERISTICS (Over Operating Range) Symbol Parameter Conditions Device TYP. MA. 70ns Unit 1 ISB1 ISB2 VDD Dynamic Operating Supply Current Operating Supply Current TT Standby Current ( TT Inputs ) CMOS Standby Current ( CMOS Inputs ) VDD=Max.,IOUT=0mA, f=fma, All inputs = 0.4V or VDD 0.2V VDD=Max.,=0.2V, WE#= VDD 0.2V, f=1mz VDD=Max.,VIN=VI or VI, = VI, CS2=VI, f=1mz VDD=Max., > VDD 0.2V, CS2 < 0.2V, VIN > VDD 0.2V or VIN < 0.2V, f=0 1. At f = f MA, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change ma ma ma ua 2.5V3.6V POWER SUPPY CARACTERISTICS (Over Operating Range) Symbol Parameter Conditions Device TYP MA 55ns Unit VDD Dynamic Operating Supply Current VDD=Max.,IOUT=0mA, f=fma, All inputs = 0.4V or VDD 0.3V Typ.(2) ma 1 Operating Supply Current VDD=Max.,=0.2V, WE#= VDD 0.2V, f=1mz ma ISB1 TT Standby Current ( TT Inputs ) VDD=Max.,VIN=VI or VI, = VI, CS2=VI, f=1mz ma ISB2 CMOS Standby Current ( CMOS Inputs ) VDD=Max., > VDD 0.2V, CS2 < 0.2V, VIN > VDD 0.2V or VIN < 0.2V,f=0 Typ. (2) ua 1. At f = f MA, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, Ta = 25 ºC, and not 100% tested. SRAM@issi.com 6

7 IS66WV1M16EA IS66/67WV1M16EB READ CYCE SWITCING CARACTERISTICS (1) (Over Operating Range) Symbol Parameter Min Max Min Max Unit Notes t RC Read cycle time ns t AA Address Acess Time ns 1 t OA Output old Time ns t ACS1/ACS2 /CS2 Acess Time ns t DOE OE# Access Time ns 1 t ZOE OE# to ighz output ns 2 t ZOE OE# to owz output 5 5 ns 2 t CSM Maximum /CS2 pulse width us t ZCS1/ZCS2 /CS2 to ighz output ns 2 t ZCS1/ZCS2 /CS2 to owz output ns 2 t BA UB#/B# Acess Time ns 1 t ZB UB#/B# to ighz output ns 2 t ZB UB#/B# to owz output 0 0 ns 2 t CP IG (CS2 OW) time 5 5 ns 1. Test conditions and output loading are specified in the AC Test Conditions and AC Test oads (Figure 1) on page Tested with the load in Figure 2. Transition is measured ±100 mv from steadystate voltage. Not 100% tested. AC WAVEFORMS READ CYCE NO. 1 (1) (Address Controlled, OE#= VI, WE#=VI, UB# or B# = VI) Address trc tcsm CS2 toa taa toa DQ 015 PREVIOUS DATA VAID DATA VAID 1. WE# is IG for a Read Cycle. SRAM@issi.com 7

8 IS66WV1M16EA IS66/67WV1M16EB READ CYCE NO. 2 (1) (, CS2, OE# and UB#/B# Controlled) trc ADDRESS OE# taa tdoe toa tcsm tzoe tzoe tace1/tace2 CS2 tzcs1/ tzcs2 tcsm tzcs1/ tzcs2 UB#,B# tzb tba tzb DOUT IGZ DATA VAID 1. Address is valid prior to or coincident with OW (CS2 IG) transition, and is valid after or coincident with I G (CS2 OW) transition. SRAM@issi.com 8

9 IS66WV1M16EA IS66/67WV1M16EB WRITE CYCE SWITCING CARACTERISTICS (1) (Over Operating Range) Symbol Parameter Min Max Min Max Unit Notes t WC Write Cycle Time ns t SCS1/SCS2 /CS2 to Write End ns t CSM Maximum /CS2 pulse width us t AW Address Setup to Write Time ns t A Address old to End of Write 0 0 ns t SA Address Setup Time 0 0 ns t PWB UB#/B# Valid to End of Write ns t PWE WE# Pulse Width ns t SD Data Setup Time ns t ZWE WE# OW to ighz output ns 3 t ZWE WE# IG to owz output 5 5 ns 3 t CP IG (CS2 OW) time 5 5 ns 1. Test conditions and output loading are specified in the AC Test Conditions and AC Test oads (Figure 1) on page The internal write time is defined by the overlap of, UB#, B# and WE# OW, CS2 IG. All signals must be in valid states to initiate a Write, but anyone can go inactive to terminate Write. The Data Input Setup and old timing are referenced to the rising or falling edge of the signals that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±100 mv from steadystate voltage. Not 100% tested. 4. tpwe > tzwe + tsd when OE# is OW. 5. Chip Select Active Time (both OW and CS2 IG) must not be longer than tcms of 15 us. SRAM@issi.com 9

10 IS66WV1M16EA IS66/67WV1M16EB AC WAVEFORMS WRITE CYCE NO. 1 (1) ( Controlled, OE#= IG or OW) twc ADDRESS CS2 WE# UB#,B# tcsm taw tpwe tpwb ta DOUT DIN tsa tzwe tzwe IGZ DATA UNDEFINED tsd td DATA IN VAID 1. Write address is valid prior to or coincident with OW (CS2 IG) transition, and is valid after or coincident with C S1# IG (CS2 OW) transition. WRITE CYCE NO. 2 (WE# Controlled, OE#= IG during Write Cycle) ADDRESS twc OE# tscs1 ta CS2 WE# taw tscs2 tpwe UB#,B# DOUT DIN tsa tzwe tzwe IGZ DATA UNDEFINED tsd td DATA IN VAID SRAM@issi.com 10

11 IS66WV1M16EA IS66/67WV1M16EB WRITE CYCE NO. 3 (WE# Controlled, OE#= OW during Write Cycle) twc ADDRESS OE# CS2 WE# OW taw tscs1 tscs2 tpwe ta UB#,B# tpwb DOUT DIN tsa tzwe tzwe IGZ DATA UNDEFINED tsd td DATAIN VAID WRITE CYCE NO. 4 (UB# / B# Controlled, CS2 is IG during Write Cycle) twc twc ADDRESS ADDRESS 1 ADDRESS 2 tcsm tsa WE# tpwb ta tsa tpwb ta UB#,B# WORD 1 WORD 2 DOUT tzwe DATA UNDEFINED IGZ tsd td tzwe DIN DATA IN VAID DATA IN VAID SRAM@issi.com 11

12 IS66WV1M16EA IS66/67WV1M16EB AVOIDABE TIMING and RECOMMENDATIONS Figure 3a : tcsm Violation 15us WE# Address Figure 3b : Recommendation 15 us 15us 5ns WE# Address SRAM@issi.com 12

13 IS66WV1M16EA IS66/67WV1M16EB AVOIDABE TIMING and RECOMMENDATIONS Figure 4a : tcsm Violation,WE# UB# &B# 15us Address Figure 4b : Recommendation 15us WE#, UB#, B# 15us Address 1. PSRAM uses DRAM cell which needs a REFRES action periodically to retain the information.this REFRES action is performed only when the device is not selected (Chip Select Pins are Disabled). A hidden REFRES action has to be executed by the device at least once every 15 μs of tcsm. 2. Figure 3a shows a timing example in which consecutive READ cycles for more than 15 us. This timing should be avoided for proper REFRES operation. REFRES operation can begin only during Chip Select pins are Disabled ( is igh and CS2 is ow ) for more than 5ns. Example on how to avoid tcsm violation in Figure 3a is shown in Figure 3b. 3. Figure 4a shows a timing example in which a single WRITE operation is maintained for a period greater than 15 μs. Since a proper REFRES action cannot be performed during device is selected by Chip Select pins, information stored in the device will not be retained if this timing occurs. Figure 4b is a timing example of using signal toggling for proper the WRITE operation SRAM@issi.com 13

14 IS66WV1M16EA IS66/67WV1M16EB IS66WV1M16EA Industrial Temperature Range: (40 o C to +85 o C) Voltage Range : 1.7V to 1.95V Config. Speed ( ns) Order Part No. Package 1Mx16 70 IS66WV1M16EA70BI mini BGA(6mm x 8mm), eadfree IS66WV1M16EB Industrial Temperature Range: (40 o C to +85 o C) Voltage Range : 2.5V to 3.6V Config. Speed (ns) Order Part No. Package 1Mx16 55 IS66WV1M16EB55BI mini BGA(6mm x 8mm), eadfree 70 IS66WV1M16EB70BI mini BGA(6mm x 8mm), eadfree motive (A1) Temperature Range: (40 o C to +85 o C) Voltage Range : 2.5V to 3.6V Config. Speed (ns) Order Part No. Package 1Mx16 55 IS67WV1M16EB55BA1 mini BGA(6mm x 8mm), eadfree 70 IS67WV1M16EB70BA1 mini BGA(6mm x 8mm), eadfree motive (A2) Temperature Range: (40 o C to +105 o C) Voltage Range : 2.5V to 3.6V Config. Speed (ns) Order Part No. Package 1Mx16 55 IS67WV1M16EB55BA2 mini BGA(6mm x 8mm), eadfree 70 IS67WV1M16EB70BA2 mini BGA(6mm x 8mm), eadfree SRAM@issi.com 14

15 IS66WV1M16EA IS66/67WV1M16EB 15

IS66WV51216DALL IS66/67WV51216DBLL

IS66WV51216DALL IS66/67WV51216DBLL 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM FEATURES High-speed access time: 70ns (IS66WV51216DALL, ) 55ns () CMOS low power operation Single power supply Vdd = 1.7V-1.95V (IS66WV51216DALL)