I/O1 ~ I/O8 I/O9 ~ I/O16 I/O9 ~ I/O16 I/O1 ~ I/O8
|
|
- Ira Carr
- 5 years ago
- Views:
Transcription
1 Document Title 64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release with Preliminary. Aug Preliminary Rev. 1.0 Release to Data Sheet Delete Preliminary Changed DC characteristics. Item Previous Changed ICC 12ns 85mA 95mA 15ns 83mA 93mA 20ns 80mA 90mA Sep Rev. 2.0 Added 48-fine pitch BGA. Sep Rev. 2.1 Changed device part name for FP-BGA. Item Previous Changed Symbol Z F ex) K6R1016V1C-Z -> K6R1016V1C-F Nov Rev. 2.2 Changed device ball name for FP-BGA. Previous Changed I/O1 ~ I/O8 I/O9 ~ I/O16 I/O9 ~ I/O16 I/O1 ~ I/O8 Dec Rev Added 10ns speed for FP-BGA only. 2. Changed Standby Current. Item Previous Changed Standby Current(Isb1) 0.3mA 0.5mA 3. Added Data Retention Characteristics. Mar Rev. 3.1 Added 10ns speed for all packages(44soj / 44TSOP2 / 48FPBGA) Apr Rev. 3.2 Supply Voltage Change 1. Only 10ns Bin : 3.15V ~ 3.6V 2. The Rest Bin : 3.0V ~ 3.6V Aug Rev. 3.3 VIH/VIL Change Item Previous Changed Min Max Min Max VIH 2.0 VCC VCC+0.3 VIL Oct Rev. 4.0 Delete 20ns speed bin Sep The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters
2 64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating) FEATURES Fast Access Time 10,12,15ns(Max.) Low Power Dissipation Standby (TTL) : 30mA(Max.) (CMOS) : 5mA(Max.) 0.5mA(Max.) L-ver. only Operating * K6R1016V1C-10: 105mA(Max.) K6R1016V1C-12: 95mA(Max.) K6R1016V1C-15: 93mA(Max.) Single 3.3V Power Supply TTL Compatible Inputs and Outputs Fully Static Operation - No Clock or Refresh required Three State Outputs 2V Minimum Data Retention: L-ver. only Center Power/Ground Pin Configuration Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16 Standard Pin Configuration: K6R1016V1C-J: 44-SOJ-400 K6R1016V1C-T: 44-TSOP2-400BF K6R1016V1C-F: 48-Fine pitch BGA with 0.75 Ball pitch GENERAL DESCRIPTION The K6R1016V1C is a 1,048,576-bit high-speed Static Random Access Memory organized as 65,536 words by 16 bits. The K6R1016V1C uses 16 common input and output lines and has at output enable pin which operates faster than address access time at read cycle. Also it allows that lower and upper byte access by data byte control (UB, LB). The device is fabricated using SAMSUNG s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1016V1C is packaged in a 400mil 44-pin plastic SOJ or TSOP2 forward or 48-Fine pitch BGA. FUNCTIONAL BLOCK DIAGRAM Clk Gen. Pre-Charge Circuit ORDERING INFORMATION K6R1016V1C-C10/C12/C15 K6R1016V1C-I10/I12/I15 Commercial Temp. Industrial Temp. A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1~I/O8 I/O 9~I/O16 Row Select Data Cont. Data Cont. Gen. CLK A 9 Memory Array 512 Rows 128x16 Columns I/O Circuit & Column Select A10 A11 A12 A13 A14 A15 PIN FUNCTION Pin Name Pin Function A0 - A15 Inputs Write Enable Chip Select OE Output Enable LB Lower-byte Control(I/O1~I/O8) UB Upper-byte Control(I/O9~I/O16) OE I/O1 ~ I/O16 VCC VSS Data Inputs/Outputs Power(+3.3V) Ground UB LB N.C No Connection - 2 -
3 PIN CONFIGURATION(TOP VIEW) A0 A1 A2 A3 A4 I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 A5 A6 A7 A8 N.C SOJ/ TSOP2 44 A15 43 A14 42 A13 41 OE 40 UB 39 LB 38 I/O16 37 I/O15 36 I/O14 35 I/O13 34 Vss 33 Vcc 32 I/O12 31 I/O11 30 I/O10 29 I/O9 28 N.C 27 A12 26 A11 25 A10 24 A9 23 N.C A B C D E F G H LB OE A0 A1 A2 N.C I/O1 UB A3 A4 I/O9 I/O2 I/O3 A5 A6 I/O11 I/O10 Vss I/O4 N.C A7 I/O12 Vcc Vcc I/O5 N.C N.C I/O13 Vss I/O7 I/O6 A14 A15 I/O14 I/O15 I/O8 N.C A12 A13 I/O16 N.C A8 A9 A10 A11 N.C 48-P ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 4.6 V Voltage on VCC Supply Relative to VSS VCC -0.5 to 4.6 V Power Dissipation Pd 1 W Storage Temperature TSTG -65 to 150 C Operating Temperature Commercial TA 0 to 70 C Industrial TA -40 to 85 C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70 C) Parameter Symbol Min Typ Max Unit Supply Voltage VCC (1) V Supply Voltage VCC (2) V Ground VSS V Input High Voltage VIH VCC+0.3 (3) V Input Low Voltage VIL -0.3 (4) V (1) For K6R1016V1C-10 only. (2) For all speed grades except K6R1016V1C-10. (3) VIH(Max) = VCC + 2.0V a.c(pulse Width 8ns) for I 20mA (4) VIL(Min) = -2.0V a.c(pulse Width 8ns) for I 20mA
4 *DC AND OPERATING CHARACTERISTI*(TA=0 to 70 C, Vcc=3.3V+0.3V/-0.15V, unless otherwise specfied) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN=VSS to VCC -2 2 µa Output Leakage Current ILO =VIH or OE=VIH or =VIL VOUT=VSS to VCC Operating Current ICC Min. Cycle, 100% Duty =VIL, VIN = VIH or VIL, IOUT=0mA -2 2 µa 10ns ma 12ns ns - 93 Standby Current ISB Min. Cycle, =VIH - 30 ma ISB1 f=0mhz, VCC-0.2V, VIN VCC-0.2V or VIN 0.2V Normal - 5 ma L-Ver Output Low Voltage Level VOL IOL=8mA V Output High Voltage Level VOH IOH=-4mA V * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE*(TA=25 C, f=1.0mhz) Item Symbol Test Conditions MIN Max Unit Input/Output Capacitance CI/O VI/O=0V - 8 pf Input Capacitance CIN VIN=0V - 6 pf * Capacitance is sampled and not 100% tested. AC CHARACTERISTI(TA=0 to 70 C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.) TEST CONDITIONS* Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below * The above test conditions are also applied at industrial temperature range. Output Loads(A) Output Loads(B) for thz, tlz, twhz, tow, tolz & tohz DOUT ZO = 50Ω RL = 50Ω 30pF* VL = 1.5V DOUT 353Ω +3.3V 319Ω 5pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance - 4 -
5 READ CYCLE* Parameter Symbol K6R1016V1C-10 K6R1016V1C-12 K6R1016V1C-15 Unit Min Max Min Max Min Max Read Cycle Time trc ns Access Time taa ns Chip Select to Output tco ns Output Enable to Valid Output toe ns UB, LB Access Time tba ns Chip Enable to Low-Z Output tlz ns UB, LB Enable to Low-Z Output tblz ns Output Enable to Low-Z Output tolz ns Chip Disable to Output thz ns Output Disable to Output tohz ns UB, LB Disable to Output tbhz ns Output Hold from Change toh ns Chip Selection to Power Up Time tpu ns Chip Selection to Power DownTime tpd ns * The above parameters are also guaranteed at industrial temperature range. WRITE CYCLE* Parameter Symbol K6R1016V1C-10 K6R1016V1C-12 K6R1016V1C-15 Unit Min Max Min Max Min Max Write Cycle Time twc ns Chip Select to End of Write tcw ns Set-up Time tas ns Valid to End of Write taw ns Write Pulse Width(OE High) twp ns Write Pulse Width(OE Low) twp ns UB, LB Valid to End of Write tbw ns Write Recovery Time twr ns Write to Output twhz ns Data to Write Time Overlap tdw ns Data Hold from Write Time tdh ns End Write to Output Low-Z tow ns * The above parameters are also guaranteed at industrial temperature range. TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) ( Controlled, =OE=VIL, =V IH, UB, LB=V IL trc toh Data Out Previous Valid Data Valid Data taa - 5 -
6 TIMING WAVEFORM OF READ CYCLE(2) (=V IH) trc taa thz(3,4,5) tco tba tbhz(3,4,5) UB, LB OE tblz(4,5) toe tohz tolz toh Data out tlz(4,5) Valid Data VCC Current ICC ISB tpu 50% tpd 50% NOTES(READ CYCLE) 1. is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. thz and tohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or V OL levels. 4. At any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with =V IL. 7. valid prior to coincident with transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock) OE twc taw tcw(3) twr(5) UB, LB tbw tas(4) twp(2) tdw tdh Data in Valid Data tohz(6) Data out - 6 -
7 TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed) twc taw tcw(3) tbw twr(5) UB, LB tas(4) twp1(2) Data in Data out tdw Valid Data tdh twhz(6) tow (10) (9) TIMING WAVEFORM OF WRITE CYCLE(3) (=Controlled) twc taw tcw(3) twr(5) tbw UB, LB tas(4) twp(2) Data in Data out tlz twhz(6) tdw Valid Data tdh (8) - 7 -
8 TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled) twc taw tcw(3) tbw twr(5) UB, LB tas(4) twp(2) Data in Data out tblz twhz(6) tdw Valid Data tdh (8) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low,, LB and UB. A write begins at the latest transition going low and going low; A write ends at the earliest transition going high or going high. twp is measured from the beginning of write to the end of write. 3. tcw is measured from the later of going low to end of write. 4. tas is measured from the address valid to the beginning of write. 5. twr is measured from the end of write to the address change. t WR applied in case a write ends as or going high. 6. If OE, and are in the Read Mode during this period, the I/O pins are in the output low-z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If goes low simultaneously with going or after going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION OE LB UB Mode I/O1~I/O8 I/O Pin I/O9~I/O16 Supply Current H X X* X X Not Select ISB, ISB1 L H H X X Output Disable ICC L X X H H L H L L H Read DOUT ICC H L DOUT L L DOUT DOUT L L X L H Write DIN ICC H L DIN L L DIN DIN * X means Don t Care
9 DATA RETENTION CHARACTERISTI*(TA=0 to 70 C) Parameter Symbol Test Condition Min. Typ. Max. Unit VCC for Data Retention VDR VCC-0.2V V Data Retention Current IDR VCC=3.0V, VCC-0.2V VIN VCC-0.2V or VIN 0.2V VCC=2.0V, VCC-0.2V VIN VCC-0.2V or VIN 0.2V ma Data Retention Set-Up Time tsdr See Data Retention ns Recovery Time trdr Wave form(below) ms * The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only. DATA RETENTION WAVE FORM controlled VCC tsdr Data Retention Mode trdr 3.0V VIH VDR GND VCC - 0.2V - 9 -
10 PACKAGE DIMENSIONS Units:millimeters/Inches 44-SOJ-400 #44 # ± ± ± ± # MAX # MIN ± ± ( ) ( ) ( ) MAX 0.10 MAX TSOP2-400BF TYP Units:millimeters/Inches 0~8 #44 # ~ ~ ± ± ( 0.50 ) # MAX ± ± # ( ) ± ± MIN MAX MAX - 10
11 PACKAGE OUTLINE (Units : millimeter) Top View Bottom View B B B A1 INDEX MARK A #A1 B C D C E C1 C C1/2 F G H B/2 Side View Detail A E E E2 D 0.25/Typ. A Y C 0.80/Typ. Min Typ Max A B B C C D E E E Y Notes. 1. Bump counts: 48(8row x 6column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/ unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max) - 11
I/O1 ~ I/O8 I/O9 ~ I/O16 I/O9 ~ I/O16 I/O1 ~ I/O8
Document Title 64Kx16 Bit High-Speed CMOS Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release
More informationItem Previous Current 8ns 110mA 80mA. 10ns 90mA 65mA 12ns 80mA 55mA 15ns 70mA 45mA 8ns 130mA 100mA
Document Title 256Kx16 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial release with
More informationPRELIMINARY PRELIMINARY
Document Title 256Kx4 Bit (with ) High-Speed CMOS Static RAM(5.0V Operating). Revision History Rev. No. History Draft Data Remark Rev. 0.0 Rev. 0.1 Rev. 0.2 Initial release with Preliminary. Current modify
More informationDocument Title. Revision History. 256Kx16 bit Low Power and Low Voltage CMOS Static RAM. Draft Date. Revision No. History. Remark.
Document Title 256Kx16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No History Draft Date Remark 0.0 Initial draft July 29, 2002 Preliminary 0.1 Revised - Added Commercial product
More informationDocument Title. Revision History. 32Kx8 bit Low Power CMOS Static RAM. Remark. History. Revision No. Draft Data. Design target. Initial draft 0.
Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data Remark 0.0 Initial draft May 18, 1997 Design target 0.1 First revision - KM62256DL/DLI ISB1 = 100 50µA
More informationCMOS SRAM. KM684000B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.
Document Title 512Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft December 7, 1996 Advance 0.1 Revise - Changed Operating current by reticle
More informationRev. No. History Issue Date Remark
8K X 8 BIT CMOS SRAM Document Title 8K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 9, 2004 Preliminary 1.0 Remove non-pb-free package type July 3, 2006
More informationRev. No. History Issue Date Remark
32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 2, 2001 Preliminary 0.1 Add ultra temp grade and 28-pin DIP package
More informationHY62WT08081E Series 32Kx8bit CMOS SRAM
32Kx8bit CMOS SRAM Document Title 32K x8 bit 2.7~5.5V Low Power Slow SRAM Revision History Revision No History Draft Date Remark 00 Initial Feb.05.2001 Preliminary 01 Revised Feb.13.2001 Final - Change
More informationLY62L K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 1.1 Adding PKG type : 32 SOP Mar.3.2006 Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR May.14.2007
More informationIDT CMOS Static RAM 1 Meg (256K x 4-Bit)
CMOS Static RAM 1 Meg (256K x 4-Bit) IDT71028 Features 256K x 4 advanced high-speed CMOS static RAM Equal access and cycle times Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable
More informationLY K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0. Initial Issue Jul.25.2004 Rev. 2.0. Revised Vcc Range(Vcc=4.5~5.5V => 2.7~5.5V) May.4.2005 Rev. 2.1. Revised ISB1 May.13.2005 Rev. 2.2 Adding
More informationLY K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0. Initial Issue Jul.25.2004 Rev. 2.0. Revised Vcc Range(Vcc=4.5~5.5V => 2.7~5.5V) May.4.2005 Rev. 2.1. Revised ISB1 May.13.2005 Rev. 2.2 Adding
More informationUTRON UT K X 8 BIT LOW POWER CMOS SRAM
FEATURES GENERAL DESCRIPTION Access time : 35/70ns (max) Low power consumption: Operating : 60/40 ma (typical) Standby : 3mA (typical) normal ua (typical) L-version 1uA (typical) LL-version Single 5V power
More informationLY62L K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Feb.24.2010 Rev. 1.1 Revised PACKAGE OUTLINE DIMENSION in page 10 May.7.2010 Deleted WRITE CYCLE Notes : 1. WE#, CE# must be high
More informationCMOS STATIC RAM 1 MEG (128K x 8-BIT)
CMOS STATIC RAM 1 MEG (12K x -BIT) IDT71024 Integrated Device Technology, Inc. FEATURES: 12K x advanced high-speed CMOS static RAM Commercial (0 to 70 C), Industrial (-40 to 5 C) and Military (-55 to 125
More informationLY V 128K X 16 BIT HIGH SPEED CMOS SRAM
Y6112816 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Aug.12.2007 Rev. 1.1 Apr. 17.2009 Revised TEST CONDITION of ICC Revised FEATURES & ORDERING INFORMATION ead free and green
More information3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Description OBSOLESCENCE ORDER 71V016SA. Row / Column Decoders. Sense Amps and Write Drivers
3.3V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1 Features 4K x 1 advanced high-speed CMOS Static RAM Commercial ( to +7 C) and Industrial ( 4 C to +5 C) Equal access and cycle times Commercial and Industrial:
More informationLY61L K X 16 BIT HIGH SPEED CMOS SRAM
Y6125616 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue May.24.2006 Rev. 1.1 Added Extended Grade Jan.22.2007 Rev. 1.2 Added PKG Type : 48-ball 6mm x 8mm TFBGA Jan.30.2007 Rev.
More information3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
3.3V CMOS Static RAM Meg (2K x 1-Bit) IDT71V1S IDT71V1L Features 2K x 1 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle times Commercial and
More informationLY61L25616A 256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 VCC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current ICC1 on
More information10/February/07, v.1.0 Alliance Memory Inc. Page 1 of 13
FEATURES Access time : 55ns Low power consumption: Operating current :20mA (TYP.) Standby current : 20mA(TYP.)L Version 1µ A (TYP.) LL-version Single 2.7V ~ 3.6V power supply Fully static operation Tri-state
More informationCMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S
CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S Features 128K x 8 advanced high-speed CMOS static RAM Commercial (0 C to +70 C), Industrial ( 40 C to +85 C) Equal access and cycle times Commercial and Industrial:
More informationIDT71V424S/YS/VS IDT71V424L/YL/VL
.V CMOS Static RAM Meg (K x -Bit) IDT1V2S/YS/VS IDT1V2L/YL/VL Features K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times Commercial
More informationHY62256A Series 32Kx8bit CMOS SRAM
32Kx8bit CMOS SRAM DESCRIPTION The HY62256A is a high-speed, low power and 32,786 x 8-bits CMOS Static Random Access Memory fabricated using Hyundai's high performance CMOS process technology. The HY62256A
More informationIDT71V016SA/HSA. 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)
.V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1SA/HSA Features 4K x 1 advanced high-speed CMOS Static RAM Equal access and cycle times Commercial: 1//1/2 Industrial: /1/2 One Chip Select plus one Output
More informationRevision No History Draft Date Remark. 10 Initial Revision History Insert Jul Final
128Kx8bit CMOS SRAM Document Title 128K x8 bit 5.0V Low Power CMOS slow SRAM Revision History Revision No History Draft Date Remark 10 Initial Revision History Insert Jul.14.2000 Final 11 Marking Information
More informationJANUARY/2008, V 1.0 Alliance Memory Inc. Page 1 of 11
1024K X 8 BIT SUPER 512K LOW POWER X8BITCMOS LOW SRAM FEATURES Fast access time : 55ns Low power consumption: Operating current : 30mA (TYP.) Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V
More informationUM61512A Series 64K X 8 BIT HIGH SPEED CMOS SRAM. Features. General Description. Pin Configurations UM61512AV UM61512A
Series 64K X 8 BIT HIGH SPEE CMOS SRAM Features Single +5V power supply Access times: 15/20/25ns (max.) Current: Operating: 160mA (max.) Standby: 10mA (max.) Full static operation, no clock or refreshing
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JULY 2006 FEATURES High-speed access time: 10, 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS stand-by
More informationpower and 32,786 x 8-bits and outputs -2.0V(min.) data fabricated using
查询 HY62256A 供应商 Data Sheet-sram/62256ald1 http://www.hea.com/hean2/sram/62256ald1.htm HY62256A-(I) Series 32Kx8bit CMOS SRAM Description Features The Fully static operation and HY62256A/HY62256A-I Tri-state
More informationIS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
64K x 16 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
128K x 8 LOW POR CMOS STATIC RAM DECEMBER 2003 FEATURES High-speed access time: 35, 70 ns Low active power: 450 mw (typical) Low standby power: 150 µw (typical) CMOS standby Output Enable (OE) and two
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C64 8K x 8 LOW POR CMOS STATIC RAM FEATURES CMOS low power operation 400 mw (max.) operating 25 mw (max.) standby Automatic power-down when chip is deselected TTL compatible interface levels Single
More information64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005 FEATURES IS61C6416AL and High-speed access time: 12 ns, 15ns Low Active Power: 175 mw (typical) Low Standby Power: 1 mw (typical) CMOS standby and High-speed
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
8K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 0 ns CMOS low power operation mw (typical) CMOS standby 25 mw (typical) operating TTL compatible interface levels Single
More informationIS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM MAY 2012 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
More informationIS62WV102416ALL IS62WV102416BLL IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POR ASYNCHRONOUS CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
More information1M Async Fast SRAM. Revision History CS16FS1024(3/5/W) Rev. No. History Issue Date
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014 2.0 Add 32TSOPII-400mil pin configuration and outline May 26, 2014 3.0 Delete 128kx8 products May 22, 2015 4.0 Add part no. CS16FS10245GC(I)-12
More information16M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr. 15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 16,789,216-bit high-speed Static Random Access Memory organized as 1M(2M) words
More informationIS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 10, 12 ns CMOS Low Power Operation 1 mw (typical) CMOS standby 125 mw (typical) operating Fully static operation: no clock
More informationIS65LV256AL IS62LV256AL
32K x 8 LOW VOLTAGE CMOS STATIC RAM MAY 2012 FEATURES High-speed access time: 20, 45 ns Automatic power-down when chip is deselected CMOS low power operation 17 µw (typical) CMOS standby 50 mw (typical)
More informationIS61/64WV5128EFALL IS61/64WV5128EFBLL. 512Kx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
512Kx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC APRIL 2018 KEY FEATURES A0 A17 A18 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV5128EFALL) 2.4V-3.6V () Error Detection
More information2M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 2,097,152-bit high-speed Static Random Access Memory organized as 128K(256) words
More information4M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 4,194,304-bit high-speed Static Random Access Memory organized as 256K(512) words
More informationIS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM DEMBER 00 FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical)
More informationIS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
More informationIS61C25616AL IS61C25616AS IS64C25616AL IS64C25616AS
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) High-speed access time: 10ns, 12 ns Low Active Power: 150 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby LOW POR:
More informationIS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS
More informationRev. No. History Issue Date Remark
256K X 8 BIT LOW VOLTAGE CMOS SRAM ocument Title 256K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue June 24, 2002 Preliminary 0.1 Change VCC range from
More informationCMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
Integrated Device Technology, Inc. CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM IDT6178S FEATURES: High-speed Address to Valid time Military: 12/15/20/25ns Commercial: 10/12/15/20/25ns (max.) High-speed
More informationIS63LV1024 IS63LV1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT FEATURES High-speed access times: 8, 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise
More informationIS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection
More informationIS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
IS61WV25616ALL/ALS IS61WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) High-speed access time: 8, 10, 20 ns Low Active Power: 85 mw (typical)
More informationIS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM JULY 2007 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
More informationIS61WV20488FALL IS61/64WV20488FBLL. 2Mx8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
2Mx8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
More informationIS61WV102416FALL IS61/64WV102416FBLL. 1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
More informationIS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
More informationIS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM August 2016 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW POR CMOS STATIC RAM FEATURES Access time: 45, 70 ns Low active power: 200 mw (typical) Low standby power 250 µw (typical) CMOS standby 28 mw (typical) TTL standby Fully static operation: no
More informationDECODER I/O DATA CONTROL CIRCUIT
1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2006 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation: 36 mw (typical) operating 12 µw (typical) CMOS standby TTL compatible
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW VOLTAGE CMOS STATIC RAM June 2005 FEATURES High-speed access times: -- 8, 10, 12, 15 ns Automatic power-down when chip is deselected CMOS low power operation -- 345 mw (max.) operating -- 7
More informationIS61WV3216DALL/DALS IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS
IS61WV3216DALL/DALS IS61WV3216DBLL/DBLS 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM MAY 2012 FEATURES HIGH SPEED: (IS61/64WV3216DALL/DBLL) High-speed access time: 8, 10, 12, 20 ns Low Active Power:
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES High-speed access times: 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2008 FEATURES High-speed access time: 8, 10 ns Operating Current: 50mA (typ.) Standby Current: 700µA (typ.) Multiple center power and ground pins for greater noise
More information32M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr. 26,2017
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 26,2017 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 33,578,432-bit high-speed Static Random Access Memory organized as 4M(2M) words
More informationIS61WV102416ALL IS61WV102416BLL IS64WV102416BLL
1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY MAY 2012 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for
More informationIS62C10248AL IS65C10248AL
IS62C10248AL IS65C10248AL 1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM AUGUST 2009 FEATURES High-speed access time: 10, 12, 15, 20 ns Low active power: 400 mw (typical) Low standby power 250 µw (typical) CMOS standby 55 mw (typical) TTL
More informationIS61WV10248EEALL IS61/64WV10248EEBLL. 1Mx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM OCTOBER 2018
1Mx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC OCTOBER 2018 KEY FEATURES High-speed access time: 8ns, 10ns, 20ns Single power supply 1.65V-2.2V (IS61WV10248EEALL) 2.4V-3.6V () Error Detection and Correction
More informationIS62C51216AL IS65C51216AL
IS62C51216AL IS65C51216AL 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
More informationIS62WV102416GALL/BLL IS65WV102416GALL/BLL. 1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM. FUNCTIONAL Block Diagram NOVEMBER 2017
1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM NOVEMBER 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
More informationIS61WV6416DALL/DALS IS61WV6416DBLL/DBLS IS64WV6416DBLL/DBLS
ISWVDALL/DALS ISWVDBLL/DBLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM JANUARY 0 FEATURES HIGH SPEED: (IS/WVDALL/DBLL) High-speed access time:, 0,, 0 ns Low Active Power: mw (typical) Low Standby Power:
More informationIS62WV25616EALL/EBLL/ECLL IS65WV25616EBLL/ECLL. 256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM JANUARY 2018
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2018 KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current:
More informationIS61WV10248EDBLL IS64WV10248EDBLL
1M x 8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEBRUARY 2013 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
More informationIS62/65WV2568DALL IS62/65WV2568DBLL
IS62/65WV2568DALL IS62/65WV2568DBLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating
More informationIS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM Long-term Support NOVEMBER 2016 FEATURES High-speed access time: 45ns, 55ns, 70ns CMOS low power operation 36 mw (typical)
More informationIS61C1024AL IS64C1024AL
IS61C1024AL IS64C1024AL 128K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2015 FEATURES High-speed access time: 12, 15 ns Low active power: 160 mw (typical) Low standby power: 1000 µw (typical) CMOS standby Output
More informationIS61WV10248ALL IS61WV10248BLL IS64WV10248BLL
1M x 8 HIGH-SPEED CMOS STATIC RAM MARCH 2017 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
More informationIS62C5128BL, IS65C5128BL
512K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2011 FEATURES High-speed access time: 45ns Low Active Power: 50 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby TTL compatible interface levels Single
More informationIS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
More informationIS62C25616EL, IS65C25616EL
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM AUGUST 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 5.0uA
More informationIS62WV25616ALL IS62WV25616BLL
IS62WV25616ALL IS62WV25616BLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM MARCH 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
More informationIS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
More informationIS62WV102416FALL/BLL IS65WV102416FALL/BLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM MARCH 2018
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
More informationIS61WV2568EDBLL IS64WV2568EDBLL
ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply
More informationIS62WV6416ALL IS62WV6416BLL
IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access time: 45ns, 55ns CMOS low power operation: 30 mw (typical) operating 15 µw (typical)
More informationFUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
More informationDESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C1024 128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES High-speed access time: 35, 45, 55, 70 ns Low active power: 450 mw (typical) Low standby power: 500 µw (typical) CMOS standby Output Enable () and
More informationSRM2B256SLMX55/70/10
256K-BIT STATIC RAM Wide Temperature Range Extremely Low Standby Current Access Time 100ns (2.7V) 55ns (4.5V) 32,768 Words 8-Bit Asynchronous DESCRIPTION The SRM2B256SLMX is a low voltage operating 32,768
More informationIS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES High-speed access time: 35, 45, 55 ns CMOS low power operation 30 mw (typical) operating 6 µw (typical) CMOS standby TTL compatible interface
More informationIS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
More informationIS62WV25616EHALL/BLL IS65WV25616EHALL/BLL. 256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC PRELIMINARY INFORMATION AUGUST 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.)
More informationIS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
More informationVery Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable FEATURES DESCRIPTION Very low operation voltage : 45 ~ 55V Very low power consumption : = 50V C-grade: 40mA (Max) operating current
More informationIS62WV51216EFALL/BLL IS65WV51216EFALL/BLL. 512Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM AUGUST 2017
512Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC AUGUST 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA
More informationWhite Electronic Designs
* 1Mx32 SRAM 3.3V MODULE FEATURES Access Times of 17, 20, 25ns 4 lead, 2mm CQFP, (Package 511) Organized as two banks of 512Kx32, User Configurable as 2Mx16 or 4Mx Commercial, Industrial and Military Temperature
More informationDESCRIPTION ECC. Array 1Mx5
1Mx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES High-speed access time: 10ns, 12ns A0 A19 Single power supply 2.4V-3.6V Error Detection and Correction with optional ERR1/ERR2 output
More information