Document Title. Revision History. 32Kx8 bit Low Power CMOS Static RAM. Remark. History. Revision No. Draft Data. Design target. Initial draft 0.

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1 Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data Remark 0.0 Initial draft May 18, 1997 Design target 0.1 First revision - KM62256DL/DLI ISB1 = µA KM62256DL-L ISB1 = 20 10µA KM62256DLI-L ISB1 = 50 15µA - CIN = 6 8pF, CIO = 8 10pF - KM62256D-4/5/7 Family toh = 5 10ns - KM62256DL/DLI IDR = 50 30µA KM62256DL-L/DLI-L IDR = 30 15µA April 1, 1997 Preliminily 1.0 Finalize - Remove ICC write value - Improved operating current ICC2 = 70 60mA - Improved standby current KM62256DL/DLI ISB1 = 50 30µA KM62256DL-L ISB1 = 10 5µA KM62256DLI-L ISB1 = 15 5µA - Improved data retention current KM62256DL/DLI IDR = 30 5µA KM62256DL-L/DLI-L IDR = 15 3µA - Remove 45ns part from commercial product and 100ns part from industrial product. Replace test load 100pF to 50pF for 55ns part November 11, 1997 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

2 32Kx8 bit Low Power CMOS Static RAM FEATURES Process Technology : TFT Organization : 32Kx8 Power Supply Voltage : 4.5~5.5V Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : 28-DIP-600B, 28-SOP TSOP F/R GENERAL DESCRIPTION The K6T0808C1D families are fabricated by SAMSUNG s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current. PRODUCT FAMILY Product Family Operating Temperature VCC Range Speed 1. The parameter is tested with 50pF test load. Power Dissipation Standby (ISB1, Max) K6T0808C1D-L 30µA Commercial (0~70 C) 55 1) /70ns K6T0808C1D-B 5µA 4.5 to 5.5V K6T0808C1D-P Industrial (-40~85 C) 70ns K6T0808C1D-F 5µA Operating (Icc2, Max) PKG Type 28-DIP,28-SOP 28-TSOP1-F/R 60mA 30µA 28-SOP 28-TSOP1-F/R PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS DIP 28-SOP VCC A13 A8 A9 A11 A10 I/O8 I/O7 I/O6 I/O5 I/O4 A11 A9 A8 A13 VCC A14 A12 A7 A6 A5 A4 A3 A3 A4 A5 A6 A7 A12 A14 VCC A13 A8 A9 A TSOP Type1 - Forward 28-TSOP Type1 - Reverse A10 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 A10 I/O1 I/O8 A13 A8 A12 A14 A4 A5 A6 A7 Clk gen. Row select Data cont Data cont Precharge circuit. Memory array 256 rows columns I/O Circuit Column select A10 A3 A0 A1 A2 A9 A11 Pin Name Function Pin Name Function Chip Select Input I/O1~I/O8 Data Inputs/Outputs Output Enable Input Vcc Power Write Enable Input Vss Ground A0~A14 Address Inputs NC No connect Control Logic SAMSUNG ELECTRONI CO., LTD. reserves the right to change products and specifications without notice.

3 PRODUCT LIST Commercial Temperature Products(0~70 C) Industrial Temperature Products(-40~85 C) Part Name Function Part Name Function K6T0808C1D-DL55 K6T0808C1D-DB55 K6T0808C1D-DL70 K6T0808C1D-DB70 K6T0808C1D-GL55 K6T0808C1D-GB55 K6T0808C1D-GL70 K6T0808C1D-GB70 K6T0808C1D-TL55 K6T0808C1D-TB55 K6T0808C1D-TL70 K6T0808C1D-TB70 K6T0808C1D-RL55 K6T0808C1D-RB55 K6T0808C1D-RL70 K6T0808C1D-RB70 28-DIP, 55ns, L-pwr 28-DIP, 55ns, LL-pwr 28-DIP, 70ns, L-pwr 28-DIP, 70ns, LL-pwr 28-SOP, 55ns, L-pwr 28-SOP, 55ns, LL-pwr 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP1 F, 55ns, L-pwr 28-TSOP1 F, 55ns, LL-pwr 28-TSOP1 F, 70ns, L-pwr 28-TSOP1 F, 70ns, LL-pwr 28-TSOP1 R, 55ns, L-pwr 28-TSOP1 R, 55ns, LL-pwr 28-TSOP1 R, 70ns, L-pwr 28-TSOP1 R, 70ns, LL-pwr K6T0808C1D-GP70 K6T0808C1D-GF70 K6T0808C1D-TP70 K6T0808C1D-TF70 K6T0808C1D-RP70 K6T0808C1D-RF70 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP1 F, 70ns, L-pwr 28-TSOP1 F, 70ns, LL-pwr 28-TSOP1 R, 70ns, L-pwr 28-TSOP1 R, 70ns, LL-pwr FUNCTIONAL DESCRIPTION I/O Mode Power H X 1) X 1) High-Z Deselected Standby L H H High-Z Output Disabled Active L L H Dout Read Active L X 1) L Din Write Active 1. X means don t care (Must be in high or low states) ABSOLUTE IMUM RATINGS 1) Item Symbol Ratings Unit Remark Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V - Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V - Power Dissipation PD 1.0 W - Storage temperature TSTG -65 to 150 C - Operating Temperature TA 0 to 70 C K6T0808C1D-L -40 to 85 C K6T0808C1D-P Soldering temperature and time TSOLDER 260 C, 10sec (Lead Only) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

4 RECOMMENDED DC OPERATING CONDITIONS 1) Item Symbol Min Typ Max Unit Supply voltage Vcc V Ground Vss V Input high voltage VIH Vcc+0.5V 2) V Input low voltage VIL ) V Note: 1. Commercial Product : TA=0 to 70 C, otherwise specified Industrial Product : TA=-40 to 85 C, otherwise specified 2. Overshoot : VCC+3.0V in case of pulse width 30ns 3. Undershoot : -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested CAPACITANCE 1) (f=1mhz, TA=25 C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pf Input/Output capacitance CIO VIO=0V - 10 pf 1. Capacitance is sampled not, 100% tested DC AND OPERATING CHARACTERISTI Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1-1 µa Output leakage current ILO =VIH or =VIH or =VIL, VIO=VSS to Vcc -1-1 µa Operating power supply current ICC IIO=0mA, =VIL, VIN=VIH or VIL, Read ma Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA 0.2V, VIN 0.2V, VIN Vcc -0.2V Read Write - 20 ICC2 Cycle time=min,100% duty, IIO=0mA, =VIL, VIN=VIH or VIL ma Output low voltage VOL IOL=2.1mA V Output high voltage VOH IOH=-1.0mA V Standby Current(TTL) ISB =VIH, Other inputs=vih or VIL ma Standby Current (CMOS) ISB1 Vcc-0.2V, Other inputs=0~vcc ma Low Power µa Low Low Power µa

5 AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL=50pF+1TTL CL 1) 1. Including scope and jig capacitance AC CHARACTERISTI (Vcc=4.5~5.5V, K6T0808C1D-L Family:TA=0 to 70 C, K6T0808C1D-P Family:TA=-40 to 85 C) Speed Bins Parameter List Symbol 55 1) ns 70ns Units Min Max Min Max Read cycle time trc ns Address access time taa ns Chip select to output tco ns Output enable to valid output t ns Read Chip select to low-z output tlz ns Output enable to low-z output tolz ns Chip disable to high-z output thz ns Output disable to high-z output tohz ns Output hold from address change toh ns Write cycle time twc ns Chip select to end of write tcw ns Address set-up time tas ns Address valid to end of write taw ns Write Write pulse width twp ns Write recovery time twr ns Write to output high-z twhz ns Data to write time overlap tdw ns Data hold from write time tdh ns End write to output low-z tow ns 1. The parameter is tested with 50pF test load. DATA RETENTION CHARACTERISTI Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR Vcc-0.2V V Data retention current IDR Vcc=3.0V, Vcc-0.2V L-Ver µa LL-Ver Data retention set-up time tsdr See data retention waveform ms Recovery time trdr 5 - -

6 TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, ==VIL, =VIH) Address trc toh Data Out Previous Data Valid Data Valid taa TIMING WAVEFORM OF READ CYCLE(2) (=VIH) trc Address taa toh tco t thz tolz tohz Data out High-Z tlz Data Valid NOTES (READ CYCLE) 1. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection.

7 TIMING WAVEFORM OF WRITE CYCLE(1) ( Controlled) Address twc tcw(2) twr(4) taw twp(1) tas(3) tdw tdh Data in Data Valid twhz tow Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) ( Controlled) twc Address tas(3) tcw(2) twr(4) taw twp(1) tdw tdh Data in Data Valid Data out High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low and a low. A write begins at the latest transition among going Low and going low : A write end at the earliest transition among going high and going high, twp is measured from the begining of write to the end of write. 2. tcw is measured from the going low to end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as or going high. DATA RETENTION WAVE FORM controlled VCC tsdr Data Retention Mode trdr 4.5V 2.2V VDR GND VCC - 0.2V

8 PACKAGE DIMENSIONS 28 PIN DUAL INLINE PACKAGE(600mil) Units: millimeter(inch) #28 # ± ± #1 #14 0~ ± ± ± ± ± ± ± ± ± ± MIN 28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil) 0~8 #28 # ± ± ± ± #1 # ± ± ± ± ± ± ± ± MIN 0.002

9 PACKAGE DIMENSIONS Units: millimeter(inch) 28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F) # ± ± # #14 # ~ TYP 11.80± ± ± ± MIN 0.45 ~ ~ PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R) # ± ± # #1 # TYP 11.80± ± ± ± MIN 0~ ~ ~