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1 256K X 8 BIT LOW VOLTAGE CMOS SRAM ocument Title 256K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue June 24, 2002 Preliminary 0.1 Change VCC range from 2.7V~3.3V to 2.7V~3.6V October 15, Add 32-pin TSSOP reverse type package April 15, 2003 Final Final version release 1.1 Add 32L Pb-Free TSSOP package type June 16, Add Pb-Free package type for all parts August 19, 2004 (August, 2004, Version 1.2) AMIC Technology, Corp.
2 256K X 8 BIT LOW VOLTAGE CMOS SRAM Features Power supply range: 2.7V to 3.6V Access times: 55/70 ns (max.) Current: Very low power version: Operating: 55ns: 25mA (max.) 70ns: 20mA (max.) Standby: 10µA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using three-state output Output enable and two chip enable inputs for easy application ata retention voltage: 2V (min.) Available in 32-pin SOP, TSOP, TSSOP (8X13.4mm forward & reverse type) and 36-pin CSP packages General escription The LP62S2048A-T is a low operating current 2,097,152-bit static random access memory organized as 262,144 words by 8 bits and operates on a low power supply range: 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-OWN and device enable and an output enable input is included for easy interfacing. ata retention is guaranteed at a power supply voltage as low as 2V. Product Family Product Family Operating Temperature VCC Range Speed ata Retention (ICCR, Typ.) Power issipation Standby (ISB1, Typ.) Operating (ICC2, Typ.) LP62S2048A -25 C ~ +85 C 2.7V~3.6V 55ns / 70ns 0.5µA 0.5µA 3mA Package Type 32L SOP 32L TSOP 32L TSSOP (Forward type) 32L TSSOP (Reverse type) 36L CSP 1. Typical values are measured at VCC = 3.0V, TA = 25 C and not 100% tested. 2. ata retention current VCC = 2.0V. (August, 2004, Version 1.2) 1 AMIC Technology, Corp.
3 Pin Configurations SOP TSOP/(TSSOP) TSSOP CSP (Chip Size Package) (forward type) (reverse type) 36-pin Top View A17 A VCC A A CE2 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O LP62S2048AM-T WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 LP62S2048AV-T (LP62S2048AX-T) LP62S2048AXR-T A B C E F G H 1 A0 I/O5 I/O6 GN VCC I/O7 I/O8 A9 2 A1 A2 OE A10 3 CE2 WE NC NC CE1 A A3 A6 A8 A4 A7 I/O1 A5 I/O2 VCC GN A17 I/O3 A16 A15 I/O4 A12 A13 A14 GN I/O4 Pin No Pin Name A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 Pin No Pin Name A3 A2 A1 A0 I/O1 I/O2 I/O3 GN I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE Block iagram A0 VCC GN A15 A16 ROW ECOER 1024 X 2048 MEMORY ARRAY A17 I/O1 INPUT ATA CIRCUIT COLUMN I/O I/O8 CE2 CE1 OE WE CONTROL CIRCUIT (August, 2004, Version 1.2) 2 AMIC Technology, Corp.
4 Pin escription - SOP Pin No. Symbol escription Pin escriptions - TSOP/TSSOP Pin No. Symbol escription 1-12, 23, 25-28, 31 A0 - A17 Address Inputs 1-4, 7, 9-20, 31 A0 - A17 Address Inputs 13-15, I/O1 - I/O8 16 GN Ground ata Input/Outputs 22 CE1 Chip Enable 24 OE Output Enable 29 WE Write Enable 30 CE2 Chip Enable 32 VCC Power Supply 5 WE Write Enable 6 CE2 Chip Enable 8 VCC Power Supply 9 NC No Connection 21-23, I/O1 - I/O8 ata Input/Outputs 24 GN Ground 30 CE1 Chip Enable 32 OE Output Enable Pin escription - CSP Symbol escription Symbol escription A0 - A17 Address Inputs NC No Connection WE Write Enable I/O1 - I/O8 ata Input/Output OE Output Enable VCC Power Supply CE1 Chip Enable GN Ground CE2 Chip Enable Recommended C Operating Conditions (TA = -25 C to + 85 C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GN Ground V VIH Input High Voltage VCC V VIL Input Low Voltage V CL Output Load pf TTL Output Load (August, 2004, Version 1.2) 3 AMIC Technology, Corp.
5 Absolute Maximum Ratings* VCC to GN V to + 4.6V IN, IN/OUT Volt to GN V to VCC + 0.5V Operating Temperature, Topr C to + 85 C Storage Temperature, Tstg C to C Temperature Under Bias, Tbias C to + 85 C Power issipation, PT W Soldering Temp. & Time C, 10 sec *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. C Electrical Characteristics (TA = -25 C to + 85 C, VCC = 2.7V to 3.6V, GN = 0V) Symbol Parameter LP62S2048A-55LLT LP62S2048A-70LLT Unit Conditions Min. Max. Min. Max. ILI Input Leakage Current µa VIN = GN to VCC ILO Output Leakage Current µa CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GN to VCC ICC Active Power Supply Current ma CE1 = VIL, CE2 = VIH II/O = 0mA ICC1 ICC2 ynamic Operating Current ma ma Min. Cycle, uty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1 MHZ, II/O = 0mA ISB ma CE1 = VIH or CE2 =VIL ISB1 Standby Power Supply Current µa CE1 VCC - 0.2V VIN 0V ISB µa CE2 0.2V VIN 0V VOL Output Low Voltage V IOL = 2.1mA VOH Output High Voltage V IOH = -1.0mA (August, 2004, Version 1.2) 4 AMIC Technology, Corp.
6 Truth Table Mode CE1 CE2 OE WE I/O Operation Supply Current Standby H X X X High Z ISB, ISB1 X L X X High Z ISB, ISB2 Output isable L H H H High Z ICC, ICC1, ICC2 Read L H L H OUT ICC, ICC1, ICC2 Write L H X L IN ICC, ICC1, ICC2 Note: X = H or L Capacitance (TA = 25 C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pf VIN = 0V CI/O* Input/Output Capacitance 8 pf VI/O = 0V * These parameters are sampled and not 100% tested. (August, 2004, Version 1.2) 5 AMIC Technology, Corp.
7 AC Characteristics (TA = -25 C to + 85 C, VCC = 2.7V to 3.6V) Symbol Parameter LP62S2048A-55LLT LP62S2048A-70LLT Unit Min. Max. Min. Max. Read Cycle trc Read Cycle Time ns taa Address Access Time ns tace1 Chip Enable Access Time CE ns tace2 CE ns toe Output Enable to Output Valid ns tclz1 Chip Enable to Output in Low Z CE ns tclz2 CE ns tolz Output Enable to Output in Low Z ns tchz1 Chip isable to Output in High Z CE ns tchz2 CE ns tohz Output isable to Output in High Z ns toh Output Hold from Address Change ns Write Cycle twc Write Cycle Time ns tcw Chip Enable to End of Write ns tas Address Setup Time ns taw Address Valid to End of Write ns twp Write Pulse Width ns twr Write Recovery Time ns twhz Write to Output in High Z ns tw ata to Write Time Overlap ns th ata Hold from Write Time ns tow Output Active from End of Write ns Notes: tchz1, tchz2, tohz, and twhz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (August, 2004, Version 1.2) 6 AMIC Technology, Corp.
8 Timing Waveforms (1, 2, 4) Read Cycle 1 trc Address taa toh toh OUT (1, 3, 4, 6) Read Cycle 2 CE1 tace1 tclz1 5 tchz1 5 OUT (1, 4, 7, 8) Read Cycle 3 CE2 tace2 tclz2 5 tchz2 5 OUT (August, 2004, Version 1.2) 7 AMIC Technology, Corp.
9 Timing Waveforms (continued) Read Cycle 4 (1) trc Address taa OE toe toh CE1 tolz 5 tace1 tclz1 5 tchz1 5 CE2 tace2 tohz 5 tclz2 5 tchz25 OUT Notes: 1. WE is high for Read Cycle. 2. evice is continuously enabled CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. CE1 is low. 8. Address valid prior to or coincident with CE2 transition high. Write Cycle 1 (6) (Write Enable Controlled) twc Address taw twr 3 CE1 (4) tcw 5 CE2 (4) tas 1 twp 2 WE tw th IN twhz tow OUT (August, 2004, Version 1.2) 8 AMIC Technology, Corp.
10 Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) twc Address taw twr 3 tcw 5 CE1 tas 1 (4) CE2 (4) tcw 5 twp 2 WE tw th IN twhz 7 OUT Notes: 1. tas is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (twp) of a low CE1, a high CE2 and a low WE. 3. twr is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tcw is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (August, 2004, Version 1.2) 9 AMIC Technology, Corp.
11 AC Test Conditions Input Pulse Levels 0.4V to 2.4V Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 TTL TTL CL 30pF CL 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tclz1, tclz2, tohz, tolz, tchz1, tchz2, twhz, and tow ata Retention Characteristics (TA = -25 C to 85 C) Symbol Parameter Min. Max. Unit Conditions VR V CE1 VCC - 0.2V VR2 VCC for ata Retention V CE2 0.2V, ICCR1-5** µa ata Retention Current VCC = 2.0V, CE1 VCC - 0.2V, VIN 0V ICCR2-5** µa VCC = 2.0V, CE2 0.2V, VIN 0V tcr Chip isable to ata Retention Time 0 - ns tr Operation Recovery Time trc - ns tvr VCC Rising Time from ata Retention Voltage to Operating Voltage 5 - ms See Retention Waveform ** LP62S2048A-55LLT/70LLT ICCR: max. 1µA at TA = 0 C to + 40 C (August, 2004, Version 1.2) 10 AMIC Technology, Corp.
12 Low VCC ata Retention Waveform (1) ( CE1 Controlled) ATA RETENTION MOE VCC 2.7V 2.7V tcr VR 2V tvr tr CE1 VIH VIH CE1 VR - 0.2V Low VCC ata Retention Waveform (2) (CE2 Controlled) ATA RETENTION MOE VCC 2.7V 2.7V tcr VR 2V tvr tr CE2 VIL VIL CE2 0.2V (August, 2004, Version 1.2) 11 AMIC Technology, Corp.
13 Ordering Information Part No. Access Time (ns) Operating Current Max. (ma) Standby Current Max. (µa) Package LP62S2048AM-55LLT L SOP LP62S2048AM-55LLTF L Pb-Free SOP LP62S2048AV-55LLT L TSOP LP62S2048AV-55LLTF L Pb-Free TSOP LP62S2048AX-55LLT L TSSOP (Forward) 55 LP62S2048AX-55LLTF L Pb-Free TSSOP LP62S2048AXR-55LLT L TSSOP (Reverse) LP62S2048AXR-55LLTF L Pb-Free TSSOP (Reverse) LP62S2048AU-55LLT L CSP LP62S2048AU-55LLTF L Pb-Free CSP LP62S2048AM-70LLT L SOP LP62S2048AM-70LLTF L Pb-Free SOP LP62S2048AV-70LLT L TSOP LP62S2048AV-70LLTF L Pb-Free TSOP LP62S2048AX-70LLT L TSSOP (Forward) 70 LP62S2048AX-70LLTF L Pb-Free TSSOP LP62S2048AXR-70LLT L TSSOP (Reverse) LP62S2048AXR-70LLTF L Pb-Free TSSOP (Reverse) LP62S2048AU-70LLT L CSP LP62S2048AU-70LLTF L Pb-Free CSP (August, 2004, Version 1.2) 12 AMIC Technology, Corp.
14 Package Information SOP (W.B.) 32L Outline imensions unit: inches/mm e1 ~ E HE L 1 b 16 etail F e1 c s Seating Plane y e A1 A2 A See etail F LE Symbol imensions in inches imensions in mm A Max Max. A Min Min. A ± ±0.13 b c Typ. (0.820 Max.) Typ. (20.83 Max.) E 0.445± ±0.25 e ± ±0.15 e NOM NOM. HE 0.556± ±0.25 L 0.031± ±0.20 LE 0.055± ±0.20 S Max Max. y Max Max. θ 0 ~ 10 0 ~ 10 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. (August, 2004, Version 1.2) 13 AMIC Technology, Corp.
15 Package Information TSOP 32L TYPE I (8 X 20mm) Outline imensions unit: inches/mm e A A E c GAUGE PLANE A1 θ 0.25 BSC L LE H etail "A" etail "A" y S b 0.10(0.004) M Symbol imensions in inches imensions in mm A Max Max. A ± ±0.05 A ± ±0.05 b 0.008± ±0.03 c 0.006± ± ± ±0.10 E 0.315± ±0.10 e TYP TYP. H 0.787± ±0.20 L 0.020± ±0.10 LE TYP TYP. S TYP TYP. Y Max Max. θ 0 ~ 6 0 ~ 6 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. (August, 2004, Version 1.2) 14 AMIC Technology, Corp.
16 Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline imensions (Forward Type) unit: inches/mm 1 32 e 12.0 A2 E c A GAUGE PLANE A BSC L LE θ etail "A" etail "A" 0.10MM SEATING PLANE S b Symbol imensions in inches imensions in mm A Max Max. A Min Min. A ± ±0.05 b 0.008± ±0.03 c 0.006± ±0.008 E 0.315± ±0.10 e TYP TYP ± ± ± ±0.10 L 0.02± ±0.20 LE Min Min. S TYP TYP. y Max Max. θ 0 ~ 6 0 ~ 6 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. (August, 2004, Version 1.2) 15 AMIC Technology, Corp.
17 Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline imensions (Reverse Type) unit: inches/mm LE 1 32 L E GAUGE PLANE A2 A 0.25 BSC A1 θ c e etail "A" SEATING PLANE etail "A" S b 0.10MM Symbol imensions in inches imensions in mm A Max Max. A Min Min. A ± ±0.05 b 0.008± ±0.03 c 0.006± ±0.008 E 0.315± ±0.10 e TYP TYP ± ± ± ±0.10 L 0.02± ±0.20 LE Min Min. S TYP TYP. y Max Max. θ 0 ~ 6 0 ~ 6 Notes: 1. The maximum value of dimension includes end flash. 2. imension E does not include resin fins. 3. imension e1 is for PC Board surface mount pad pitch design reference only. 4. imension S includes end flash. (August, 2004, Version 1.2) 16 AMIC Technology, Corp.
18 Package Information 36L CSP (6 x 8 mm) Outline imensions unit: mm TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (36X) A B C E F G H E E1 e A B C E F G H B e 1 SIE VIEW A // 0.25 C A C 0.20(4X) (0.36) C SEATING PLANE A1 A Symbol imensions in mm MIN. NOM. MAX. A A A E E e b Note: 1. THE BALL IAMETER, BALL PITCH, STAN-OFF & PACKAGE THICKNESS ARE IFFERENT FROM JEEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY ATUM C AN SEATING PLANE ARE EFINE BY THE SPHERICAL CROWNS OF THE SOLER BALLS. 3. IMENSION b IS MEASURE AT THE MAXIMUM. 4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EGE OF THE SOLER BALL AN THE BOY EGE. (August, 2004, Version 1.2) 17 AMIC Technology, Corp.
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DECODER I/O DATA CONTROL CIRCUIT
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Item Previous Current 8ns 110mA 80mA. 10ns 90mA 65mA 12ns 80mA 55mA 15ns 70mA 45mA 8ns 130mA 100mA
Document Title 256Kx16 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial release with
IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POR ASYNCHRONOUS CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
IS65LV256AL IS62LV256AL
32K x 8 LOW VOLTAGE CMOS STATIC RAM MAY 2012 FEATURES High-speed access time: 20, 45 ns Automatic power-down when chip is deselected CMOS low power operation 17 µw (typical) CMOS standby 50 mw (typical)
CMOS SRAM. KM684000B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.
Document Title 512Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft December 7, 1996 Advance 0.1 Revise - Changed Operating current by reticle
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM August 2016 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
Rev. No. History Issue Date Remark
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 15, 2000 Preliminary
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM JULY 2007 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM AUGUST 2009 FEATURES High-speed access time: 10, 12, 15, 20 ns Low active power: 400 mw (typical) Low standby power 250 µw (typical) CMOS standby 55 mw (typical) TTL
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES High-speed access times: 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
IS62WV25616ALL IS62WV25616BLL
IS62WV25616ALL IS62WV25616BLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM MARCH 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JULY 2006 FEATURES High-speed access time: 10, 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS stand-by
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
8K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 0 ns CMOS low power operation mw (typical) CMOS standby 25 mw (typical) operating TTL compatible interface levels Single
A426316B Series 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE.
64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 15, 2000 Preliminary
IS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 10, 12 ns CMOS Low Power Operation 1 mw (typical) CMOS standby 125 mw (typical) operating Fully static operation: no clock
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW VOLTAGE CMOS STATIC RAM June 2005 FEATURES High-speed access times: -- 8, 10, 12, 15 ns Automatic power-down when chip is deselected CMOS low power operation -- 345 mw (max.) operating -- 7
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM MAY 2012 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
IS61WV20488FALL IS61/64WV20488FBLL. 2Mx8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
2Mx8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
64K x 16 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
IS61WV10248ALL IS61WV10248BLL IS64WV10248BLL
1M x 8 HIGH-SPEED CMOS STATIC RAM MARCH 2017 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
IS63LV1024 IS63LV1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT FEATURES High-speed access times: 8, 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
IS62WV6416ALL IS62WV6416BLL
IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access time: 45ns, 55ns CMOS low power operation: 30 mw (typical) operating 15 µw (typical)
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2008 FEATURES High-speed access time: 8, 10 ns Operating Current: 50mA (typ.) Standby Current: 700µA (typ.) Multiple center power and ground pins for greater noise
IS61/64WV5128EFALL IS61/64WV5128EFBLL. 512Kx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
512Kx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC APRIL 2018 KEY FEATURES A0 A17 A18 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV5128EFALL) 2.4V-3.6V () Error Detection
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
28K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY JUNE 2005 FEATURES High-speed access time: 8, 0 ns CMOS low power operation 756 mw (max.) operating @ 8 ns 36 mw (max.) standby @ 8 ns TTL compatible
IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL
1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY MAY 2012 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for
IS61C1024AL IS64C1024AL
IS61C1024AL IS64C1024AL 128K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2015 FEATURES High-speed access time: 12, 15 ns Low active power: 160 mw (typical) Low standby power: 1000 µw (typical) CMOS standby Output
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM Long-term Support NOVEMBER 2016 FEATURES High-speed access time: 45ns, 55ns, 70ns CMOS low power operation 36 mw (typical)
IS62C10248AL IS65C10248AL
IS62C10248AL IS65C10248AL 1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005 FEATURES IS61C6416AL and High-speed access time: 12 ns, 15ns Low Active Power: 175 mw (typical) Low Standby Power: 1 mw (typical) CMOS standby and High-speed
IS61WV102416FALL IS61/64WV102416FBLL. 1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES High-speed access time: 8, 10 ns High-performance, low-power CMOS process TTL compatible interface levels Single power supply VDD 3.3V ± 5%
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
IS62/65WV2568DALL IS62/65WV2568DBLL
IS62/65WV2568DALL IS62/65WV2568DBLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating
IS61WV10248EDBLL IS64WV10248EDBLL
1M x 8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEBRUARY 2013 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
IS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
IS61WV10248EEALL IS61/64WV10248EEBLL. 1Mx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM OCTOBER 2018
1Mx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC OCTOBER 2018 KEY FEATURES High-speed access time: 8ns, 10ns, 20ns Single power supply 1.65V-2.2V (IS61WV10248EEALL) 2.4V-3.6V () Error Detection and Correction
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM DEMBER 00 FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical)
IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES High-speed access time: 35, 45, 55 ns CMOS low power operation 30 mw (typical) operating 6 µw (typical) CMOS standby TTL compatible interface
IS61C25616AL IS61C25616AS IS64C25616AL IS64C25616AS
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) High-speed access time: 10ns, 12 ns Low Active Power: 150 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby LOW POR:
IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
IS61WV2568EDBLL IS64WV2568EDBLL
ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
IS61WV25616ALL/ALS IS61WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) High-speed access time: 8, 10, 20 ns Low Active Power: 85 mw (typical)
IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION APRIL 2008 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center
Very Low Power/Voltage CMOS SRAM 1M X 16 bit DESCRIPTION. SPEED (ns) 55ns : 3.0~3.6V 70ns : 2.7~3.6V BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 1M X 16 bit (Dual CE Pins) FEATURES operation voltage : 27~36V Very low power consumption : = 30V C-grade: 45mA (@55ns) operating current I -grade: 46mA (@55ns) operating
IS62C5128BL, IS65C5128BL
512K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2011 FEATURES High-speed access time: 45ns Low Active Power: 50 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby TTL compatible interface levels Single
Very Low Power/Voltage CMOS SRAM 512K X 16 bit DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) 55ns : 3.0~5.5V 70ns : 2.7~5.5V
FEATURES Wide operation voltage : 24~55V Very low power consumption : = 30V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade:
IS62C51216AL IS65C51216AL
IS62C51216AL IS65C51216AL 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
IS62WV25616EALL/EBLL/ECLL IS65WV25616EBLL/ECLL. 256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM JANUARY 2018
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2018 KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current:
IS62WV102416GALL/BLL IS65WV102416GALL/BLL. 1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM. FUNCTIONAL Block Diagram NOVEMBER 2017
1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM NOVEMBER 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
IS62WV102416FALL/BLL IS65WV102416FALL/BLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM MARCH 2018
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
2M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 2,097,152-bit high-speed Static Random Access Memory organized as 128K(256) words
4M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 4,194,304-bit high-speed Static Random Access Memory organized as 256K(512) words
IS66WV51216DALL IS66/67WV51216DBLL
8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM FEATURES High-speed access time: 70ns (IS66WV51216DALL, ) 55ns () CMOS low power operation Single power supply Vdd = 1.7V-1.95V (IS66WV51216DALL)
Distributed by: www.jameco.com 1-00-31-4242 The content and copyrights of the attached material are the property of its owner. FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption :
16M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr. 15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 16,789,216-bit high-speed Static Random Access Memory organized as 1M(2M) words