A426316B Series 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE.
|
|
- Alexina Ward
- 5 years ago
- Views:
Transcription
1 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 15, 2000 Preliminary 1.0 Final version release September 29, 2003 Final (September, 2003, Version 1.0) AMIC Technology, Corp.
2 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Features Organization: 65,536 words X 16 bits Part Identification: - A426316B - A426316B-L (with self-refresh mode) High speed - 30/35/40 ns access time - 16/18/20 ns column address access time - 10/11/12 ns CAS access time Low power consumption - Operating: 75mA (-30 max) - Standby: 3 ma (TTL) Separate CAS (, ) for byte selection Self refresh mode 256 refresh cycles, 4 ms refresh interval Read-modify-write, -only, CAS -before-, Hidden refresh capability TTL-compatible, three-state I/O JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package Single 5V power supply/built-in VBB generator Pin Configuration SOJ TSOP Pin Descriptions VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC NC A0 A1 A2 A3 VCC A426316BS 40 VSS VCC 39 I/O0 38 I/O14 I/O1 37 I/O13 I/O2 36 I/O12 I/O3 35 VSS VCC 34 I/O11 I/O4 33 I/O10 I/O5 32 I/O9 I/O6 31 I/O8 I/O7 30 NC 29 NC 28 NC NC 25 A7 NC 24 A6 A0 23 A5 A1 22 A4 A2 21 VSS A3 VCC A426316BV VSS I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC A7 A6 A5 A4 VSS Symbol A0 A7 I/O0 - VCC VSS Description Address Inputs Data Input/Output Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable +5V Power Supply Ground NC No Connection (September, 2003, Version 1.0) 1 AMIC Technology, Corp.
3 Selection Guide Symbol Description Unit trac Maximum Access Time ns taa Maximum Column Address Access Time ns tcac Maximum CAS Access Time ns ta Maximum Output Enable ( ) Access Time ns trc Minimum Read or Write Cycle Time ns tpc Minimum EDO Page Mode Cycle Time ns ICC1 Maximum Operating Current ma ICC6 Maximum CMOS Standby Current ma Functional Description The A426316B is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 16 bits. The A426316B is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The A426316B features a high speed page mode operation in which high speed read, write and read-write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe ( and ) which acts as an output enable independent of. Very EDO and to output access time eases system design. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 12/14/15 ns. The A426316B is best suited for graphics, digital signal processing and high performance peripherals. The A426316B is available in JEDEC standard 40-pin plastic SOJ package and 40/44 TSOP type II package. (September, 2003, Version 1.0) 2 AMIC Technology, Corp.
4 Block Diagram VCC VSS REFRESH CONTROLLER Y0 - Y7 COLUMN DECODER SENSE AMP UPPER BYTE DATA I/O BUFFER I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 256 X 16 I/O7 CLOCK GENERATOR CLOCK GENERATOR A0 A1 A2 A3 A4 A5 A6 A7 ADDRESS BUFFERS X0 - X7 ROW DECODER X 256 X 16 ARRAY LOR BYTE DATA I/O BUFFER I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLOCK GENERATOR CLOCK GENERATOR CLOCK GENERATOR SUBSTRATE BIAS GENERATOR Recommended Operating Conditions (Ta = 0 C to +70 C) Symbol Description Min. Typ. Max. Unit VCC Supply Voltage V VSS V VIH Input Voltage VCC + 1 V VIL V (September, 2003, Version 1.0) 3 AMIC Technology, Corp.
5 Truth Table Function Address I/Os Notes Standby H H H X X X High-Z Read: Word L L L H L Row/Col. Data Out Read: Lower Byte L H L H L Row/Col. I/O0-7 = Data Out I/O8-15 = High-Z Read: Upper Byte L L H H L Row/Col. I/O0-7 = High-Z I/O8-15 = Data Out Write: Word(Early) L L L L X Row/Col. Data In Write: Lower Byte(Early) L H L L X Row/Col. I/O0-7 = Data In I/O8-15 = X Write: Upper Byte(Early) L L H L X Row/Col. I/O0-7 = X I/O8-15 = Data In Read-Write L L L L H Row/Col. Data Out Data In 1.2 EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles L L H H Row/Col. Col. Data Out Data Out 2 2 EDO-Page-Mode Write(Early) -First cycle -Subsequent Cycles L L L L X X Row/Col. Col. Data In Data In 1 1 EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles L L L H L H Row/Col. Col. Data In Data In 1, 2 1, 2 Hidden Refresh Read L L L H L Row/Col. Data Out 2 Hidden Refresh Write L L L L X Row/Col. Data In High-Z 1 -Only Refresh L H H X X Row High-Z CBR Refresh L L X X X High-Z 3 Self Refresh (L-ver only) L L X X X High-Z Note: 1. Byte Write may be executed with either or active. 2. Byte Read may be executed with either or active. 3. Only one CAS signal ( or ) must be active. (September, 2003, Version 1.0) 4 AMIC Technology, Corp.
6 Absolute Maximum Ratings* Input Voltage (Vin) V to +7.0V Output Voltage (Vout) V to +7.0V Power Supply Voltage (VCC) V to +7.0V Operating Temperature (TOPR) C to +70 C Storage Temperature (TSTG) C to +150 C Soldering Temperature X Time (TSLODER) C X 10sec Power Dissipation (PD) W Short Circuit Output Current (Iout) mA Latch-up Current mA *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) Symbol Parameter Unit Test Conditions Notes Min. Max. Min. Max. Min. Max. IIL IOL Input Leakage Current Output Leakage Current µa 0V Vin +5.5V Pins not under test = 0V µa DOUT disabled, 0V Vout +5.5V ICC1 Operating Current ma,, Address cycling trc = min. 1, 2 ICC2 TTL Standby Power Supply Current ma = CAS VIH All other inputs VSS ICC3 Refresh Current ma cycling, 1 ( only Refresh) = = VIH, trc = min. ICC4 EDO Page Mode Current ma = VIL,, Address cycling tpc = min. 1, 2 ICC5 Refresh Current ( CAS -before ma,, cycling trc = min. 1 Refresh ) ICC6 CMOS Standby Power Supply Current ma = CAS VCC - 0.2V All other inputs VSS ICC7 Self Refresh Mode Current ma = CAS VSS + 0.2V All other inputs VSS VOH Output High Voltage V IOUT = -5.0mA VOL Output Low Voltage V IOUT = 4.2mA (September, 2003, Version 1.0) 5 AMIC Technology, Corp.
7 AC Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) # Std Symbol Parameter Unit Notes Min. Max. Min. Max. Min. Max. 1 trc Random Read or Write Cycle Time ns 2 trp Precharge Time ns 3 t Pulse Width 30 75K 35 75K 40 75K ns 4 tcas CAS Pulse Width ns 5 trcd to CAS Delay Time ns 6 6 trad to Column Address Delay Time ns 7 7 trsh CAS to Hold Time ns 8 tcsh CAS Hold Time ns 9 tcrp CAS to Precharge Time ns 10 tasr Row Address Setup Time ns 11 trah Row Address Hold Time ns tt Transition Time (Rise and Fall) ns 4, 5 tref Refresh Period ms 3 12 tclz CAS to Output in Low Z ns 8 13 trac Access Time from ns 6,7 14 tcac Access Time from CAS ns 6, taa Access Time from Column Address ns 7, tar Column Address Hold Time from ns 17 trcs Read Command Setup Time ns (September, 2003, Version 1.0) 6 AMIC Technology, Corp.
8 AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) # Std Symbol Parameter Unit Notes Min. Max. Min. Max. Min. Max. 18 trch Read Command Hold Time ns 9 19 trrh Read Command Hold Time Reference to ns 9 20 tral Column Address to Lead Time ns 21 tcoh Output Hold After CAS Low ns 22 tods Output Disable Setup Time ns 23 toff Output Buffer Turn-Off Delay Time ns 8, tasc Column Address Setup Time ns 25 tcah Column Address Hold Time ns 26 trps Precharge Setup Time ns 27 twcs Write Command Setup Time ns twch Write Command Hold Time ns twcr Write Command Hold Time to ns 30 twp Write Command Pulse Width ns 31 trwl Write Command to Lead Time ns 32 tcwl Write Command to CAS Lead Time ns 33 tds Data-in setup Time ns tdh Data-in Hold Time ns tdhr Data-in Hold Time to ns 36 trmw Read-Modify-Write Cycle Time ns 37 trwd to Delay Time (Read-Modify-Write) ns 11 (September, 2003, Version 1.0) 7 AMIC Technology, Corp.
9 AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) # Std Symbol Parameter Unit Notes Min. Max. Min. Max. Min. Max. 38 tcwd CAS to Delay Time (Read-Modify-Write) 39 tawd Column Address to Delay Time (Read-Modify-Write) ns ns ts Pulse Width (Self Refresh Mode) µs 41 tcpn CAS Precharge Time ( CAS before ) K K K ns 42 tpc Read or Write Cycle Time (EDO Page) ns tcpa Access Time from CAS Precharge (EDO Page) ns tcp CAS Precharge Time (EDO Page) ns 45 tprm EDO Page Mode RMW Cycle Time ns 46 tcrw EDO Page Mode CAS Pulse Width (RMW) ns 47 tp Pulse Width (EDO Page) 30 75K 35 75K 40 75K ns 48 tcsr CAS Setup Time ( CAS -before- ) ns 3 49 tchr CAS Hold Time ( CAS -before- ) ns 3 50 trpc to CAS Precharge Time ns ( CAS -before- ) 51 troh Hold Time Reference to ns 52 ta Access Time ns 53 td to Data Delay ns 54 tz Output Buffer Turn-off Delay from ns 8 (September, 2003, Version 1.0) 8 AMIC Technology, Corp.
10 AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) # Std Symbol Parameter Unit Notes Min. Max. Min. Max. Min. Max. 55 th Command Hold Time ns 56 tcpt CAS Precharge Time ( CAS -before- Counter Test) ns Notes: 1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. 3. An initial pause of 200µs is required after power-up followed by any 8 cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- initialization cycles instead of 8 cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8ms). 4. AC Characteristics assume tt = 3ns. All AC parameters are measured with a load equivalent to one TTL loads and 50pF, VIL (min.) GND and VIH (max.) VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the trcd (max.) limit insures that trac (max.) can be met. trcd (max.) is specified as a reference point only. If trcd is greater than the specified trcd (max.) limit, then access time is controlled exclusively by tcac. 7. Operation within the trad (max.) limit insures that trac (max.) can be met. trad (max.) is specified as a reference point only. If trad is greater than the specified trad (max.) limit, then access time is controlled exclusively by taa. 8. Assumes three state test load (5pF and a 380Ω Thevenin equivalent). 9. Either trch or trrh must be satisfied for a read cycle. 10. toff (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. twcs, twch, trwd, tcwd and tawd are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs twcs (min.) and twch twch (min.), the cycle is an early write cycle and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If trwd trwd (min.), tcwd tcwd (min.) and tawd tawd (min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. These parameters are referenced to and leading edge in early write cycles and to leading edge in read-modify-write cycles. 13. Access time is determined by the longer of taa or tcac or tcpa. 14. tasc tcp to achieve tpc (min.) and tcpa (max.) values. 15. These parameters are sampled and not 100% tested. (September, 2003, Version 1.0) 9 AMIC Technology, Corp.
11 Word Read Cycle trc(1) t(3) tcsh(8) trcd(5) trsh(7) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Address Column Address tar(16) trcs(17) trch(18) trrh(19) troh(51) ta(52) tcac(14) taa(15) toff(23) trac(13) tz(54) I/O0 ~ High-Z Valid Data-out tclz(12) : High or Low (September, 2003, Version 1.0) 10 AMIC Technology, Corp.
12 Word Write Cycle (Early Write) trc(1) t(3) tcsh(8) trcd(5) trsh(7) tar(16) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Address Column Address twcr(29) tcwl(32) trwl(31) twp(30) twcs(27) twch(28) tdhr(35) I/O0 ~ tds(33) tdh(34) Valid Data-in : High or Low (September, 2003, Version 1.0) 11 AMIC Technology, Corp.
13 Word Write Cycle (Late Write) trc(1) t(3) tcsh(8) trcd(5) trsh(7) tar(16) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Address Column Address tcwl(32) trwl(31) twcr(29) twp(30) td(54) th(55) tdhr(35) tds(33) tdh(34) I/O0 ~ High-Z Vaild Data-in : High or Low (September, 2003, Version 1.0) 12 AMIC Technology, Corp.
14 Word Read-Modify-Write Cycle trwc(36) t(3) tcsh(8) trcd(5) trsh(7) tar(16) trad(6) tasr(10) trah(11) A0 ~ A7 Row Address Column Address tawd(39) trcs(17) trwd(37) tcwd38) tcwl(32) trwl(31) ta(52) tz(54) td(53) twp(30) tcac(14) th(55) taa(15) tds(33) tdh(34) trac(13) I/O0 ~ High-Z tclz(12) Data-out Data-in : High or Low (September, 2003, Version 1.0) 13 AMIC Technology, Corp.
15 EDO Page Mode Word Read Cycle tp(47) trcd(5) tcsh(8) tcp(44) tpc(42) trsh(7) A0 ~ A7 tcsh(8) tral(20) tar(16) trad(6) tasr(10) trah(11) Row Column Column Column trcs(17) trcs(17) trch(25) trcs(17) trch(25) taa(15) tcpa(43) taa(15) trrh(19) ta(52) ta(52) ts(26) trac(13) tcac(14) tclz(12) tcac(14 ) tcoh(21) tp(41) tz(54) tcac(14) toff(23) tz(54) I/O0 ~ Data-out Data-out Data-out tclz(12) : High or Low (September, 2003, Version 1.0) 14 AMIC Technology, Corp.
16 EDO Page Mode Early Word Write Cycle tp(47) trcd(5) tcsh(8) tpc(42) trsh(7) tcp(44) tcp(44) tral(20) A0 ~ A7 trad(6) tasr(10) trah(11) Row Column Column Column tcwl(32) tcwl(32) tcwl(32) trwl(31) twcs(27) twcs(27) twcs(27) twch(28) twch(28) twch(28) twp(30) twp(30) twp(30) tdh(34) tdh(34) tdh(34) tds(33) tds(33) tds(33) I/O0 ~ Data-in Data-in Data-in : High or Low (September, 2003, Version 1.0) 15 AMIC Technology, Corp.
17 EDO Page Mode Word Read-Modify-Write Cycle tp(47) trcd(5) tcsh(8) tcp(44) tpcm(45) tcp(44) trsh(7) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Column Column Column tcwl(32) tcwl(32) tcwl(32) trwd(37) trwl(31) trcs(17) tcwd(38) tcwd(38) tcwd(38) twp(30) twp(30) twp(30) tawd(39) tawd(39) tawd(39) troh(51) ta(52) ta(52) ta(52) th(55) td(53) td(53) td(53) tcac(14) tcpa(43) tcpa(43) taa(15) taa(15) taa(15) tz(54) tz(54) tz(54) I/O0 ~ High-Z trac(13) tds(33) tdh(34) tds(33) tclz(12) tclz(12) tclz(12) Data-out Data-in Data-in Data-out tdh(34) tds(33) Data-in Data-out tdh(34) : High or Low (September, 2003, Version 1.0) 16 AMIC Technology, Corp.
18 Only Refresh Cycle trc(1) t(3) trpc(50) tasr(10) trah(11) A0 ~ A7 Row Note:, = Don't care. : High or Low CAS Before Refresh Cycle trc(1) t(3) trpc(50) tchr(49) tcpn(41) tcsr(48) I/O0 ~ toff(23) High-Z Note:,, A0 ~ A7 = Don't care. : High or Low (September, 2003, Version 1.0) 17 AMIC Technology, Corp.
19 Timing Waveform of CAS -before- Refresh Counter Test Cycle t (3) trp (2) trsh (7) CAS tcsr (48) tchr (49) tcpt (56) tcas (4) tral (20) tcah (25) Address I/O Col Address taa (15) tcac (14) tclz (12) toff (23) Data Out trcs (17) trch (18) trrh (19) Read Cycle ta (52) troh (53) tcwl(32) trwl(31) twcs(27) twp(30) twch(28) Write Cycle I/O tds (33) Data In tdh (34) trcs (17) tawd(39) tcwd(38) twp (30) tcwl(32) Read-Write Cycle tclz (12) tcac (14) ta(52) taa (15) td (53) tz(54) tds (33) tdh (34) I/O Data Out Data In (September, 2003, Version 1.0) 18 AMIC Technology, Corp.
20 Hidden Refresh Cycle (Word Read) trc(1) trc(1) t(3) t(3) tar(16) trcd(5) trsh(7) tchr(49) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Column trcs(17) trrh(19) taa(15) tcac(14) toff(23) tclz(12) trac(13) I/O0 ~ High-Z Valid Data-out : High or Low (September, 2003, Version 1.0) 19 AMIC Technology, Corp.
21 Hidden Refresh Cycle (Early Word Write) trc(1) trc(1) t(3) t(3) tar(16) trcd(5) trsh(7) tchr(49) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Column twcs(27) twch(28) twp(30) tds(33) tdh(34) I/O0 ~ Valid Data-in : High or Low (September, 2003, Version 1.0) 20 AMIC Technology, Corp.
22 Self Refresh Mode (A426316B-L Only) tpr(2) ts(40) trps(26) trpc(50) tcsr(48) tchs(21) tcpn(41) tasr(10) A0 ~ A7 ROW COL toff(23) I/O0 ~ High-Z Note:, = Don't care. : High or Low Self Refresh Mode. a. Entering the Self Refresh Mode: The A426316B-L Self Refresh Mode is entered by using CAS before cycle and holding and CAS signal low longer than 300µs. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding low after entering the Self Refresh Mode. It does not depend on CAS being high or low after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A426316B exits the Self Refresh Mode when the signal is brought high. (September, 2003, Version 1.0) 21 AMIC Technology, Corp.
23 Capacitance 15 (f = 1MHz, Ta = Room Temperature, VCC = 5V ± 10%) Symbol Signals Parameter Max. Unit Test Conditions CIN1 A0 A7 5 pf Vin = 0V CIN2,, Input Capacitance 7 pf Vin = 0V,, CI/O I/O0 - I/O Capacitance 7 pf Vin = Vout = 0V Ordering Codes Package\ Access Time 30ns 35ns 40ns Self-Refresh 40L SOJ (400 mil) A426316BS-30 A426316BS-35 A426316BS-40 No 40/44L TSOP type II (400mil) A426316BV-30 A426316BV-35 A426316BV-40 No 40L SOJ (400mil) A426316BS-30L A426316BS-35L A426316BS-40L Yes 40/44L TSOP II (400mil) A426316BV-30L A426316BV-35L A426316BV-40L Yes (September, 2003, Version 1.0) 22 AMIC Technology, Corp.
24 Package Information SOJ 40L Outline Dimensions unit: inches/mm E HE 1 20 D C S Seating Plane b b1 e D y A1 A2 A L θ e1 Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A b b C D E e e HE L S y θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (September, 2003, Version 1.0) 23 AMIC Technology, Corp.
25 Package Information TSOP 40/44L (Type II) Outline Dimensions unit: inches/mm 44 E HE θ L 1 D L1 c S B e D y A1 A2 A L L1 Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A B c D E e BSC 0.80 BSC HE L L S y θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (September, 2003, Version 1.0) 24 AMIC Technology, Corp.
Rev. No. History Issue Date Remark
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 15, 2000 Preliminary
More information1M x 16Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION
KM46C0B, KM46C00B KM46V0B, KM46V00B M x 6Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of,048,576 x 6 bit Fast Page Mode s. Fast Page Mode offers high speed random access of memory
More informationKM44C1000D, KM44V1000D
1M x 4Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 1,048,576 x 4bit Fast Page Mode s. Fast Page Mode offers high speed random access of memory cells within the same row. Power
More informationFEATURES Row Access Time Column Access Time Random Read/Write Cycle Time Page Mode Cycle Time
E DRAM DIMM 16MX72 Nonbuffered EDO DIMM based on 8MX8, 4K Refresh, 3.3V DRAMs GENERAL DESCRIPTION The Advantage E is a JEDEC standard 16MX72 bit Dynamic RAM high density memory module. The Advantage EDC1672-8X8-66VNBS4
More informationFEATURES. EDC X4-66VB8 DRAM DIMM 32MX72 Buffered EDO DIMM based on 16MX4, 8K Refresh, 3.3V DRAMs
EDC3272-16X4-66VB8 DRAM DIMM 32MX72 Buffered EDO DIMM based on 16MX4, 8K Refresh, 3.3V DRAMs GENERAL DESCRIPTION The Advantage EDC3272-16X4-66VB8 is a JEDEC standard 32MX72 bit Dynamic RAM high density
More informationKM416C4004C, KM416C4104C
4M x 16bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 16 bit Extended Data Out Mode s. Extended Data Out Mode offers high speed random access of memory cells within
More informationTMS418160A BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY
This data sheet is applicable to TMS418160As symbolized by Revision E and subsequent revisions as described in the device symbolization section. Organization...1048576 by 16 Bits Single 5-V Power Supply
More informationAS4C256K16E0. 5V 256K 16 CMOS DRAM (EDO) Features. Pin designation. Pin arrangement. Selection guide
5V 256K 16 CMOS DRAM (EDO) Features Organization: 262,144 words 16 bits High speed - 30/35/50 ns access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time Low power consumption
More informationRev. No. History Issue Date Remark
8K X 8 BIT CMOS SRAM Document Title 8K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 9, 2004 Preliminary 1.0 Remove non-pb-free package type July 3, 2006
More informationTMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P WORD BY 16-BIT HIGH-SPEED DRAMS
Organization...1048576 16 Single Power Supply (5 V or 3.3 V) Performance Ranges: ACCESS ACCESS ACCESS TMS416160, TMS416160P, TMS418160, TMS418160P READ OR TIME TIME TIME RITE trac tcac taa CYCLE MAX MAX
More informationRev. No. History Issue Date Remark
32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 2, 2001 Preliminary 0.1 Add ultra temp grade and 28-pin DIP package
More informationUM61512A Series 64K X 8 BIT HIGH SPEED CMOS SRAM. Features. General Description. Pin Configurations UM61512AV UM61512A
Series 64K X 8 BIT HIGH SPEE CMOS SRAM Features Single +5V power supply Access times: 15/20/25ns (max.) Current: Operating: 160mA (max.) Standby: 10mA (max.) Full static operation, no clock or refreshing
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C64 8K x 8 LOW POR CMOS STATIC RAM FEATURES CMOS low power operation 400 mw (max.) operating 25 mw (max.) standby Automatic power-down when chip is deselected TTL compatible interface levels Single
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW VOLTAGE CMOS STATIC RAM June 2005 FEATURES High-speed access times: -- 8, 10, 12, 15 ns Automatic power-down when chip is deselected CMOS low power operation -- 345 mw (max.) operating -- 7
More informationRev. No. History Issue Date Remark
256K X 8 BIT LOW VOLTAGE CMOS SRAM ocument Title 256K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue June 24, 2002 Preliminary 0.1 Change VCC range from
More informationLY62L K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 1.1 Adding PKG type : 32 SOP Mar.3.2006 Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR May.14.2007
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
8K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 0 ns CMOS low power operation mw (typical) CMOS standby 25 mw (typical) operating TTL compatible interface levels Single
More informationIDT CMOS Static RAM 1 Meg (256K x 4-Bit)
CMOS Static RAM 1 Meg (256K x 4-Bit) IDT71028 Features 256K x 4 advanced high-speed CMOS static RAM Equal access and cycle times Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable
More informationCMOS STATIC RAM 1 MEG (128K x 8-BIT)
CMOS STATIC RAM 1 MEG (12K x -BIT) IDT71024 Integrated Device Technology, Inc. FEATURES: 12K x advanced high-speed CMOS static RAM Commercial (0 to 70 C), Industrial (-40 to 5 C) and Military (-55 to 125
More information64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005 FEATURES IS61C6416AL and High-speed access time: 12 ns, 15ns Low Active Power: 175 mw (typical) Low Standby Power: 1 mw (typical) CMOS standby and High-speed
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES High-speed access times: 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
128K x 8 LOW POR CMOS STATIC RAM DECEMBER 2003 FEATURES High-speed access time: 35, 70 ns Low active power: 450 mw (typical) Low standby power: 150 µw (typical) CMOS standby Output Enable (OE) and two
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2008 FEATURES High-speed access time: 8, 10 ns Operating Current: 50mA (typ.) Standby Current: 700µA (typ.) Multiple center power and ground pins for greater noise
More informationLY K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0. Initial Issue Jul.25.2004 Rev. 2.0. Revised Vcc Range(Vcc=4.5~5.5V => 2.7~5.5V) May.4.2005 Rev. 2.1. Revised ISB1 May.13.2005 Rev. 2.2 Adding
More informationA23W9308. Document Title 524,288 X 8 BIT CMOS MASK ROM. Revision History. Rev. No. History Issue Date Remark
Preliminary 524,288 X 8 BIT CMOS MASK ROM Document Title 524,288 X 8 BIT CMOS MASK ROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 2, 1999 Preliminary PRELIMINARY (November,
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM AUGUST 2009 FEATURES High-speed access time: 10, 12, 15, 20 ns Low active power: 400 mw (typical) Low standby power 250 µw (typical) CMOS standby 55 mw (typical) TTL
More information3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Description OBSOLESCENCE ORDER 71V016SA. Row / Column Decoders. Sense Amps and Write Drivers
3.3V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1 Features 4K x 1 advanced high-speed CMOS Static RAM Commercial ( to +7 C) and Industrial ( 4 C to +5 C) Equal access and cycle times Commercial and Industrial:
More informationIS61C25616AL IS61C25616AS IS64C25616AL IS64C25616AS
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) High-speed access time: 10ns, 12 ns Low Active Power: 150 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby LOW POR:
More informationHY62WT08081E Series 32Kx8bit CMOS SRAM
32Kx8bit CMOS SRAM Document Title 32K x8 bit 2.7~5.5V Low Power Slow SRAM Revision History Revision No History Draft Date Remark 00 Initial Feb.05.2001 Preliminary 01 Revised Feb.13.2001 Final - Change
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JULY 2006 FEATURES High-speed access time: 10, 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS stand-by
More informationDESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C1024 128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES High-speed access time: 35, 45, 55, 70 ns Low active power: 450 mw (typical) Low standby power: 500 µw (typical) CMOS standby Output Enable () and
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 10, 12 ns CMOS Low Power Operation 1 mw (typical) CMOS standby 125 mw (typical) operating Fully static operation: no clock
More informationLY K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0. Initial Issue Jul.25.2004 Rev. 2.0. Revised Vcc Range(Vcc=4.5~5.5V => 2.7~5.5V) May.4.2005 Rev. 2.1. Revised ISB1 May.13.2005 Rev. 2.2 Adding
More informationHY62256A Series 32Kx8bit CMOS SRAM
32Kx8bit CMOS SRAM DESCRIPTION The HY62256A is a high-speed, low power and 32,786 x 8-bits CMOS Static Random Access Memory fabricated using Hyundai's high performance CMOS process technology. The HY62256A
More information3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
3.3V CMOS Static RAM Meg (2K x 1-Bit) IDT71V1S IDT71V1L Features 2K x 1 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle times Commercial and
More informationLY62L K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Feb.24.2010 Rev. 1.1 Revised PACKAGE OUTLINE DIMENSION in page 10 May.7.2010 Deleted WRITE CYCLE Notes : 1. WE#, CE# must be high
More information10/February/07, v.1.0 Alliance Memory Inc. Page 1 of 13
FEATURES Access time : 55ns Low power consumption: Operating current :20mA (TYP.) Standby current : 20mA(TYP.)L Version 1µ A (TYP.) LL-version Single 2.7V ~ 3.6V power supply Fully static operation Tri-state
More informationIDT71V424S/YS/VS IDT71V424L/YL/VL
.V CMOS Static RAM Meg (K x -Bit) IDT1V2S/YS/VS IDT1V2L/YL/VL Features K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times Commercial
More informationIS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM JULY 2007 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
More informationCMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S
CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S Features 128K x 8 advanced high-speed CMOS static RAM Commercial (0 C to +70 C), Industrial ( 40 C to +85 C) Equal access and cycle times Commercial and Industrial:
More informationRevision No History Draft Date Remark. 10 Initial Revision History Insert Jul Final
128Kx8bit CMOS SRAM Document Title 128K x8 bit 5.0V Low Power CMOS slow SRAM Revision History Revision No History Draft Date Remark 10 Initial Revision History Insert Jul.14.2000 Final 11 Marking Information
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW POR CMOS STATIC RAM FEATURES Access time: 45, 70 ns Low active power: 200 mw (typical) Low standby power 250 µw (typical) CMOS standby 28 mw (typical) TTL standby Fully static operation: no
More informationIS65LV256AL IS62LV256AL
32K x 8 LOW VOLTAGE CMOS STATIC RAM MAY 2012 FEATURES High-speed access time: 20, 45 ns Automatic power-down when chip is deselected CMOS low power operation 17 µw (typical) CMOS standby 50 mw (typical)
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
64K x 16 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
More informationUTRON UT K X 8 BIT LOW POWER CMOS SRAM
FEATURES GENERAL DESCRIPTION Access time : 35/70ns (max) Low power consumption: Operating : 60/40 ma (typical) Standby : 3mA (typical) normal ua (typical) L-version 1uA (typical) LL-version Single 5V power
More informationIS62WV102416ALL IS62WV102416BLL IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POR ASYNCHRONOUS CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
More informationCMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
Integrated Device Technology, Inc. CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM IDT6178S FEATURES: High-speed Address to Valid time Military: 12/15/20/25ns Commercial: 10/12/15/20/25ns (max.) High-speed
More information16 Meg FPM DRAM AS4LC4M4. 4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT ACTIVE POWER DISSIPATION PERFORMANCE RANGE
4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883 FEATURES Fast Page Mode Operation CAS\-before-RAS\ Refresh Capability RAS\-only and
More informationI/O1 ~ I/O8 I/O9 ~ I/O16 I/O9 ~ I/O16 I/O1 ~ I/O8
Document Title 64Kx16 Bit High-Speed CMOS Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release
More informationPart No. Clock Frequency Power Organization Interface Package. Normal. 4Banks x 2Mbits x8. Low power
4 Banks x 2M x 8Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V658020A is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and
More informationIDT71V016SA/HSA. 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)
.V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1SA/HSA Features 4K x 1 advanced high-speed CMOS Static RAM Equal access and cycle times Commercial: 1//1/2 Industrial: /1/2 One Chip Select plus one Output
More informationJANUARY/2008, V 1.0 Alliance Memory Inc. Page 1 of 11
1024K X 8 BIT SUPER 512K LOW POWER X8BITCMOS LOW SRAM FEATURES Fast access time : 55ns Low power consumption: Operating current : 30mA (TYP.) Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V
More informationPart No. Clock Frequency Power Organization Interface Package. Normal. Low power
4 Banks x 2M x 8Bit Synchronous DRAM DESCRIPTION The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and
More informationPart No. Clock Frequency Power Organization Interface Package. Normal. Low power
4 Banks x 4M x 4Bit Synchronous DRAM DESCRIPTION The Hynix HY57V654020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and
More informationPRELIMINARY PRELIMINARY
Document Title 256Kx4 Bit (with ) High-Speed CMOS Static RAM(5.0V Operating). Revision History Rev. No. History Draft Data Remark Rev. 0.0 Rev. 0.1 Rev. 0.2 Initial release with Preliminary. Current modify
More informationRevision No. History Draft Date Remark. 0.1 Initial Draft Jan Preliminary. 1.0 Final Version Apr. 2007
64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O Document Title 4Bank x 1M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Jan. 2007 Preliminary 1.0
More informationIS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
More informationAuto refresh and self refresh refresh cycles / 64ms. Programmable CAS Latency ; 2, 3 Clocks
4 Banks x 1M x 16Bit Synchronous DRAM DESCRIPTION The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and
More informationHY57V281620HC(L/S)T-S
4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density
More informationIS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
More informationPart No. Clock Frequency Power Organization Interface Package. Normal. Low power
4 Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high
More informationDECODER I/O DATA CONTROL CIRCUIT
1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2006 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation: 36 mw (typical) operating 12 µw (typical) CMOS standby TTL compatible
More informationIS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM MAY 2012 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
More informationHY57V561620C(L)T(P)-S
4 Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density
More informationIS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
More informationI/O1 ~ I/O8 I/O9 ~ I/O16 I/O9 ~ I/O16 I/O1 ~ I/O8
Document Title 64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release
More informationHY57V561620B(L/S)T 4 Banks x 4M x 16Bit Synchronous DRAM
4 Banks x 4M x 16Bit Synchronous DRAM Doucment Title 4 Bank x 4M x 16Bit Synchronous DRAM Revision History Revision No. History Draft Date Remark 1.4 143MHz Speed Added July 14. 2003 This document is a
More informationIS61C1024AL IS64C1024AL
IS61C1024AL IS64C1024AL 128K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2015 FEATURES High-speed access time: 12, 15 ns Low active power: 160 mw (typical) Low standby power: 1000 µw (typical) CMOS standby Output
More informationIS63LV1024 IS63LV1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT FEATURES High-speed access times: 8, 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise
More informationIS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM DEMBER 00 FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical)
More informationRevision No. History Draft Date Remark. 0.1 Initial Draft Jul Preliminary. 1.0 Release Aug. 2009
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Jul. 2009 Preliminary 1.0
More informationRevision No. History Draft Date Remark. 1.0 First Version Release Dec Corrected PIN ASSIGNMENT A12 to NC Jan. 2005
128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 1.0 First Version Release Dec. 2004 1.1 1.
More informationLY V 128K X 16 BIT HIGH SPEED CMOS SRAM
Y6112816 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Aug.12.2007 Rev. 1.1 Apr. 17.2009 Revised TEST CONDITION of ICC Revised FEATURES & ORDERING INFORMATION ead free and green
More informationPart No. Clock Frequency Organization Interface Package
2 Banks x 512K x 16 Bit Synchronous DRAM DESCRIPTION THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory
More informationpower and 32,786 x 8-bits and outputs -2.0V(min.) data fabricated using
查询 HY62256A 供应商 Data Sheet-sram/62256ald1 http://www.hea.com/hean2/sram/62256ald1.htm HY62256A-(I) Series 32Kx8bit CMOS SRAM Description Features The Fully static operation and HY62256A/HY62256A-I Tri-state
More informationSRM2B256SLMX55/70/10
256K-BIT STATIC RAM Wide Temperature Range Extremely Low Standby Current Access Time 100ns (2.7V) 55ns (4.5V) 32,768 Words 8-Bit Asynchronous DESCRIPTION The SRM2B256SLMX is a low voltage operating 32,768
More informationLY61L K X 16 BIT HIGH SPEED CMOS SRAM
Y6125616 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue May.24.2006 Rev. 1.1 Added Extended Grade Jan.22.2007 Rev. 1.2 Added PKG Type : 48-ball 6mm x 8mm TFBGA Jan.30.2007 Rev.
More informationDESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
28K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY JUNE 2005 FEATURES High-speed access time: 8, 0 ns CMOS low power operation 756 mw (max.) operating @ 8 ns 36 mw (max.) standby @ 8 ns TTL compatible
More informationHY5V56D(L/S)FP. Revision History. No. History Draft Date Remark. 0.1 Defined Target Spec. May Rev. 0.1 / Jan
Revision History No. History Draft Date Remark 0.1 Defined Target Spec. May 2003 Rev. 0.1 / Jan. 2005 1 Series 4 Banks x 4M x 16bits Synchronous DRAM DESCRIPTION The HY5V56D(L/S)FP is a 268,435,456bit
More informationHY57V653220C 4 Banks x 512K x 32Bit Synchronous DRAM Target Spec.
4 Banks x 512K x 32Bit Synchronous DRAM Target Spec. DESCRIPTION The Hyundai HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O
More informationIS62C10248AL IS65C10248AL
IS62C10248AL IS65C10248AL 1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
More informationIS62C5128BL, IS65C5128BL
512K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2011 FEATURES High-speed access time: 45ns Low Active Power: 50 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby TTL compatible interface levels Single
More informationLY61L25616A 256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 VCC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current ICC1 on
More informationIS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM August 2016 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
More informationIS62WV6416ALL IS62WV6416BLL
IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access time: 45ns, 55ns CMOS low power operation: 30 mw (typical) operating 15 µw (typical)
More informationDocument Title. Revision History. 32Kx8 bit Low Power CMOS Static RAM. Remark. History. Revision No. Draft Data. Design target. Initial draft 0.
Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data Remark 0.0 Initial draft May 18, 1997 Design target 0.1 First revision - KM62256DL/DLI ISB1 = 100 50µA
More informationHY57V28420A. Revision History. Revision 1.1 (Dec. 2000)
Revision History Revision 1.1 (Dec. 2000) Eleminated -10 Bining product. Changed DC Characteristics-ll. - tck to 15ns from min in Test condition - -K IDD1 to 120mA from 110mA - -K IDD4 CL2 to 120mA from
More informationIS42/45S16100F, IS42VS16100F
512K Words x 16 Bits x 2 Banks 16Mb SDRAM JUNE 2012 FEATURES Clock frequency: IS42/45S16100F: 200, 166, 143 MHz IS42VS16100F: 133, 100 MHz Fully synchronous; all signals referenced to a positive clock
More informationIS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM Long-term Support NOVEMBER 2016 FEATURES High-speed access time: 45ns, 55ns, 70ns CMOS low power operation 36 mw (typical)
More information128Mb F-die SDRAM Specification
128Mb F-die SDRAM Specification Revision 0.2 November. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Revision History Revision 0.0 (Agust, 2003) - First
More information512Mb B-die SDRAM Specification
512Mb B-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) Revision 1.1 August 2004 * Samsung Electronics reserves the right to change products or specification without notice. Revision History
More informationIS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION APRIL 2008 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center
More informationIS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
IS61WV25616ALL/ALS IS61WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) High-speed access time: 8, 10, 20 ns Low Active Power: 85 mw (typical)
More information256Mb E-die SDRAM Specification
256Mb E-die SDRAM Specification Revision 1.5 May 2004 * Samsung Electronics reserves the right to change products or specification without notice. Revision History Revision 1.0 (May. 2003) - First release.
More informationIS62/65WV2568DALL IS62/65WV2568DBLL
IS62/65WV2568DALL IS62/65WV2568DBLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating
More informationIS62WV25616ALL IS62WV25616BLL
IS62WV25616ALL IS62WV25616BLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM MARCH 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
More informationIS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
More informationIS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS
More informationIS61/64WV5128EFALL IS61/64WV5128EFBLL. 512Kx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
512Kx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC APRIL 2018 KEY FEATURES A0 A17 A18 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV5128EFALL) 2.4V-3.6V () Error Detection
More informationIS61WV2568EDBLL IS64WV2568EDBLL
ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply
More information