TMS418160A BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY

Transcription

1 This data sheet is applicable to TMS418160As symbolized by Revision E and subsequent revisions as described in the device symbolization section. Organization by 16 Bits Single 5-V Power Supply (± 10% Tolerance) 1024-Cycle Refresh in 16 ms Performance Ranges: ACCESS ACCESS ACCESS READ/ TIME TIME TIME RITE trac tcac taa CYCLE MAX MAX MAX MIN A ns 13 ns 25 ns 90 ns A ns 15 ns 30 ns 110 ns A ns 18 ns 35 ns 130 ns Enhanced Page-Mode Operation ith xcas-before- ( xcbr) Refresh 3-State Unlatched Output Low Power Dissipation High-Reliability Plastic 42-Lead 400-Mil-ide Surface-Mount Small-Outline J-Lead (SOJ) Package (DZ Suffix) Ambient Temperature Range 0 C to 70 C description V DD DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 NC NC NC NC A0 A1 A2 A3 V DD DZ PACKAGE ( TOP VIE ) V SS DQ15 DQ14 DQ13 DQ12 V SS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS A9 A8 A7 A6 A5 A4 V SS The TMS418160A is a bit dynamic random-access memory (DRAM) device organized as words of 16 bits. It employs state-of-the-art technology for high performance, reliability, and low power at low cost. This device features maximum access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS418160A is offered in a 42-lead plastic surface-mount SOJ package (DZ suffix). This package is designed for operation from 0 to 70 C. A[0:9] DQ[0:15] LCAS UCAS NC VDD VSS PIN NOMENCLATURE Inputs Data In / Data Out Lower Column- Strobe Upper Column- Strobe No Internal Connection Output Enable Row- Strobe 5-V Supply Ground rite Enable Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated POST OFFICE BOX 1443 HOUSTON, TEXAS

2 logic symbol 17 A0 18 A1 19 A2 20 A3 23 A4 24 A5 25 A6 26 A7 A8 27 A D10/21D0 20D19/21D9 RAM 1M 16 A LCAS C20[RO] G23/[REFRESH RO] 24[PR DN] C21 G24 & 23C UCAS DQ0 2 3 DQ1 4 DQ2 5 DQ3 7 DQ4 8 DQ5 9 DQ6 10 DQ7 33 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ C21 G34 & 31 Z31 23,21D 25 A,22D 26,27 A,32D 36,37 23C32 24,25EN27 34,25EN37 A, Z26 A, Z36 This symbol is in accordance with ANSI/IEEE Std and IEC Publication POST OFFICE BOX 1443 HOUSTON, TEXAS

3 functional block diagram UCAS LCAS Timing and Control A0 A1 A9 Column- Buffers Row - Buffers Column Decode Sense Amplifiers 256K Array 256K Array 256K Array R o w D e c o d e 256K Array 256K Array 256K Array I/O Buffers 16 of 32 Selection Data- In Reg. Data- Out Reg DQ0 DQ15 10 operation dual xcas Two xcas pins (LCAS and UCAS) are provided to give independent control of the 16 data I/O pins (DQ0 DQ15), with LCAS corresponding to DQ0 DQ7 and UCAS corresponding to DQ8 DQ15. Each xcas going low enables its corresponding DQx pin. In write cycles, data-in setup and hold time (t DS and t DH ) and write-command setup and hold time (t CS, t CL and t CH ) must be satisfied for each individual xcas to ensure writing into the storage cells of the corresponding DQ pins. Different modes of operation for upper and lower bytes in one cycle are not allowed, such as the example shown in Figure 1. UCAS Delayed write LCAS Early write Figure 1. Illegal Dual-xCAS Operation POST OFFICE BOX 1443 HOUSTON, TEXAS

4 enhanced page mode Page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by the maximum low time and the xcas page-mode cycle time used. ith minimum xcas page-cycle time, all columns can be accessed without intervening cycles. Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling edge of. The buffers act as transparent or flow-through latches while xcas is high. The falling edge of the first xcas latches the column addresses. This performance improvement is referred to as enhanced-page mode. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode because data retrieval begins as soon as the column address is valid rather than when xcas transitions low. A valid column address may be presented immediately after t RAH (row-address hold time) has been satisfied, usually well in advance of the falling edge of xcas. In this case, data is obtained after t CAC maximum (access time from xcas low) if t AA maximum (access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time xcas goes high, minimum access time for the next cycle is determined by t CPA. address: A0 A9 Twenty address bits are required to decode each of the storage cell locations. Twelve row-address bits are set up on A0 through A11 and latched onto the chip by. Eight column-address bits are set up on A0 through A7 and latched onto the chip by the first xcas. All addresses must be stable on or before the falling edge of and xcas. is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. xcas is used as a chip select, activating its corresponding output buffer and latching the address bits into the column-address buffers. The column address is latched on the first xcas falling edge with address setup and hold parameters referenced to that edge. In order to latch in a new column address, both xcas pins must be brought high. The column-precharge time (see parameter t CP ) is measured from the last xcas rising edge to the first xcas falling edge of the new cycle. Keeping a column address valid while toggling xcas requires a minimum hold time, t CLCH. During t CLCH, at least one xcas must be brought low before the other xcas is taken high. write enable () Read- or write mode is selected through. A logic high on selects the read mode and a logic low selects the write mode. Data in is disabled when the read mode is selected. hen goes low prior to xcas (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation independent of the state of. This permits early-write operations to be completed with grounded. data in (DQ0 DQ15) Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge of xcas or strobes data into the on-chip data latch. In an early-write cycle, is brought low prior to a xcas falling edge and the data is strobed into the on-chip data latch for the corresponding DQs with setup-and-hold times referenced to this xcas signal. In a delayed-write- or read-modify-write cycle, xcas is already low and the data is strobed in by with setup and hold times referenced to this signal. Also, must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines (see parameter t D ). 4 POST OFFICE BOX 1443 HOUSTON, TEXAS

5 data out (DQ0 DQ15) Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xcas and are brought low. In a read cycle, the output becomes valid after the access-time-interval t CAC (which begins with the negative transition of xcas) as long as t RAC (access time from ) and t AA (access time from column address) are satisfied. The delay time from xcas low to valid data out is measured from each individual xcas to its corresponding DQx pin. output enable () controls the impedance of the output buffers. hen is high, the buffers remain in the high-impedance state. Bringing low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both and xcas to be brought low (until either or xcas is brought high) for the output buffers to go into the low-impedance state. -only refresh A refresh operation must be performed once every 16 ms to retain data. This can be achieved by strobing each of the 1024 rows (A0 A9). A normal read or write cycle refreshes all bits in each row that is selected. A -only operation can be used by holding both xcas at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a -only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding xcas at V IL after a read operation and cycling after a specified precharge period, similar to a -only refresh cycle. The external address is ignored, and the refresh address is generated internally. xcas-before- (xcbr) refresh xcbr refresh is utilized by bringing at least one xcas low earlier than (see parameter t CSR ) and holding it low after falls (see parameter t CHR ). For successive xcbr refresh cycles, xcas can remain low while cycling. The external address is ignored and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs, followed by a minimum of eight initialization cycles, is required after power up to the full V DD level. These eight initialization cycles must include at least one refresh (-only or xcbr) cycle. POST OFFICE BOX 1443 HOUSTON, TEXAS

6 absolute maximum ratings over ambient temperature range (unless otherwise noted) Supply voltage range, V DD V to 7 V Voltage range on any pin (see Note 1) V to 7 V Short-circuit output current ma Power dissipation Ambient temperature range, T A C to 70 C Storage temperature range, T stg C to 125 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT VDD Supply voltage V VSS Supply voltage 0 V VIH High-level input voltage V VIL Low-level input voltage (see Note 2) V TA Ambient temperature 0 70 C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. 6 POST OFFICE BOX 1443 HOUSTON, TEXAS

7 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) VOH PARAMETER High-level output voltage TEST CONDITIONS A A A- 70 MIN MAX MIN MAX MIN MAX IOH = 5 ma V VOL Low-level output voltage IOL = 4.2 ma V II IO ICC1 ICC2 ICC3 Input current (leakage) Output current (leakage) Average read- or write-cycle current Average standby current Average refresh current (-only refresh or xcbr) VDD = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VDD VDD = 5.5 V, xcas high VO = 0 V to VDD, UNIT ± 10 ± 10 ± 10 µa ± 10 ± 10 ± 10 µa VDD = 5.5 V, Minimum cycle ma VIH = 2.4 V ( TTL), After one memory cycle, and xcas high VIH = VDD 0.2 V (CMOS), After one memory cycle, and xcas high VDD = 5.5 V, Minimum cycle, cycling, xcas high ( only), low after xcas low (xcbr) ma ma ma ICC4 Average page current VDD = 5.5 V, tpc = MIN, ma low, xcas cycling For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while = VIL Measured with a maximum of one address change during each page cycle, tpc capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT Ci(A) Input capacitance, A0 A9 5 pf Ci() Input capacitance, 7 pf Ci(RC) Input capacitance, xcas and 7 pf Ci() Input capacitance, 7 pf CO Output capacitance# 7 pf # LCAS and UCAS = VIH to disable outputs NOTE 3: VDD = 5 V ± 10%, and the bias on pins under test is 0 V. POST OFFICE BOX 1443 HOUSTON, TEXAS

8 switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 4) PARAMETER A A A- 70 MIN MAX MIN MAX MIN MAX taa Access time from column address ns tcac Access time from xcas ns tcpa Access time from xcas precharge ns trac Access time from ns ta Access time from ns tclz Delay time, xcas to output in the low-impedance state ns toh Output data hold time from xcas ns toho Output data hold time from ns toff Output buffer turn-off delay from xcas (see Note 5) ns tz Output buffer turn-off delay from (see Note 5) ns NOTES: 4. ith ac parameters, it is assumed that tt = 5 ns. 5. toff and tz are specified when the output is no longer driven. Data-in should not be enabled until one of the applicable maximum specifications is satsified. ac timing requirements (see Note 4) A A A- 70 UNIT MIN MAX MIN MAX MIN MAX trc Cycle time, read ns tc Cycle time, write ns trc Cycle time, read-write ns tpc Cycle time, page-mode read or write (see Note 6) ns tprc Cycle time, page-mode read-write ns tp Pulse duration, active, page mode (see Note 7) ns t Pulse duration, active, nonpage mode (see Note 7) ns Pulse duration, xcas active (see Note 8) ns Pulse duration, (precharge) ns tp Pulse duration, write command ns tasc Setup time, column address ns tasr Setup time, row address ns tds Setup time, data-in (see Note 9) ns trcs Setup time, read command ns tcl Setup time, write command before xcas precharge ns trl Setup time, write command before precharge ns tcs Setup time, write command before xcas active (early-write only) ns Setup time, write before active (CBR refresh only) ns NOTES: 4. ith ac parameters, it is assumed that tt = 5 ns. 6. To assure tpc min, tasc should be to tcp. 7. In a read-write cycle, trd and trl must be observed. 8. In a read-write cycle, tcd and tcl must be observed. 9. Referenced to the later of xcas or in write operations UNIT 8 POST OFFICE BOX 1443 HOUSTON, TEXAS

9 ac timing requirements (see Note 4) (continued) A A A- 70 MIN MAX MIN MAX MIN MAX tcah Hold time, column address ns tdh Hold time, data-in (see Note 9) ns trah Hold time, row address ns trch Hold time, read command referenced to xcas (see Note 10) ns trrh Hold time, read command referenced to (see Note 10) ns tch Hold time, write command during xcas active (early-write only) ns tclch Hold time, xcas low to xcas high ns trhcp Hold time, active from xcas precharge ns th Hold time, command ns troh Hold time, referenced to ns trh Hold time, write after active (CBR refresh only) ns tcp Delay time, xcas precharge ns tad Delay time, column address to write command (read-write operation only) ns tchr Delay time, xcas referenced to (xcbr refresh only) ns tcrp Delay time, xcas precharge to ns tcsh Delay time, active to xcas precharge ns tcsr Setup time, xcas referenced to (xcbr refresh only) ns tcd Delay time, xcas to write command (read-write operation only) ns td Delay time, to data in ns trad Delay time, to column address (see Note 11) ns tral Delay time, column address to precharge ns tcal Delay time, column address to xcas precharge ns trcd Delay time, to xcas (see Note 11) ns C Delay time, precharge to xcas active ns trsh Delay time, xcas active to precharge ns trd Delay time, to write command (read-write operation only) ns Delay time, xcas precharge to write command tcp ns (read-write operation only) tref Refresh time interval ms tt Transition time ns NOTES: 4. ith ac parameters, it is assumed that tt = 5 ns. 9. Referenced to the later of xcas or in write operations 10. Either trrh or trch must be satisfied for a read cycle. 11. The maximum value is specified only to assure access time. UNIT POST OFFICE BOX 1443 HOUSTON, TEXAS

10 PARAMETER MEASUREMENT INFORMATION VTH VDD RL R1 Output Under Test CL = 100 pf (see Note A) Output Under Test CL = 100 pf (see Note A) R2 (a) LOAD CIRCUIT (b) ALTERNATE LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance. DEVICE VDD (V) R1 (Ω) R2 (Ω) VTH (V) RL (Ω ) A Figure 2. Load Circuits for Timing Parameters 10 POST OFFICE BOX 1443 HOUSTON, TEXAS

11 PARAMETER MEASUREMENT INFORMATION trc TMS418160A t tt trcd UCAS LCAS tclch (see Note A) tcrp tcp trad trah tcsh trsh tasr tasc tcal tral Row Column tcah trrh trcs trch tcac (see Note B) toff tclz taa toh DQ0 DQ15 See Note C trac troh Valid Data Out toho tz ta NOTES: A. B. To hold the address latched by the first xcas going low, the parameter tclch must be met. tcac is measured from xcas to its corresponding DQx. C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. D. xcas order is arbitrary. Figure 3. Read-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

12 PARAMETER MEASUREMENT INFORMATION tc t tt trcd UCAS tclch (see Note A) tcp LCAS tasr tcsh tcrp trah trsh tasc tcal tral Row Column tcah trad tcl trl (see Note C) tds tdh tp DQ0 DQ15 Valid Data In td th NOTES: A. To hold the address latched by the first xcas going low, the parameter tclch must be met. B. xcas order is arbitrary. C. tcl must be satisfied for each xcas to write properly to each byte. Figure 4. rite-cycle Timing 12 POST OFFICE BOX 1443 HOUSTON, TEXAS

13 PARAMETER MEASUREMENT INFORMATION tc TMS418160A t UCAS tt trcd tcsh tcrp trsh tclch (see Note A) LCAS tasr trad trah tcp tasc tcal tral Row Column (see Note C) tcs (see Note C) tcs tcah tch (see Note C) (See Note C) tch (see Note E) tcl trl tp See Note E DQ8 DQ15 Valid Data In tds (see Note D) tdh DQ0 DQ7 Valid Data In tds (see Note D) tdh (see Note D) NOTES: A. To hold the address latched by the first xcas going low, the parameter tclch must be met. B. xcas order is arbitrary. C. tcs and tch must be satisfied for each xcas. D. tds and tdh of a DQ input are referenced to the corresponding xcas. E. tcl must be satisfied for each xcas to write properly to each byte. Figure 5. Early-rite-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

14 PARAMETER MEASUREMENT INFORMATION trc t xcas tt trcd tasr trah trad tasc tcah tcrp tt tcp Row Column trcs trd tcl tp trl tad t CD DQ0 DQ15 tclz See Note A taa tcac Data Out tds Data In tdh trac ta toho tz td th NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Read-rite-Cycle Timing 14 POST OFFICE BOX 1443 HOUSTON, TEXAS

15 PARAMETER MEASUREMENT INFORMATION TMS418160A tp UCAS trcd trhcp tcrp tclch (see Note A) tcsh tpc trsh tcp LCAS tasr trah tasc tcah tcal tral Row Column Column Don t Care trad tcac (see Note B) taa taa trch toh trrh Don t Care trcs tcpa (see Note C) trac DQ8 DQ15 See Note D tclz Valid Out toff tz DQ0 DQ7 See Note D Valid Out Valid Out ta ta toho toho NOTES: A. B. To hold the address latched by the first xcas going low, the parameter tclch must be met. tcac is measured from xcas to its corresponding DQx. C. Access time is tcpa-, taa-, or tcac-dependent. D. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. E. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing specifications are not violated. F. xcas order is arbitrary. Figure 7. Enhanced-Page-Mode Read-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

16 PARAMETER MEASUREMENT INFORMATION tp UCAS trsh trcd tclch (see Note A) tcsh tcp trhcp tpc tcrp LCAS tasr tasc trah tcah tcal tral Row Column Column trad tcl (see Note D) tcl tp trl tds tds DQ8 DQ15 tdh Valid In tdh DQ0 DQ7 Valid In Valid In td NOTES: A. To hold the address latched by the first xcas going low, the parameter tclch must be met. B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing specifications are not violated. C. xcas order is arbitrary. D. tcl must be satisfied for each xcas to ensure proper writing to each byte. Figure 8. Enhanced-Page-Mode rite-cycle Timing 16 POST OFFICE BOX 1443 HOUSTON, TEXAS

17 PARAMETER MEASUREMENT INFORMATION TMS418160A tp trsh UCAS trcd tclch (see Note A) tcsh tcp trhcp tpc tcrp LCAS tasr tasc trah tcah tcal tral Row Column Column trad tcs (see Note D) tcl (see Note F) tch (see Note D) tcl trl DQ8 DQ15 tds (see Note E) Valid In tdh (see Note E) DQ0 DQ7 Valid In Valid In NOTES: A. To hold the address latched by the first xcas going low, the parameter tclch must be met. B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing specifications are not violated. C. xcas order is arbitrary. D. tcs and tch must be satisfied for each xcas. E. tds and tdh for a DQ is referenced to the corresponding xcas. F. tcl must be satisfied for each xcas. Figure 9. Enhanced-Page-Mode Early rite-cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

18 PARAMETER MEASUREMENT INFORMATION tp trcd tcsh tprc trsh tcrp UCAS LCAS tclch (see Note A) tcp trad tasc tasr tcah tcp Row Column Column trah tcd tad trd tp tcl trl trcs taa trac tclz tcac taa tds tdh (see Note C) tcpa (see Note B) Valid Out th DQ0 DQ15 Valid In Valid In Valid Out ta tz th td NOTES: A. B. To hold the address latched by the first xcas going low, the parameter tclch must be met. Access time is tcpa-, taa-, or tcac-dependent. C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. D. xcas order is arbitrary. E. A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are not violated. F. tcac is measured from xcas to its corresponding DQx. Figure 10. Enhanced-Page-Mode Read-Modify-rite-Cycle Timing 18 POST OFFICE BOX 1443 HOUSTON, TEXAS

19 PARAMETER MEASUREMENT INFORMATION TMS418160A t trc tcrp tt C xcas See Note A tasr trah Row Row DQ0 DQ15 Hi-Z NOTE A: All xcas must be high. Figure 11. -Only Refresh-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

20 PARAMETER MEASUREMENT INFORMATION Memory Cycle t Refresh Cycle t Refresh Cycle tchr xcas tasc tcah trah tasr Row Col trrh trh trh trh trcs trac taa tcac toff DQ0 DQ15 Valid Data Out tclz ta tz Figure 12. Hidden-Refresh-Cycle (Read) Timing 20 POST OFFICE BOX 1443 HOUSTON, TEXAS

21 PARAMETER MEASUREMENT INFORMATION TMS418160A Memory Cycle Refresh Cycle Refresh Cycle t t xcas tchr tcah tasc trah tasr Row Col tcs trh tp tch tds tdh DQ0 DQ15 Valid Data Figure 13. Hidden-Refresh-Cycle ( rite) Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

22 PARAMETER MEASUREMENT INFORMATION trc t xcas C tcsr tt tchr trh DQ0 DQ15 Hi-Z NOTE A: Any xcas can be used. If both LCAS and UCAS are used, both must satisfy tcsr and tchr. Figure 14. Automatic-xCBR-Refresh-Cycle Timing 22 POST OFFICE BOX 1443 HOUSTON, TEXAS

23 DZ (R-PDSO-J42) MECHANICAL DATA PLASTIC SMALL-OUTLINE J-LEAD PACKAGE (27,43) (27,18) (11,30) (11,05) 0,405 (10,29) (10,03) (0,81) (0,66) (2,69) NOM (3,76) (3,25) Seating Plane (1,27) (0,51) (0,41) (0,18) M (0,10) (9,65) (9,14) (0,20) NOM / C 4/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is (0,125). device symbolization TI -SS Speed ( - 50, - 60, - 70) TMS418160A E Y DZ M LLLL P Package Code Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code afer Fab Code POST OFFICE BOX 1443 HOUSTON, TEXAS

24 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR ARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated