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1 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 15, 2000 Preliminary 1.0 Final version release September 29, 2003 Final 1.1 Add Pb-Free package type August 5, 2004 (August, 2004, Version 1.1) AMIC Technology, Corp.

2 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Features Organization: 65,536 words X 16 bits Part Identification: - A416316B - A416316B-L (with self-refresh mode) High speed - 30/35/40 ns access time - 16/18/20 ns column address access time - 10/11/12 ns CAS access time Low power consumption - Operating: 75mA (-30 max) - Standby: 3 ma (TTL) Separate CAS (, ) for byte selection Self refresh mode 256 refresh cycles, 4 ms refresh interval Read-modify-write, -only, CAS -before-, Hidden refresh capability TTL-compatible, three-state I/O JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package Single 5V power supply/built-in VBB generator Pin Configuration SOJ TSOP Pin Descriptions VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC NC A0 A1 A2 A3 VCC A416316BS 40 VSS VCC 39 I/O0 38 I/O14 I/O1 37 I/O13 I/O2 36 I/O12 I/O3 35 VSS VCC 34 I/O11 I/O4 33 I/O10 I/O5 32 I/O9 I/O6 31 I/O8 I/O7 30 NC 29 NC 28 NC NC 25 A7 NC 24 A6 A0 23 A5 A1 22 A4 A2 21 VSS A3 VCC A416316BV VSS I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC A7 A6 A5 A4 VSS Symbol A0 A7 I/O0 - VCC Address Inputs Data Input/Output Description Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable +5V Power Supply VSS Ground NC No Connection (August, 2004, Version 1.1) 1 AMIC Technology, Corp.

3 Selection Guide Symbol Description Unit trac Maximum Access Time ns taa Maximum Column Address Access Time ns tcac Maximum CAS Access Time ns ta Maximum Output Enable ( ) Access Time ns trc Minimum Read or Write Cycle Time ns tpc Minimum Fast Page Mode Cycle Time ns ICC1 Maximum Operating Current ma ICC6 Maximum CMOS Standby Current ma Functional Description The A416316B is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 16 bits. The A416316B is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The A416316B features a high speed page mode operation in which high speed read, write and read-write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe ( and ) which acts as an output enable independent of. Very fast and to output access time eases system design. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 19/21/23 ns. The A416316B is best suited for graphics, digital signal processing and high performance peripherals. The A416316B is available in JEDEC standard 40-pin plastic SOJ package and 40/44 TSOP type II package. (August, 2004, Version 1.1) 2 AMIC Technology, Corp.

4 Block Diagram VCC VSS REFRESH CONTROLLER Y0 - Y7 COLUMN DECODER SENSE AMP UPPER BYTE DATA I/O BUFFER I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 256 X 16 I/O7 CLOCK GENERATOR CLOCK GENERATOR A0 A1 A2 A3 A4 A5 A6 A7 ADDRESS BUFFERS X0 - X7 ROW DECODER X 256 X 16 ARRAY LOR BYTE DATA I/O BUFFER I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLOCK GENERATOR CLOCK GENERATOR CLOCK GENERATOR SUBSTRATE BIAS GENERATOR Recommended Operating Conditions (Ta = 0 C to +70 C) Symbol Description Min. Typ. Max. Unit VCC Supply Voltage V VSS V VIH Input Voltage VCC + 1 V VIL V (August, 2004, Version 1.1) 3 AMIC Technology, Corp.

5 Truth Table Function Address I/Os Notes Standby H H H L L L L Read: Word L L L H L Row/Col. Data Out Read: Lower Byte L H L H L Row/Col. I/O0-7 = Data Out I/O8-15 = High-Z Read: Upper Byte L L H H L Row/Col. I/O0-7 = High-Z I/O8-15 = Data Out Write: Word(Early) L L L L X Row/Col. Data In Write: Lower Byte(Early) L H L L X Row/Col. I/O0-7 = Data In I/O8-15 = X Write: Upper Byte(Early) L L H L X Row/Col. I/O0-7 = X I/O8-15 = Data In Read-Write L L L L H Row/Col. Data Out Data In 1.2 Fast-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles L L H H Row/Col. Col. Data Out Data Out 2 2 Fast-Page-Mode Write(Early) -First cycle -Subsequent Cycles L L L L X X Row/Col. Col. Data In Data In 1 1 Fast-Page-Mode Read-Write -First cycle -Subsequent Cycles L L L H L H Row/Col. Col. Data In Data In 1, 2 1, 2 Hidden Refresh Read L L L H L Row/Col. Data Out 2 Hidden Refresh Write L L L L X Row/Col. Data In High-Z 1 -Only Refresh L H H X X Row High-Z CBR Refresh L L X X X High-Z 3 Self Refresh (L-ver only) L L X X X High-Z Note: 1. Byte Write may be executed with either or active. 2. Byte Read may be executed with either or active. 3. Only one CAS signal ( or ) must be active. (August, 2004, Version 1.1) 4 AMIC Technology, Corp.

6 Absolute Maximum Ratings* Input Voltage (Vin) V to +7.0V Output Voltage (Vout) V to +7.0V Power Supply Voltage (VCC) V to +7.0V Operating Temperature (TOPR) C to +70 C Storage Temperature (TSTG) C to +150 C Soldering Temperature X Time (TSLODER) C X 10sec Power Dissipation (PD) W Short Circuit Output Current (Iout) mA Latch-up Current mA *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) Symbol Parameter Unit Test Conditions Notes Min. Max. Min. Max. Min. Max. IIL IOL Input Leakage Current Output Leakage Current µa 0V Vin +5.5V Pins not under test = 0V µa DOUT disabled, 0V Vout +5.5V ICC1 Operating Current ma,, Address cycling trc = min. 1, 2 ICC2 TTL Standby Power Supply Current ma = CAS VIH All other inputs VSS ICC3 Refresh Current ( only Refresh) ma cycling, = = VIH, trc = min. 1 ICC4 Fast Page Mode Current ma = VIL,, Address cycling tpc = min. 1, 2 ICC5 Refresh Current ( CAS -before- Refresh ) ma,, cycling trc = min. 1 ICC6 CMOS Standby Power Supply Current ma = CAS VCC - 0.2V All other inputs VSS ICC7 Self Refresh Mode Current ma = CAS VSS + 0.2V All other inputs VSS VOH Output High Voltage V IOUT = -5.0mA VOL Output Low Voltage V IOUT = 4.2mA (August, 2004, Version 1.1) 5 AMIC Technology, Corp.

7 AC Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) # Std Symbol Parameter Unit Notes Min. Max. Min. Max. Min. Max. 1 trc Random Read or Write Cycle Time ns 2 trp Precharge Time ns 3 t Pulse Width 30 75K 35 75K 40 75K ns 4 tcas CAS Pulse Width ns 5 trcd to CAS Delay Time ns 6 6 trad to Column Address Delay Time ns 7 7 trsh CAS to Hold Time ns 8 tcsh CAS Hold Time ns 9 tcrp CAS to Precharge Time ns 10 tasr Row Address Setup Time ns 11 trah Row Address Hold Time ns tt Transition Time (Rise and Fall) ns 4, 5 tref Refresh Period ms 3 12 tclz CAS to Output in Low Z ns 8 13 trac Access Time from ns 6,7 14 tcac Access Time from CAS ns 6, taa Access Time from Column Address ns 7, tar Column Address Hold Time from ns 17 trcs Read Command Setup Time ns 18 trch Read Command Hold Time ns 9 19 trrh Read Command Hold Time Reference to ns 9 20 tral Column Address to Lead Time ns (August, 2004, Version 1.1) 6 AMIC Technology, Corp.

8 AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) # Std Symbol Parameter Unit Notes Min. Max. Min. Max. Min. Max. 21 tcoh Output Hold After CAS Low ns 22 tods Output Disable Setup Time ns 23 toff Output Buffer Turn-Off Delay Time ns 8, tasc Column Address Setup Time ns 25 tcah Column Address Hold Time ns 26 trps Precharge Setup Time ns 27 twcs Write Command Setup Time ns twch Write Command Hold Time ns twcr Write Command Hold Time to ns 30 twp Write Command Pulse Width ns 31 trwl Write Command to Lead Time ns 32 tcwl Write Command to CAS Lead Time ns 33 tds Data-in setup Time ns tdh Data-in Hold Time ns tdhr Data-in Hold Time to ns 36 trmw Read-Modify-Write Cycle Time ns 37 trwd to Delay Time (Read-Modify-Write) 38 tcwd CAS to Delay Time (Read-Modify-Write) 39 tawd Column Address to Delay Time (Read-Modify-Write) ns ns ns ts Pulse Width (Self Refresh Mode) µs 41 tcpn CAS Precharge Time K K K ns ( CAS before ) (August, 2004, Version 1.1) 7 AMIC Technology, Corp.

9 AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0 C to +70 C) # Std Symbol Parameter Unit Notes Min. Max. Min. Max. Min. Max. 42 tpc Read or Write Cycle Time (Fast Page) ns tcpa Access Time from CAS Precharge (Fast Page) ns tcp CAS Precharge Time (Fast Page) ns 45 tprm Fast Page Mode RMW Cycle Time ns 46 tcrw Fast Page Mode CAS Pulse Width (RMW) ns 47 tp Pulse Width (Fast Page) 30 75K 35 75K 40 75K ns 48 tcsr CAS Setup Time ( CAS -before- ) ns 3 49 tchr CAS Hold Time ( CAS -before- ) ns 3 50 trpc to CAS Precharge Time ns ( CAS -before- ) 51 troh Hold Time Reference to ns 52 ta Access Time ns 53 td to Data Delay ns 54 tz Output Buffer Turn-off Delay from ns 8 55 th Command Hold Time ns 56 tcpt CAS Precharge Time ( CAS -before- Counter Test) ns (August, 2004, Version 1.1) 8 AMIC Technology, Corp.

10 Notes: 1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. 3. An initial pause of 200µs is required after power-up followed by any 8 cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- initialization cycles instead of 8 cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8ms). 4. AC Characteristics assume tt = 3ns. All AC parameters are measured with a load equivalent to one TTL loads and 50pF, VIL (min.) GND and VIH (max.) VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the trcd (max.) limit insures that trac (max.) can be met. trcd (max.) is specified as a reference point only. If trcd is greater than the specified trcd (max.) limit, then access time is controlled exclusively by tcac. 7. Operation within the trad (max.) limit insures that trac (max.) can be met. trad (max.) is specified as a reference point only. If trad is greater than the specified trad (max.) limit, then access time is controlled exclusively by taa. 8. Assumes three state test load (5pF and a 380Ω Thevenin equivalent). 9. Either trch or trrh must be satisfied for a read cycle. 10. toff (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. twcs, twch, trwd, tcwd and tawd are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs twcs (min.) and twch twch (min.), the cycle is an early write cycle and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If trwd trwd (min.), tcwd tcwd (min.) and tawd tawd (min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. These parameters are referenced to and leading edge in early write cycles and to leading edge in read-modify-write cycles. 13. Access time is determined by the longer of taa or tcac or tcpa. 14. tasc tcp to achieve tpc (min.) and tcpa (max.) values. 15. These parameters are sampled and not 100% tested. (August, 2004, Version 1.1) 9 AMIC Technology, Corp.

11 Word Read Cycle trc(1) t(3) tcsh(8) trcd(5) trsh(7) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Address Column Address tar(16) trcs(17) trch(18) trrh(19) troh(51) ta(52) tcac(14) taa(15) toff(23) trac(13) tz(54) I/O0 ~ High-Z Valid Data-out tclz(12) : High or Low (August, 2004, Version 1.1) 10 AMIC Technology, Corp.

12 Word Write Cycle (Early Write) trc(1) t(3) tcsh(8) trcd(5) trsh(7) tar(16) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Address Column Address twcr(29) tcwl(32) trwl(31) twp(30) twcs(27) twch(28) tdhr(35) I/O0 ~ tds(33) tdh(34) Valid Data-in : High or Low (August, 2004, Version 1.1) 11 AMIC Technology, Corp.

13 Word Write Cycle (Late Write) trc(1) t(3) tcsh(8) trcd(5) trsh(7) tar(16) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Address Column Address tcwl(32) trwl(31) twcr(29) twp(30) td(54) th(55) tdhr(35) tds(33) tdh(34) I/O0 ~ High-Z Vaild Data-in : High or Low (August, 2004, Version 1.1) 12 AMIC Technology, Corp.

14 Word Read-Modify-Write Cycle trmw(36) t(3) tcsh(8) trcd(5) trsh(7) tar(16) trad(6) tasr(10) trah(11) A0 ~ A7 Row Address Column Address tawd(39) tcwd38) tcwl(32) trwd(37) trwl(31) ta(52) tz(54) td(53) twp(30)) tcac(14) taa(15) tds(33) tdh(34) trac(13) I/O0 ~ High-Z tclz(12) Data-out Data-in : High or Low (August, 2004, Version 1.1) 13 AMIC Technology, Corp.

15 Fast Page Mode Word Read Cycle tp(47) trcd(5) tcsh(8) tcp(44) tpc(42) tcp(44) trsh(7) tar(16) tral(20) A0 ~ A7 trad(6) tasr(10) trah(11) Row Column Column Column taa(15) taa(15) trrh(19) trcs(17) trcs(17) trcs(17) trch(18) trch(18) trch(18) tcpa(43) tcpa(43) troh(51) ta(52) ta(52) ta(52) taa(15) toff(23) toff(23) toff(23) tcac(14) tcac(14) tcac(14) trac(13) tz(54) tz(54) tz(54) I/O0 ~ Data-out Data-out Data-out tclz(12) tclz(12) tclz(12) : High or Low (August, 2004, Version 1.1) 14 AMIC Technology, Corp.

16 Fast Page Mode Early Word Write Cycle tp(47) tcsh(8) tpc(42) trsh(7) trcd(5) tcp(44) tcp(44) tral(20) trad(6) tasr(10) trah(11) A0 ~ A7 Row Column Column Column tcwl(32) tcwl(32) tcwl(32) trwl(31) twcs(27) twcs(27) twcs(27) twch(28) twch(28) twch(28) twp(30) twp(30) twp(30) tdh(34) tdh(34) tdh(34) tds(33) tds(33) tds(33) I/O0 ~ Data-in Data-in Data-in : High or Low (August, 2004, Version 1.1) 15 AMIC Technology, Corp.

17 Fast Page Mode Word Read-Modify-Write Cycle tp(47) trcd(5) tcsh(8) tcp(44) tprmw(45) tcp(44) trsh(7) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Column Column Column tcwl(32) tcwl(32) tcwl(32) trwd(37) trwl(31) trcs(17) tcwd(38) tcwd(38) tcwd(38) twp(30) twp(30) twp(30) tawd(39) tawd(39) tawd(39) troh(51) ta(52) ta(52) ta(52) td(53) td(53) td(53) tcac(14) tcpa(43) tcpa(43) taa(15) taa(15) taa(15) tz(54) tz(54) tz(54) I/O0 ~ High-Z trac(13) tds(33) tdh(34) tds(33) tclz(12) tclz(12) tclz(12) Data-in Data-out Data-in Data-out tdh(34) tds(33) Data-in Data-out tdh(34) : High or Low (August, 2004, Version 1.1) 16 AMIC Technology, Corp.

18 Only Refresh Cycle trc(1) t(3) trpc(50) tasr(10) trah(11) A0 ~ A7 Row Note:, = Don't care. : High or Low CAS Before Refresh Cycle trc(1) t(3) trpc(50) tchr(49) tcpn(41) tcsr(48) I/O0 ~ toff(23) High-Z Note:,, A0 ~ A7 = Don't care. : High or Low (August, 2004, Version 1.1) 17 AMIC Technology, Corp.

19 Timing Waveform of CAS -before- Refresh Counter Test Cycle t (3) trp (2) trsh (7) CAS tcsr (48) tchr (49) tcpt (56) tcas (4) tral (20) tcah (25) Address I/O Col Address taa (15) tcac (14) tclz (12) toff (23) Data Out trcs (17) trch (18) trrh (19) Read Cycle ta (52) troh (53) tcwl(32) trwl(31) twcs(27) twp(30) twch(28) Write Cycle I/O tds (33) Data In tdh (34) trcs (17) tawd(39) tcwd(38) twp (30) tcwl(32) Read-Write Cycle tclz (12) tcac (14) ta(52) taa (15) td (53) tz(54) tds (33) tdh (34) I/O Data Out Data In (August, 2004, Version 1.1) 18 AMIC Technology, Corp.

20 Hidden Refresh Cycle (Word Read) trc(1) trc(1) t(3) t(3) tar(16) trcd(5) trsh(7) tchr(49) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Column trcs(17) trrh(19) taa(15) tcac(14) toff(23) tclz(12) trac(13) I/O0 ~ High-Z Valid Data-out : High or Low (August, 2004, Version 1.1) 19 AMIC Technology, Corp.

21 Hidden Refresh Cycle (Early Word Write) trc(1) trc(1) t(3) t(3) tar(16) trcd(5) trsh(7) tchr(49) trad(6) tral(20) tasr(10) trah(11) A0 ~ A7 Row Column twcs(27) twch(28) twp(30) tds(33) tdh(34) I/O0 ~ Valid Data-in : High or Low (August, 2004, Version 1.1) 20 AMIC Technology, Corp.

22 Self Refresh Mode (A416316B-L Only) tpr(2) ts(40) trps(26) trpc(50) tcsr(48) tchs(21) tcpn(41) tasr(10) A0 ~ A7 ROW COL toff(23) I/O0 ~ High-Z Note:, = Don't care. : High or Low Self Refresh Mode. a. Entering the Self Refresh Mode: The A416316B-L Self Refresh Mode is entered by using CAS before cycle and holding and CAS signal low longer than 300µs. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding low after entering the Self Refresh Mode. It does not depend on CAS being high or low after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A416316B exits the Self Refresh Mode when the signal is brought high. (August, 2004, Version 1.1) 21 AMIC Technology, Corp.

23 Capacitance 15 (f = 1MHz, Ta = Room Temperature, VCC = 5V ± 10%) Symbol Signals Parameter Max. Unit Test Conditions CIN1 A0 A7 5 pf Vin = 0V CIN2,, Input Capacitance 7 pf Vin = 0V,, CI/O I/O0 - I/O Capacitance 7 pf Vin = Vout = 0V Ordering Codes Package\ Access Time 30ns 35ns 40ns Self-Refresh 40L SOJ (400 mil) A416316BS-30 A416316BS-35 A416316BS-40 No 40L Pb-Free SOJ (400 mil) A416316BS-30F A416316BS-35F A416316BS-40F No 40/44L TSOP type II (400mil) A416316BV-30 A416316BV-35 A416316BV-40 No 40/44L Pb-Free TSOP type II (400mil) A416316BV-30F A416316BV-35F A416316BV-40F No 40L SOJ (400mil) A416316BS-30L A416316BS-35L A416316BS-40L Yes 40L Pb-Free SOJ (400mil) A416316BS-30LF A416316BS-35LF A416316BS-40LF Yes 40/44L TSOP II (400mil) A416316BV-30L A416316BV-35L A416316BV-40L Yes 40/44L Pb-Free TSOP II (400mil) A416316BV-30LF A416316BV-35LF A416316BV-40LF Yes (August, 2004, Version 1.1) 22 AMIC Technology, Corp.

24 Package Information SOJ 40L Outline Dimensions unit: inches/mm E HE 1 20 D C S Seating Plane b b1 e D y A1 A2 A L θ e1 Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A b b C D E e e HE L S y θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2004, Version 1.1) 23 AMIC Technology, Corp.

25 Package Information TSOP 40/44L (Type II) Outline Dimensions unit: inches/mm 44 E HE θ L 1 D L1 c S B e D y A1 A2 A L L1 Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A A A B c D E e BSC 0.80 BSC HE L L S y θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (August, 2004, Version 1.1) 24 AMIC Technology, Corp.