A23W9308. Document Title 524,288 X 8 BIT CMOS MASK ROM. Revision History. Rev. No. History Issue Date Remark
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1 Preliminary 524,288 X 8 BIT CMOS MASK ROM Document Title 524,288 X 8 BIT CMOS MASK ROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 2, 1999 Preliminary PRELIMINARY (November, 1999, Version 0.0) AMIC Technology, Inc.
2 Preliminary 524,288 X 8 BIT CMOS MASK ROM Features 524,288 x 8 bit organization Wide power supply range : +2.7V to +5.5V Access time: 120 ns (max.)/5v 150 ns (max.)/3v Current: Operating: 50mA (max.)/5v 15mA (max.)/3v Standby: 50µA (max.)/5v 25µA (max.)/3v General Description The A23W9308 high-performance Read Only Memory is configured as 524,288 x 8 bits. It is designed to be compatible with all microprocessors and similar applications where high-performance, large-bit storage, and simple interfacing are important design considerations. This device is designed for use with operating voltage from 3V to 5V. Mask Programmed for Chip Enable (power-down) CE/ CE, Output Enable OE/ OE /NC Three-state outputs for wired-or expansion Full static operation All inputs and outputs are directly TTL-compatible Available in 32-pin DIP, 32-pin SOP, 32-pin PLCC packages or in DICE FORM. The A23W9308 offers an automatic POWER-DOWN controlled by the Chip Enable CE/ CE input. When CE/ CE goes low/high, the device will automatically POWER-DOWN and remain in a low power STANDBY mode as long as CE/ CE remains low/high. A23W9308 also offers OE/ OE /NC (Active High or Low or No Connection), which eliminates bus contention in multiple bus microprocessor systems. Pin Configurations P-DIP / SOP PLCC NC 1 32 VCC A12 A15 A16 NC VCC A18 A17 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O A23W A18 A17 A14 A13 A8 A9 A11 OE/OE/NC A10 CE/CE O7 O6 O5 A7 A6 A5 A4 A3 A2 A1 A0 O A23W A14 A13 A8 A9 A11 OE/OE/NC A10 CE/CE O7 O2 GND O4 O3 O1 O2 GND O3 O4 O5 O6 PRELIMINARY (November, 1999, Version 0.0) 1 AMIC Technology, Inc.
3 Block Diagram ROW DECODER DRIVER MEMORY CELL ARRAY 524,288 X 8 A0 - A18 ADDRESS INPUTS COLUMN DECODER DRIVER COLUMN SELECTOR CIRCUITRY CE/CE OE/OE/NC POWER-DOWN OR OUTPUT ENABLE CIRCUITRY O0 O1 O2 O3 O4 O5 O6 O7 PRELIMINARY (November, 1999, Version 0.0) 2 AMIC Technology, Inc.
4 Pin Descriptions 32L DIP/SOP 2-12, 23, Pin No. Symbol Description 32L PLCC 2-12, 23, A0 - A18 Address Inputs CE/ CE Chip Enable Input (Note 1) OE/ OE /NC Output Enable (Note 1) 13-15, , O0 - O7 Data Outputs VCC Power Supply GND Ground 1 1 NC No Connection (Note 2) Notes: 1. This pin is user-definable as active high or active low. 2. NC indicates "No Connection." Recommended DC Operating Conditions (TA = 0 C to + 70 C) Symbol Parameter Min. Max. Unit VCC Supply Voltage V GND Ground 0 0 V VIH Input High Voltage 0.7* VCC VCC+0.3 V VIL Input Low Voltage V PRELIMINARY (November, 1999, Version 0.0) 3 AMIC Technology, Inc.
5 Absolute Maximum Ratings* Ambient Operating Temperature C to + 80 C Storage Temperature C to C Supply Voltage to Ground Potential V to + 7.0V Output Voltage V to VCC + 0.5V Input Voltage V to VCC + 0.5V Power Dissipation mW *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = 0 C to + 70 C, GND = 0V) Symbol Parameter 5.0V ± 10% 3.0V ± 10% Unit Conditions Note Min. Max. Min. Max. VOH Output High Voltage V IOH = -1mA (5V) IOH = -0.4mA (3V) VOL Output Low Voltage V IOL = 3.2mA (5V) IOL = 1.6mA (3V) VlH Input High Voltage 2.2 VCC * VCC VCC+0.5 V VlL Input Low Voltage V lli Input Leakage Current µa VCC = max. VIN = VCC to GND llo Output Leakage Current µa VCC = max. VOUT = VCC to GND 1 ICC Operating Supply Current ma tcyc = min. 2 ISB Standby Supply Current (TTL) ma CE = VIH, CE = VIL ISB1 Standby Supply Current (CMOS) µa CE = VCC - 0.2V, CE = 0.2V PRELIMINARY (November, 1999, Version 0.0) 4 AMIC Technology, Inc.
6 Capacitance Symbol Parameter Min. Max. Unit Test Conditions Note CI Input Capacitance 10 pf CO Output Capacitance 10 pf TA = 25 C 3 f = 1.0MHz AC Characteristics (TA = 0 C to +70 C, GND = 0V) Symbol Parameter 5.0V ± 10% 3.0V ± 10% Unit Note Min. Max. Min. Max. tcyc Cycle Time ns taa Address Access Time ns tace Chip Enable Access Time ns taoe Output Enable Access Time ns toh Output Hold after Address Change ns tlz Output Low Z Delay ns 4, 6 thz Output High Z Delay* ns 5, 6 * thz is specified from either OE / OE or CE / CE going disabled, whichever occurs first. Notes: 1. OE/CE = VIL, OE / CE = VIH (Output is unloaded) 2. VIN = VIH/VIL, but OE/CE = VIH, OE / CE = VIL (Output is unloaded) 3. This parameter is periodically sampled and is not 100% tested. All pins, except pins under test, are tied to AC ground. 4. Output LOW impedance delay (tlz) is measured from CE or OE going active. 5. Output HIGH impedance delay (thz) is measured from CE or OE going inactive. 6. This parameter is sampled and not 100% tested. PRELIMINARY (November, 1999, Version 0.0) 5 AMIC Technology, Inc.
7 Timing Waveforms Propagation Delay from Address (CE/ CE = Active, OE/ OE = Active) tcyc ADDRESS INPUTS VALID taa toh DATA OUT VALID Propagation Delay from Chip Enable or Output Enable (Address Valid) CHIP ENABLE VALID tace OUTPUT ENABLE VALID taoe thz tlz DATA OUT tlz VALID AC Test Conditions Applied Voltage 5.0V ± 10% 3.0V ± 10% Input Pulse Levels 0.4V to 2.4V 0.4V to 2.4V Input Rise and Fall Time 10 ns 10 ns Timing Measurement Reference Level VIH = 2.2V VIL = 0.8V VOH = 2.0V VOL = 08V VIN = 1.5V VOUT = 1.5V Output Load 1 TTL gate and CL = 100pF PRELIMINARY (November, 1999, Version 0.0) 6 AMIC Technology, Inc.
8 Function Table CE/ CE OE/ OE /NC O0 - O7 Mode A A Data Out Read I X Hi - Z Power-down A I Hi - Z Output Disable 1. CE/ CE and OE/ OE /NC are mask programmable as either active low, active high, or no connection. 2. "A" means "Active," "I" means "Inactive," and "X" means "Either." Ordering Information Part No. Access Time (ns) 5.0V 3.0V Package A23W L DIP A23W9308M L SOP A23W9308L L PLCC A23W9308H DICE FORM PRELIMINARY (November, 1999, Version 0.0) 7 AMIC Technology, Inc.
9 Pad Configurations A4 A5 A6 A7 A12 A15 A16 VCC VCC A18 A17 A14 A13 A8 A9 A Y (0,0) X A3 A2 A1 A0 O0 O1 O2 GND GND O3 O4 O5 O6 O7 CE/CE A10 OE/OE/NC Pad Location Pad No. Pad Name Coordinate (um) Coordinate (um) Pad No. Pad Name X Y X Y 1 VCC O A O A O A O A O A CE/ CE A A A OE/ OE /NC A A A A A A A A O A O A O A GND VCC GND PRELIMINARY (November, 1999, Version 0.0) 8 AMIC Technology, Inc.
10 Package Information P-DIP 32L Outline Dimensions unit: inches/mm D E 1 16 E1 C A A2 A1 Base Plane L Seating Plane B B1 e θ EA Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A B B C D E E EA e L θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. PRELIMINARY (November, 1999, Version 0.0) 9 AMIC Technology, Inc.
11 Package Information SOP (W.B.) 32L Outline Dimensions unit: inches/mm E HE θ L 1 b 16 Detail F D c S Seating Plane D y e A1 A2 A See Detail F LE Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A A A b c D E e HE L LE S y θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. PRELIMINARY (November, 1999, Version 0.0) 10 AMIC Technology, Inc.
12 Package Information PLCC 32L Outline Dimension unit: inches/mm 13 HD D E HE e GD b b1 D y A1 A2 A θ GE c L Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A b b C D E e GD GE HD HE L y θ Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. PRELIMINARY (November, 1999, Version 0.0) 11 AMIC Technology, Inc.
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1024K X 8 BIT SUPER 512K LOW POWER X8BITCMOS LOW SRAM FEATURES Fast access time : 55ns Low power consumption: Operating current : 30mA (TYP.) Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V
IS62C51216AL IS65C51216AL
IS62C51216AL IS65C51216AL 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
IDT71V424S/YS/VS IDT71V424L/YL/VL
.V CMOS Static RAM Meg (K x -Bit) IDT1V2S/YS/VS IDT1V2L/YL/VL Features K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times Commercial
32K Word x 8 Bit. Rev. No. History Issue Date Remark 2.0 Initial issue with new naming rule Dec.27,2004
Revision History Rev. No. History Issue Date Remark 2.0 Initial issue with new naming rule Dec.27,2004 1 Rev. 2.0 GENERAL DESCRIPTION The is a high performance, high speed and super low power CMOS Static
IS61WV2568EDBLL IS64WV2568EDBLL
ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply
3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)
3.3V CMOS Static RAM Meg (2K x 1-Bit) IDT71V1S IDT71V1L Features 2K x 1 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle times Commercial and
IS61WV6416DALL/DALS IS61WV6416DBLL/DBLS IS64WV6416DBLL/DBLS
ISWVDALL/DALS ISWVDBLL/DBLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM JANUARY 0 FEATURES HIGH SPEED: (IS/WVDALL/DBLL) High-speed access time:, 0,, 0 ns Low Active Power: mw (typical) Low Standby Power:
CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
HY62256A Series 32Kx8bit CMOS SRAM
32Kx8bit CMOS SRAM DESCRIPTION The HY62256A is a high-speed, low power and 32,786 x 8-bits CMOS Static Random Access Memory fabricated using Hyundai's high performance CMOS process technology. The HY62256A
IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES High-speed access time: 35, 45, 55 ns CMOS low power operation 30 mw (typical) operating 6 µw (typical) CMOS standby TTL compatible interface
Document Title. Revision History. 32Kx8 bit Low Power CMOS Static RAM. Remark. History. Revision No. Draft Data. Design target. Initial draft 0.
Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data Remark 0.0 Initial draft May 18, 1997 Design target 0.1 First revision - KM62256DL/DLI ISB1 = 100 50µA
CMOS SRAM. KM684000B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.
Document Title 512Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft December 7, 1996 Advance 0.1 Revise - Changed Operating current by reticle
32Mbit, 1MX32, 5V CMOS S-RAM MODULE
32Mbit, 1MX32, 5V CMOS S-RAM MODULE Features Module Access Times: 20, 35 & 45ns Package: 66-Pin Ceramic PGA 1.385" SQ Package Height 0.215"/ 0.160 Single 5V (±10%) Power Supply Industrial and Military
32K-Word By 8 Bit. May. 26, 2005 Jul. 04, 2005 Oct. 06, 2005 May. 16, Revise DC characteristics Dec. 13, 2006
Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Dec. 29, 2004 2.1 Update the WRITE CYCLE1 (Write Enable Controlled) waveform Mar. 31, 2005 2.2 Revise V IL from 1.5V
LY V 128K X 16 BIT HIGH SPEED CMOS SRAM
Y6112816 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Aug.12.2007 Rev. 1.1 Apr. 17.2009 Revised TEST CONDITION of ICC Revised FEATURES & ORDERING INFORMATION ead free and green
IS61WV20488FALL IS61/64WV20488FBLL. 2Mx8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
2Mx8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
PRELIMINARY C106A 1. 7C106A 12 7C106A 15 7C106A 20 7C106A 25 7C106A 35 Maximum Access Time (ns) Maximum Operating
1CY 7C10 6A Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 910 mw Low standby power 275 mw 2.0V data retention (optional) 100 µw Automatic power-down when deselected TTL-compatible
SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers
Very Low Power/Voltage CMOS SRAM 1M X 16 bit DESCRIPTION. SPEED (ns) 55ns : 3.0~3.6V 70ns : 2.7~3.6V BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 1M X 16 bit (Dual CE Pins) FEATURES operation voltage : 27~36V Very low power consumption : = 30V C-grade: 45mA (@55ns) operating current I -grade: 46mA (@55ns) operating
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
LY61L K X 16 BIT HIGH SPEED CMOS SRAM
Y6125616 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue May.24.2006 Rev. 1.1 Added Extended Grade Jan.22.2007 Rev. 1.2 Added PKG Type : 48-ball 6mm x 8mm TFBGA Jan.30.2007 Rev.
IS61WV102416FALL IS61/64WV102416FBLL. 1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
White Electronic Designs
* 1Mx32 SRAM 3.3V MODULE FEATURES Access Times of 17, 20, 25ns 4 lead, 2mm CQFP, (Package 511) Organized as two banks of 512Kx32, User Configurable as 2Mx16 or 4Mx Commercial, Industrial and Military Temperature
LY61L25616A 256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 VCC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current ICC1 on
Document Title. Revision History. 256Kx16 bit Low Power and Low Voltage CMOS Static RAM. Draft Date. Revision No. History. Remark.
Document Title 256Kx16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No History Draft Date Remark 0.0 Initial draft July 29, 2002 Preliminary 0.1 Revised - Added Commercial product
Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable FEATURES DESCRIPTION Very low operation voltage : 45 ~ 55V Very low power consumption : = 50V C-grade: 40mA (Max) operating current
HT23C128 CMOS 16K 8-Bit Mask ROM
CMOS 16K8-Bit Mask ROM Features Operating voltage: 2.7V~5.5V Low power consumption Operation: 25mA max. (V CC =5V 10mA max. (V CC =3V Standby: 30A max. (V CC =5V 10A max. (V CC =3V Access time: 150ns max.
8K x 8 Static RAM CY6264. Features. Functional Description
8K x 8 Static RAM Features 55, 70 ns access times CMOS for optimum speed/power Easy memory expansion with CE 1, CE 2, and OE features TTL-compatible inputs and outputs Automatic power-down when deselected
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT29BV040A
Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Software Protected Programming Fast Read Access Time 200 ns Low Power Dissipation 15 ma Active Current 50 µa CMOS Standby
54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
Distributed by: www.jameco.com 1-00-31-4242 The content and copyrights of the attached material are the property of its owner. FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption :
IS39LV040 / IS39LV010 / IS39LV512
4Mbit / 1Mbit / 512 Kbit 3.0 Volt-only CMOS Flash Memory FEATURES Single Power Supply Operation - Low voltage range: 2.70 V - 3.60 V Memory Organization - IS39LV040: 512K x 8 (4 Mbit) - IS39LV010: 128K
IS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection