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1 32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 2, 2001 Preliminary 0.1 Add ultra temp grade and 28-pin DIP package type November 7, Add SI grade July 17, Final version release July 16, 2003 Final 1.1 Add Pb-Free package type August 19, Remove non-pb-free package type July 3, Remove DIP -SI and -SU grade September 26, 2006 (September, 2006, Version 1.3) AMIC Technology, Corp.
2 32K X 8 BIT CMOS SRAM Features Power Supply Range: 4.5V to 5.5V Access times: 70 ns A625308A-S series: Operating: 35mA (max.) Standby: 10μA (max.) A625308A-SI/SU series: Operating: 35mA (max.) Standby: 15μA (max.) Extended operating temperature range: 0 C to 70 C for - S series, -25 C to 85 C for -SI series, -40 C to 85 C for -SU series. General Description The A625308A is a low operating current 262,144-bit static random access memory organized as 32,768 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using three-state output Data retention voltage: 2.0V (min.) Available in 28-pin, DIP/SOP and TSOP Pb-Free package only All Pb-free (Lead-free) products are RoHS compliant Minimum standby power is drawn by this device when is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2.0V. Pin Configurations DIP / SOP TSOP A14 A12 A7 A6 A5 A4 A3 A2 A1 A A625308A(M) VCC WE A13 A8 A9 A11 OE A10 I/O7 OE A A9 3 A8 4 A13 5 WE 6 VCC 7 A14 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14 ~ A625308AV ~ A10 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 I/O I/O6 I/O1 I/O2 GND I/O5 I/O4 I/O3 (September, 2006, Version 1.3) 1 AMIC Technology, Corp.
3 Block Diagram A0 VCC GND A12 A13 ROW DECODER 512 X 512 MEMORY ARRAY A14 I/O0 INPUT DATA CIRCUIT COLUMN I/O I/O7 OE WE CONTROL CIRCUIT Pin Descriptions DIP / SOP Pin No. Symbol Description 1-10, 21, A0 - A14 Address Input 11-13, I/O0 - I/O7 Data Input/Output 20 Chip Enable 22 OE Output Enable 27 WE Write Enable 28 VCC Power Supply 14 GND Ground Pin Description-TSOP Pin No. Symbol Description 2-5, 8-17, 28 A0 - A14 Address Input 18-20, I/O0 - I/O7 Data Input/Output 27 Chip Enable 1 OE Output Enable 6 WE Write Enable 7 VCC Power Supply 21 GND Ground (September, 2006, Version 1.3) 2 AMIC Technology, Corp.
4 Recommended DC Operating Conditions (TA = 0 C to +70 C, -25 C to +85 C or -40 C to +85 C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GND Ground V VIH Input High Voltage VCC V VIL Input Low Voltage V Absolute Maximum Ratings* VCC to GND V to +7.0V IN, IN/OUT Volt to GND V to VCC + 0.5V Operating Temperature, Topr.. 0 C to +70 C or -40 C to +85 C Storage Temperature, Tstg C to +125 C Power Dissipation, PT W Soldering Temp. & Time C, 10 sec *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = 0 C to +70 C, -25 C to +85 C or -40 C to +85 C, VCC = 5.0V ± 10%, GND = 0V) Symbol Parameter A625308A-70S A625308A-70SI/SU Unit Conditions Min. Max. Min. Max. ILI Input Leakage Current μa VIN = GND to VCC ILO Output Leakage Current μa = VIH VI/O = GND to VCC ICC Active Power Supply Current ma = VIL, II/O = 0mA ICC1 Dynamic Operating Current ma Min. Cycle, Duty = 100% = VIL, II/O = 0mA ICC2 Dynamic Operating Current ma = VIL, VIH = VCC VIL = 0V, f = 1 MHz II/O = 0 ma ISB ISB1 Supply Current Standby Power ma = VIH μa VCC - 0.2V VIN 0V VOL Output Low Voltage V IOL = 2.1 ma VOH Output High Voltage V IOH = -1.0 ma (September, 2006, Version 1.3) 3 AMIC Technology, Corp.
5 Truth Table Mode OE WE I/O Operation Supply Current Standby H X X High Z ISB, ISB1 Output Disable L H H High Z ICC, ICC1, ICC2 Read L L H DOUT ICC, ICC1, ICC2 Write L X L DIN ICC, ICC1, ICC2 Note: X: H or L Capacitance (TA = 25 C, f = 1.0 MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 6 pf VIN = 0V CI/O* Input/Output Capacitance - 8 pf VI/O = 0V * These parameters are sampled and not 100% tested. (September, 2006, Version 1.3) 4 AMIC Technology, Corp.
6 AC Characteristics (TA = 0 C to +70 C, -25 C to +85 C or -40 C to +85 C, VCC = 5.0V ± 10%) Symbol Parameter A625308A-70S/SI/SU Unit Min. Max. Read Cycle trc Read Cycle Time 70 - ns taa Address Access Time - 70 ns ta Chip Enable Access Time - 70 ns toe Output Enable to Output Valid - 35 ns tclz Chip Enable to Output in Low Z 10 - ns tolz Output Enable to Output in Low Z 5 - ns tchz Chip Disable to Output in High Z - 25 ns tohz Output Disable to Output in High Z - 25 ns toh Output Hold from Address Change 10 - ns Write Cycle twc Write Cycle Time 70 - ns tcw Chip Enable to End of Write 60 - ns tas Address Set up Time 0 - ns taw Address Valid to End of Write 60 - ns twp Write Pulse Width 50 - ns twr Write Recovery Time 0 - ns twhz Write to Output in High Z - 25 ns tdw Data to Write Time Overlap 30 - ns tdh Data Hold from Write Time 0 - ns tow Output Active from End of Write 5 - ns Notes: tchz, tohz and twhz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (September, 2006, Version 1.3) 5 AMIC Technology, Corp.
7 Timing Waveforms Read Cycle 1 (1) trc Address taa OE toe toh tolz 5 ta tohz 5 tclz 5 tchz 5 DOUT (1, 2, 4) Read Cycle 2 trc Address taa toh toh DOUT (September, 2006, Version 1.3) 6 AMIC Technology, Corp.
8 Timing Waveforms (continued) (1, 3, 4) Read Cycle 3 ta tclz 5 tchz 5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, = VIL. 3. Address valid prior to or coincident with transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. Write Cycle 1 (6) (Write Enable Controlled) twc Address taw twr 3 (4) tcw 5 tas 1 twp 2 WE tdw tdh DIN twhz 7 tow 7 DOUT (September, 2006, Version 1.3) 7 AMIC Technology, Corp.
9 Timing Waveforms (continued) Write Cycle 2 (6) (Chip Enable Controlled) twc Address taw twr 3 tcw 5 tas 1 (4) twp 2 WE tdw tdh DIN twhz 7 DOUT Notes: 1. tas is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (twp) of a low and a low WE. 3. twr is measured form the earliest of or WE going high to the end of the Write cycle. 4. If the low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tcw is measured from the later of going low to the end of Write. 6. OE level is high or low. 7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested. (September, 2006, Version 1.3) 8 AMIC Technology, Corp.
10 AC Test Conditions Input Pulse Levels Input Rise And Fall Time 0V, 3V 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figure 1 and 2 TTL TTL CL 30pF CL 5pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tclz1, tclz2, tohz, tolz, tchz1, tchz2, twhz, and tow Data Retention Characteristics (TA = 0 C to +70 C, -25 C to +85 C or -40 C to +85 C) Symbol Parameter Min. Max. Unit Conditions VDR VCC for Data Retention V VCC - 0.2V ICCDR Data Retention Current - 3 μa tcdr Chip Disable to Data Retention Time 0 - ns tr Operation Recovery Time trc - ns VCC = 2.0V, VCC - 0.2V VIN 0V See Retention Waveform (September, 2006, Version 1.3) 9 AMIC Technology, Corp.
11 Low VCC Data Retention Waveform DATA RETENTION MODE VCC 4.5V 4.5V tcdr VDR 2.0V tr VIH VIH VDR - 0.2V Ordering Information Part No. Access Time (ns) Operating Current Max. (ma) Standby Current Max. (μa) Package A625308A-70SF L Pb-Free DIP A625308AM-70SF L Pb-Free SOP A625308AV-70SF L Pb-Free TSOP (Forward) A625308AM-70SIF L Pb-Free SOP A625308AV-70SIF L Pb-Free TSOP (Forward) A625308AM-70SUF L Pb-Free SOP A625308AV-70SUF L Pb-Free TSOP (Forward) (September, 2006, Version 1.3) 10 AMIC Technology, Corp.
12 Package Information P-DIP 28L Outline Dimensions unit: inches/mm D E1 1 S 14 E C A A2 A1 Base Plane L Seating Plane B B1 e1 α ea Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A B B C D E E e L α ea S Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash. (September, 2006, Version 1.3) 11 AMIC Technology, Corp.
13 Package Information SOP (W.B.) 28L Outline Dimensions unit: inches/mm E H θ L 1 B 14 Detail F D c y S Seating Plane e D y A1 A2 A See Detail F L1 Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A B C D E e H L L S y θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (September, 2006, Version 1.3) 12 AMIC Technology, Corp.
14 Package Information TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm D1 Detail "A" 1 28 E c A2 e A1 A L θ D Detail "A" D y S b Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A b c E L D D e BSC 0.55 BSC S TYP TYP y θ Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (September, 2006, Version 1.3) 13 AMIC Technology, Corp.
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64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 15, 2000 Preliminary
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM Long-term Support NOVEMBER 2016 FEATURES High-speed access time: 45ns, 55ns, 70ns CMOS low power operation 36 mw (typical)
IS62WV25616ALL IS62WV25616BLL
IS62WV25616ALL IS62WV25616BLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM MARCH 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
IS61WV20488FALL IS61/64WV20488FBLL. 2Mx8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
2Mx8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS62/65WV2568DALL IS62/65WV2568DBLL
IS62/65WV2568DALL IS62/65WV2568DBLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
IS61C1024AL IS64C1024AL
IS61C1024AL IS64C1024AL 128K x 8 HIGH-SPEED CMOS STATIC RAM JULY 2015 FEATURES High-speed access time: 12, 15 ns Low active power: 160 mw (typical) Low standby power: 1000 µw (typical) CMOS standby Output
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
IS61/64WV5128EFALL IS61/64WV5128EFBLL. 512Kx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
512Kx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC APRIL 2018 KEY FEATURES A0 A17 A18 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV5128EFALL) 2.4V-3.6V () Error Detection
IS61WV10248ALL IS61WV10248BLL IS64WV10248BLL
1M x 8 HIGH-SPEED CMOS STATIC RAM MARCH 2017 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
IS62WV6416ALL IS62WV6416BLL
IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access time: 45ns, 55ns CMOS low power operation: 30 mw (typical) operating 15 µw (typical)
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
IS63LV1024 IS63LV1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT FEATURES High-speed access times: 8, 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM DEMBER 00 FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical)
IS62WV102416GALL/BLL IS65WV102416GALL/BLL. 1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM. FUNCTIONAL Block Diagram NOVEMBER 2017
1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM NOVEMBER 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
IS61WV102416FALL IS61/64WV102416FBLL. 1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS62C51216AL IS65C51216AL
IS62C51216AL IS65C51216AL 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
IS61WV10248EDBLL IS64WV10248EDBLL
1M x 8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEBRUARY 2013 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
IS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection
IS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
IS61WV10248EEALL IS61/64WV10248EEBLL. 1Mx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM OCTOBER 2018
1Mx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC OCTOBER 2018 KEY FEATURES High-speed access time: 8ns, 10ns, 20ns Single power supply 1.65V-2.2V (IS61WV10248EEALL) 2.4V-3.6V () Error Detection and Correction
IS62C25616EL, IS65C25616EL
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM AUGUST 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 5.0uA
IS62WV102416FALL/BLL IS65WV102416FALL/BLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM MARCH 2018
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL
1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY MAY 2012 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for
Distributed by: www.jameco.com 1-00-31-4242 The content and copyrights of the attached material are the property of its owner. FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption :
Very Low Power/Voltage CMOS SRAM 512K X 16 bit DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) 55ns : 3.0~5.5V 70ns : 2.7~5.5V
FEATURES Wide operation voltage : 24~55V Very low power consumption : = 30V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade:
IS62WV25616EALL/EBLL/ECLL IS65WV25616EBLL/ECLL. 256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM JANUARY 2018
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2018 KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current:
IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES High-speed access time: 35, 45, 55 ns CMOS low power operation 30 mw (typical) operating 6 µw (typical) CMOS standby TTL compatible interface
IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION APRIL 2008 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
IS61WV25616ALL/ALS IS61WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) High-speed access time: 8, 10, 20 ns Low Active Power: 85 mw (typical)
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
28K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY JUNE 2005 FEATURES High-speed access time: 8, 0 ns CMOS low power operation 756 mw (max.) operating @ 8 ns 36 mw (max.) standby @ 8 ns TTL compatible
IS61WV2568EDBLL IS64WV2568EDBLL
ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply
Very Low Power/Voltage CMOS SRAM 1M X 16 bit DESCRIPTION. SPEED (ns) 55ns : 3.0~3.6V 70ns : 2.7~3.6V BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 1M X 16 bit (Dual CE Pins) FEATURES operation voltage : 27~36V Very low power consumption : = 30V C-grade: 45mA (@55ns) operating current I -grade: 46mA (@55ns) operating
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS
IS62WV51216EFALL/BLL IS65WV51216EFALL/BLL. 512Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM AUGUST 2017
512Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC AUGUST 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA
IS62WV25616EHALL/BLL IS65WV25616EHALL/BLL. 256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC PRELIMINARY INFORMATION AUGUST 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.)
Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable FEATURES DESCRIPTION Very low operation voltage : 45 ~ 55V Very low power consumption : = 50V C-grade: 40mA (Max) operating current