ipem 16 MB ASYNC SRAM AS8S512K32PECA 16Mb, 512Kx32 CMOS 5.0V, High Speed Static RAM Integrated Plastic Encapsulated Microcircuit
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- Archibald Walton
- 6 years ago
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1 16 MB ASY SRAM 16Mb, 512Kx32 CMOS 5.0V, High Speed Static RAM Integrated Plastic Encapsulated Microcircuit FEATURES Integrated Real-Time Memory Array Solution No latency or refresh fycles Parallel Read/Write Interface User Confi gurable via multiple enables Random Access Memory Array Fast Access Times: 12, 15, 20, and 25ns TTL Compatible I/O Fully Static, No Clocks Surface Mount Package 68 Lead PLCC, No. 99 JEDEC M0-47AE Small Footprint, Sq. In. Multiple Ground Pins for imum Noise Immunity Single +5V (±5%) Supply Operation DESCRIPTION The AS8S512K32 is a high speed, 5V, 16Mb SRAM. The device is available with access times of 12, 15, 20 and 25ns creating a zero wait state/latency, real-time memory solution. The high speed, 5v supply voltage and control lines,make the device ideal for all your real-time computer memory requirements. The device can be confi gured as a 512K x 32 and used to create a single chip external data /program memory array solution or via use of the individual chip enable lines, be reconfi gured as a 1M x 16 or 2M x 8. The device provides a 50+% space savings when compared to four 512K x 8, 36 pin SOJs. In addition the AS8S512K32 has only a 20pF load on the Addr. lines vs. ~30pF for four plastic SOJs. PIN CONFIGURATIONS AND BLOCK DIAGRAM (PECA Package) D16 A18 A17 E3\ E2\ G\ A16 A15 A14 D D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D D D03 D D02 D D PIN NAMES A0 - A18 Address Inputs - E3\ Chip Enables Write Enables G\ Output Enable D0 - D31 Common Data Input/Output Power (+5V ± 10%) Ground No Connection BYTE CONTROL TABLE Chip Byte Enable Control D0-7 D8-15 E2\ D16-23 E3\ D24-31 A0-A18 G\ K x 32 Memory Array D0-D7 E2\ D8-D15 E3\ D16-D23 D24-D31 D31 A6 A5 A4 A3 A2 A1 A0 A13 A12 A11 A10 A09 A08 A07 D00 1
2 16 MB ASY SRAM ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to -0.5V to 7.0V Operating Temperature t A (Ambient) Industrial -40 o C to +85 o C Enhanced -40 o C to +105 o C Military -55 o C to +125 o C Storage Temperature, Plastic -55 o Cto +125 o C Power Dissipation 5.0 Watts Output Current 20 ma Junction Temperature, TJ 175 o C *Stress greater than those listed under "Absolute imum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those in di cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Parameter Sym Min Typ Units Supply Voltage V CC V Supply Voltage V SS V Input High Voltage V IH V V Input Low Voltage V IL V AC TEST CONDITIONS Input Pulse Levels to 3.0V Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V Output Load Figure 2 Note: For t EHZ, t GHZ and t WLZ, CL=5pF FIG. 2 FIG Ω 480Ω 255Ω 30pF 255Ω 5pF DC ELECTRICAL CHARACTERISTICS Parameter Sym Conditions Min Units 12/15 20/25 ns Operating Power Supply Current I CC1 W#=V IL, I I/O =0mA, Min Cycle ma Standby (TTL) Power Supply Current I CC2 E# V IH, V IN V IL or V IN V IH, f=0mhz ma Full Standby Power Supply Current E# V CC -0.2V I CC3 CMOS V IN V CC -0.2V or V IN 0.2V ma Input Leakage Current I LI V IN =0V to V CC ±5 μa Output Leakage Current I LO V I/O =0V to V CC ±5 μa Ouput High Voltage V OH I OH =-4.0mA 2.4 V Output Low Voltage V OL I OL =8.0mA 0.4 V TRUTH TABLE G# E# W# Mode Output Power X H X Standby HIGH Z I CC2 I CC3 H L H Output Deselect HIGH Z I CC1 L L H Read D OUT I CC1 CAPACITAE (f=1.0mhz, V IN =V CC or V SS ) Parameter Sym Unit Address Lines CI 20 pf Data Lines CD/ 7 pf Write & Output Enable Line W#, G# 20 pf Chip Enable Line E0#, E3# 7 pf X L L Write D IN I CC1 2
3 16 MB ASY SRAM AC CHARACTERISTICS READ CYCLE Parameter Symbol 12ns 15ns 20ns 25ns JEDEC Alt. Min Min Min Min Units Read Cycle Time t AVAV t RC ns Address Access Time t AVV t AA ns Chip Enable Access t ELV t ACS ns Chip Enable to Output in Low Z t ELX t CLZ ns Chip Disable to Output in High Z t EHZ t CHZ ns Output Hold from Address Change t AVX t OH ns Output Enable to Output Valid t GLV t OE ns Output Enable to Output in Low Z t GLX t OLZ ns Output Enable to Output in High Z t GHZ t OHZ ns READ CYCLE 1 - HIGH, G\, E\ LOW tavav A ADDRESS 1 ADDRESS 2 t AVV t AVX DATA 1 DATA 2 READ CYCLE 2 - HIGH tavav A tavv E# telx telv tehz G# tglv t GHZ tglx 3
4 16 MB ASY SRAM AC CHARACTERISTICS READ CYCLE Parameter Symbol 12ns 15ns 20ns 25ns JEDEC Alt. Min Min Min Min Units Write Cycle Time t AVAV t WC ns Chip Enable to End of Write t ELWH t CW ns t ELEH t CW ns Address Setup Time t AVWL t AS ns t AVEL t AS ns Address Valid to End of Write t AVWH t AW ns t AVEH t AW ns Write Pulse Width t WLWH t WP ns t ELEH t WP Write Recovery Time t WHAZ t WR ns t EHAZ t WR Data Hold Time t WHDX t DH ns t EHDZ t DH Write to Output in High Z t WLZ t WHZ ns Data to Write Time t DVWH t DW ns t DVEH t DW Output Active from End of Write t WHX t WLZ WRITE CYCLE 1 - CONTROLLED A tavav E\ telwh tavwh twhax tavwl twlwh D tdvwh twhdx DATA VALID twlz HIGH Z twhx 4
5 16 MB ASY SRAM WRITE CYCLE 2 - E\ CON TROLLED tavav A tavel teleh E\ taveh tehax twleh D tdveh tehdx DATA VALID HIGH Z PACKAGE DRAWING Package No Lead PLCC JEDEC MO-47AE BSC
6 ipem 16 MB ASY SRAM FAMILY PIN MATRIX 64Mb-SRAM, 2M x 32: 3.3V = AS8SLC2M32PEC D16 A18 A17 E3\ E2\ A20 A19 G\ A16 A15 A14 D15 16Mb-SRAM, 512K x 32: 5.0V = AS8S512K32PEC 3.3V = AS8SLC512K32PEC D16 A18 A17 E3\ E2\ G\ A16 A15 A14 D15 4Mb-SRAM, 128K x 32: 5.0V = AS8S128K32PEC D16 E3\ E2\ G\ A16 A15 A14 D15 D17 D17 D D14 D14 D14 D18 D18 D D13 D13 D13 D19 D19 D D12 D12 D D20 D20 D D11 D11 D11 D21 D21 D D10 D10 D10 D22 D22 D D09 D09 D09 D23 D23 D23 AUSTIN SEMICONDUCTOR LD. PLCC 53 D08 D08 D08 [JEDEC MO-47AE] D24 D24 D D07 D07 D07 D25 D25 D D06 D06 D06 D26 D26 D D05 D05 D05 D27 D27 D D04 D04 D D28 D28 D D03 D03 D03 D29 D29 D D02 D02 D02 D30 D30 D D01 D01 D01 D A6 A5 A4 A3 A2 A1 A0 A13 A12 A11 A10 A09 A08 A07 D00 D31 A6 A5 A4 A3 A2 A1 A0 A13 A12 A11 A10 A09 A08 A07 D00 D31 A6 A5 A4 A3 A2 A1 A0 A13 A12 A11 A10 A09 A08 A07 D00 6
7 16 MB ASY SRAM ORDERING INFORMATION Part Number Access Speed Device Grade Availability AS8S512K32PEC MS NA Mechanical Sample Obsolete AS8S512K32PEC ES NA Engineering Sample Obsolete AS8S512K32PEC 12/IT 12ns Industrial Obsolete AS8S512K32PEC 15/IT 15ns Industrial Obsolete OBSOLETE AS8S512K32PEC 20/IT 20ns Industrial Obsolete AS8S512K32PEC 25/IT 25ns Industrial Obsolete AS8S512K32PEC 12/ET 12ns Enhanced Obsolete AS8S512K32PEC 15/ET 15ns Enhanced Obsolete AS8S512K32PEC 20/ET 20ns Enhanced Obsolete AS8S512K32PEC 25/ET 25ns Enhanced Obsolete AS8S512K32PEC 12/XT 12ns Military Obsolete AS8S512K32PEC 15/XT 15ns Military Obsolete AS8S512K32PEC 20/XT 20ns Military Obsolete AS8S512K32PEC 25/XT 25ns Military Obsolete 12/IT 12ns Industrial Production 15/IT 15ns Industrial Production 20/IT 20ns Industrial Production 25/IT 25ns Industrial Production 12/ET 12ns Enhanced Production 15/ET 15ns Enhanced Production 20/ET 20ns Enhanced Production 25/ET 25ns Enhanced Production 12/XT 12ns Military Production 15/XT 15ns Military Production 20/XT 20ns Military Production 25/XT 25ns Military Production 7
8 16 MB ASY SRAM DOCUMENT TITLE 16Mb, 512K x 32, SRAM, 5.0V, sq LD. PLCC, Multi-Chip Package [ipem] REVISION HISTORY Rev # History Release Date Status 0.0 Initial Release September 2005 Advance 0.1 Updated Order Chart January 2009 Advance 0.2 Added Micross Information January 2010 Advance 0.3 Upgraded document to Release status. March 2011 Release Obsoleted and discontinued PEC package which had pin-out errors. Added PECA package refl ecting correct pin-out. Contact Micross for whitepaper addressing the pin-out error on the PEC package. 8
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Distributed by: www.jameco.com 1-00-31-4242 The content and copyrights of the attached material are the property of its owner. FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption :
Functional Block Diagram. Row Decoder. 512 x 512 Memory Array. Column I/O. Input Data Circuit. Column Decoder A 9 A 14. Control Circuit
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1Mb Ultra-Low Power Asynchronous CMOS SRAM. Features. Power Supply (Vcc) Operating Temperature A 0 -A 16 I/O 0 -I/O 7
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4Mb Ultra-Low Power Asynchronous CMOS SRAM. Features. Power Supply (Vcc) Operating Temperature A 0 -A 17 I/O 0 -I/O 15 V CC V SS
4Mb Ultra-Low Power Asynchronous CMOS SRAM 256K 16 bit N04L63W2A Overview The N04L63W2A is an integrated memory device containing a 4 Mbit Static Random Access Memory organized as 262,144 words by 16 bits.
P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM
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M48Z2M1Y M48Z2M1V. 5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER SRAM. Features
M48Z2M1Y M48Z2M1V 5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER SRAM Not recommended for new design Features Integrated, ultra low power SRAM, power-fail control circuit, and batteries Conventional SRAM operation;
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M48Z128 M48Z128Y, M48Z128V
M48Z128 M48Z128Y, M48Z128V 5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM Features Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation; unlimited
A13 A12 A11 A10 ROW DECODER DQ0 INPUT DATA CONTROL WE OE DESCRIPTION: DDC s 32C408B high-speed 4 Megabit SRAM
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32Mbit, 1MX32, 5V CMOS S-RAM MODULE
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256K (32K x 8) Paged Parallel EEPROM AT28C256
Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
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M48Z02 M48Z12. 5 V, 16 Kbit (2 Kb x 8) ZEROPOWER SRAM. Features
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SRM2B256SLMX55/70/10
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89LV1632 16 Megabit (512K x 32Bit) Low Voltage MCM SRAM 16 Megabit (512k x 32bit) SRAM MCM CS 14 Address OE, WE 89LV1632 Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM Ground MCM FEATURES: I/O 7 I/O 815 I/O
M48T02 M48T V, 16 Kbit (2Kb x 8) TIMEKEEPER SRAM
M48T02 M48T12 5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER SRAM FEATURES SUMMARY INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, and POWER-FAIL CONTROL CIRCUIT BYTEWIDE RAM-LIKE CLOCK ACCESS BCD CODED YEAR, MONTH,
M48Z08 M48Z18. 5 V, 64 Kbit (8 Kb x 8) ZEROPOWER SRAM. Features
M48Z08 M48Z18 5 V, 64 Kbit (8 Kb x 8) ZEROPOWER SRAM Features Integrated, ultra low power SRAM and powerfail control circuit Unlimited WRITE cycles READ cycle time equals WRITE cycle time Automatic power-fail
DS1270W 3.3V 16Mb Nonvolatile SRAM
19-5614; Rev 11/10 www.maxim-ic.com 3.3V 16Mb Nonvolatile SRAM FEATURES Five years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write
Obsolete Product(s) - Obsolete Product(s)
5.0 V, 1 Mbit (128 Kb x 8) TIMEKEEPER SRAM Not recommended for new design Features Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal BCD coded year, month,
M440T1MV. 3.3V, 32 Mbit (1024 Kbit x 32) TIMEKEEPER SRAM
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TC55VBM316AFTN/ASTN40,55
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random
EEPROM AS58LC K x 8 EEPROM Radiation Tolerant. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535
128K x 8 EEPROM Radiation Tolerant AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38535 FEATURES High speed: 250ns and 300ns Data Retention: 10 Years Low power dissipation, active current (20mW/MHz (TYP)),
A4 A3 A2 A1 A0 DQ0 DQ15. DQ2 DQ3 Vcc GND DQ4 DQ5 DQ6 DQ7 WE A16 A15 A14 A13 A12
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4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT29BV040A
Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Software Protected Programming Fast Read Access Time 200 ns Low Power Dissipation 15 ma Active Current 50 µa CMOS Standby
M48Z58 M48Z58Y. 5 V, 64 Kbit (8 Kbit x 8) ZEROPOWER SRAM. Features
M48Z58 M48Z58Y 5 V, 64 Kbit (8 Kbit x 8) ZEROPOWER SRAM Features Integrated, ultra low power SRAM, power-fail control circuit, and battery READ cycle time equals WRITE cycle time Automatic power-fail chip
Obsolete Product(s) - Obsolete Product(s)
M48T512Y M48T512V 5.0 or 3.3 V, 4 Mbit (512 Kbit x 8) TIMEKEEPER SRAM Not recommended for new design Features Integrated ultra low power SRAM, real-time clock, power-fail control circuit, battery, and
M48Z35 M48Z35Y. 256 Kbit (32 Kbit x 8) ZEROPOWER SRAM. Features
M48Z35 M48Z35Y 256 Kbit (32 Kbit x 8) ZEROPOWER SRAM Features Integrated, ultra low power SRAM, power-fail control circuit, and battery READ cycle time equals WRITE cycle time Automatic power-fail chip
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55YEM216ABXN is a 4,194,304-bit static random access memory (SRAM) organized
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES High-speed access times: 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7
128K x 8 Static RAM Features High speed t AA = 12 ns Low active power 495 mw (max. 12 ns) Low CMOS standby power 55 mw (max.) 4 mw 2.0V Data Retention Automatic power-down when deselected TTL-compatible
Pin Connection (Top View)
TOSHIBA TC551001BPL/BFL/BFTL/BTRL-70L/85L SILICON GATE CMOS 131,072 WORD x 8 BIT STATIC RAM Description The TC551001BPL is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits
HM K 8 High Speed CMOS SRAM. Description. Features. Interface MATRA MHS. Block Diagram
8K 8 High Speed CMOS SRAM Description The is a high speed CMOS static RAM organized as 8192x8 bits. It is manufactured using MHS high performance CMOS technology. Access times as fast as 15 ns are available
2Mx32 5V NOR FLASH MODULE
2Mx32 5V NOR FLASH MODULE WF2M32-XXX5 FEATURES Access Time of 90, 120, 150ns Packaging: 66 pin, PGA Type, 1.15" square, Hermetic Ceramic HIP (Package 401). 6 lead, Hermetic CQFP (G2U), 22.4mm (0.0") square
PY263/PY264. 8K x 8 REPROGRAMMABLE PROM FEATURES DESCRIPTION. EPROM Technology for reprogramming. Windowed devices for reprogramming.
FEATURES EPROM Technology for reprogramming High Speed 25/35/45/55 ns (Commercial) 25/35/45/55 ns (Military) Low Power Operation: 660 mw Commercial 770 mw Military PY263/PY264 8K x 8 REPROGRAMMABLE PROM
A 4 A 3 A 2 ROW DECODER 64K x 16 RAM Array I/O 1 I/O X 2048 I/O 9 I/O 16
021 CY7C1021 Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 1320 mw (max.) Automatic power-down when deselected Independent Control of Upper and Lower bits Available in
256K x 8 Static RAM Module
41 CYM1441 Features High-density 2-megabit module High-speed CMOS s Access time of 20 ns Low active power 5.3W (max.) SMD technology Separate data I/O 60-pin ZIP package TTL-compatible inputs and outputs
SENSE AMPS POWER DOWN
185 CY7C185 8K x 8 Static RAM Features High speed 15 ns Fast t DOE Low active power 715 mw Low standby power 220 mw CMOS for optimum speed/power Easy memory expansion with,, and OE features TTL-compatible
PRELIMINARY C106A 1. 7C106A 12 7C106A 15 7C106A 20 7C106A 25 7C106A 35 Maximum Access Time (ns) Maximum Operating
1CY 7C10 6A Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 910 mw Low standby power 275 mw 2.0V data retention (optional) 100 µw Automatic power-down when deselected TTL-compatible
CMOS STATIC RAM 1 MEG (128K x 8-BIT)
CMOS STATIC RAM 1 MEG (12K x -BIT) IDT71024 Integrated Device Technology, Inc. FEATURES: 12K x advanced high-speed CMOS static RAM Commercial (0 to 70 C), Industrial (-40 to 5 C) and Military (-55 to 125
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW VOLTAGE CMOS STATIC RAM June 2005 FEATURES High-speed access times: -- 8, 10, 12, 15 ns Automatic power-down when chip is deselected CMOS low power operation -- 345 mw (max.) operating -- 7
16 Meg FPM DRAM AS4LC4M4. 4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT ACTIVE POWER DISSIPATION PERFORMANCE RANGE
4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883 FEATURES Fast Page Mode Operation CAS\-before-RAS\ Refresh Capability RAS\-only and
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
Features High speed t AA = 12 ns Low active power 1320 mw (max.) Low CMOS standby power (Commercial L version) 2.75 mw (max.) 2.0V Data Retention (400 µw at 2.0V retention) Automatic power-down when deselected
Am27C Megabit (524,288 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM
FINAL Am27C040 4 Megabit (524,288 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS Fast access time 90 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved pinout Plug in upgrade
Old Company Name in Catalogs and Other Documents
To our customers, Old Company Name in Catalogs and Other Documents On April 1 st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took
DS1642 Nonvolatile Timekeeping RAM
www.dalsemi.com Nonvolatile Timekeeping RAM FEATURES Integrated NV SRAM, real time clock, crystal, power fail control circuit and lithium energy source Standard JEDEC bytewide 2K x 8 static RAM pinout
I/O 1 I/O 2 I/O 3 A 10 6
Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 467 mw (max, 12 ns L version) Low standby power 0.275 mw (max, L version) 2V data retention ( L version only) Easy memory
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM DESCRIPTION The TC51WHM516AXBN is a 33,554,432-bit pseudo static random access memory(psram) organized
MR4A16B FEATURES BENEFITS INTRODUCTION
MR4A6B FEATURES +3.3 Volt power supply Fast 35 ns read/write cycle SRAM compatible timing Unlimited read & write endurance Data always non-volatile for >0 years at temperature RoHS-compliant small footprint
64K x V Static RAM Module
831V33 Features High-density 3.3V 2-megabit SRAM module High-speed SRAMs Access time of 12 ns Low active power 1.512W (max.) at 12 ns 64 pins Available in ZIP format Functional Description CYM1831V33 64K
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 10, 12 ns CMOS Low Power Operation 1 mw (typical) CMOS standby 125 mw (typical) operating Fully static operation: no clock
RoHS MR256DL08B FEATURES BENEFITS INTRODUCTION
FEATURES 3.3 Volt V DD power supply with a range of 2.7V to 3.6V I/O Voltage range supports wide +.65 to +3.6 Volt interfaces Fast 45 ns read/write cycle SRAM compatible timing Unlimited read & write endurance
128K x 8 Static RAM CY7C1019B CY7C10191B. Features. Functional Description. Logic Block Diagram. Pin Configurations
128K x 8 Static RAM Features High speed t AA = 10, 12, 15 ns CMOS for optimum speed/power Center power/ground pinout Automatic power-down when deselected Easy memory expansion with and OE options Functionally
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2008 FEATURES High-speed access time: 8, 10 ns Operating Current: 50mA (typ.) Standby Current: 700µA (typ.) Multiple center power and ground pins for greater noise
RoHS MR0A16A FEATURES BENEFITS INTRODUCTION. 64K x 16 MRAM Memory
FEATURES 3.3 Volt power supply Fast 35ns read/write cycle SRAM compatible timing Unlimited read & write endurance Commercial, Industrial, and Extended Temperatures Data non-volatile for >20 years at temperature
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
8K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 0 ns CMOS low power operation mw (typical) CMOS standby 25 mw (typical) operating TTL compatible interface levels Single
64K x 1 Static RAM CY7C187. Features. Functional Description. Logic Block Diagram. Pin Configurations. Selection Guide DIP. SOJ Top View.
64K x 1 Static RAM Features High speed 15 ns CMOS for optimum speed/power Low active power 495 mw Low standby power 110 mw TTL compatible inputs and outputs Automatic power-down when deselected Available
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7 A 15 7
Features High speed t AA = 12 ns Low active power 495 mw (max.) Low CMOS standby power 11 mw (max.) (L Version) 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs
UTRON UT K X 8 BIT LOW POWER CMOS SRAM
FEATURES GENERAL DESCRIPTION Access time : 35/70ns (max) Low power consumption: Operating : 60/40 ma (typical) Standby : 3mA (typical) normal ua (typical) L-version 1uA (typical) LL-version Single 5V power
Rad Hard 128K x volt Very Low Power CMOS SRAM M65609E
Features Operating Voltage: 3.3V Access Time: 40 ns Very Low Power Consumption Active: 160 mw (Max) Standby: 70 µw (Typ) Wide Temperature Range: -55 C to +125 C MFP 32 leads 400 Mils Width Package TTL
I/O 1 I/O 2 I/O 3 A 10 6
Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 495 mw (Max, L version) Low standby power 0.275 mw (Max, L version) 2V data retention ( L version only) Easy memory expansion
IS62WV10248EALL/BLL IS65WV10248EALL/BLL. 1Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
1Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating TTL compatible interface levels Single power supply
P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM
P4C5 UTRA IG SPEED K X 4 RESETTABE STATIC CMOS RAM FEATURES Full CMOS, 6T Cell igh Speed (Equal Access and Cycle Times) //5//5 (Commercial) 5//5/35 (Military) Chip Clear Function ow Power Operation Separate
4-Megabit (512K x 8) OTP EPROM AT27C040
Features Fast Read Access Time 70 ns Low Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 32-lead PDIP 32-lead PLCC 32-lead TSOP 5V ± 10% Supply High Reliability
RMLV0808BGSB - 4S2. 8Mb Advanced LPSRAM (1024k word 8bit) Description. Features. Part Name Information. R10DS0232EJ0200 Rev
8Mb Advanced LPSRAM (1024k word 8bit) Description The RMLV0808BGSB is a family of 8-Mbit static RAMs organized 1,048,576-word 8-bit, fabricated by Renesas s high-performance Advanced LPSRAM technologies.
524,288-Word x 16-Bit or 1,048,576-Word x 8-Bit One Time PROM
Semiconductor 524,288Word x 16Bit or 1,048,576Word x 8Bit One Time PROM 1A DESCRIPTION The is a 8Mbit electrically Programmable ReadOnly Memory whose configuration can be electrically switched between
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM JULY 2007 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JULY 2006 FEATURES High-speed access time: 10, 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS stand-by
RoHS MR0A08B INTRODUCTION. 128K x 8 MRAM
FEATURES 3.3 Volt power supply Fast 35 ns read/write cycle SRAM compatible timing Native non-volatility Unlimited read & write endurance Data always non-volatile for >20 years at temperature Commercial
8K x 8 EPROM CY27C64. Features. Functional Description. fax id: 3006
1CY 27C6 4 fax id: 3006 CY27C64 Features CMOS for optimum speed/power Windowed for reprogrammability High speed 0 ns (commercial) Low power 40 mw (commercial) 30 mw (military) Super low standby power Less
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM MAY 2012 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
Rad. Tolerant 8K x 8-5 volts Very Low Power CMOS SRAM AT65609EHW
Features Operating Voltage: 5V Access Time: 40ns Very Low Power Consumption Active: 440mW (Max) Standby: 10mW (Typ) Wide Temperature Range: -55 C to +125 C 600 Mils Width Package: SB28 TTL Compatible Inputs
PIN DESCRIPTION FIG. 1 PIN CONFIGURATIONS
FERE P Memory olution P-26L (HRC) P-262L (HRC) exas Itruments M32LC31 RIC Memory olution MPC6 (Power uic) Random ccess Memory rray Fast ccess imes:, 15, 17, 2 and 25 Individual yte Enables ser confi guration
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005 FEATURES IS61C6416AL and High-speed access time: 12 ns, 15ns Low Active Power: 175 mw (typical) Low Standby Power: 1 mw (typical) CMOS standby and High-speed