MR4A16B FEATURES BENEFITS INTRODUCTION

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TSOP package All products meet MSL-3 moisture sensitivity level BENEFITS One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs Improves reliability by

1 MR4A6B FEATURES +3.3 Volt power supply Fast 35 ns read/write cycle SRAM compatible timing Unlimited read & write endurance Data always non-volatile for >0 years at temperature RoHS-compliant small footprint BGA and TSOP package All products meet MSL-3 moisture sensitivity level BENEFITS One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs Improves reliability by replacing battery-backed SRAM M x 6 MRAM INTRODUCTION The MR4A6B is a 6,777,6-bit magnetoresistive random access memory (MRAM) device organized as,04,576 words of 6 bits. The MR4A6B offers RoHS SRAM compatible 35 ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 0 years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. To simplify fault tolerant design, the MR4A6B includes internal single bit error correction code with 7 ECC parity bits for every 64 data bits. The MR4A6B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR4A6B is available in a small footprint 4-pin ball grid array (BGA) package and a 54-pin thin small outline package (TSOP Type ). These packages are compatible with similar low-power SRAM products and other nonvolatile RAM products. The MR4A6B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial temperature (0 to +70 C), and industrial temperature (-40 to +5 C) operating temperature options. CONTENTS. DEVICE PIN ASSIGNMENT ELECTRICAL SPECIFICATIONS TIMING SPECIFICATIONS ORDERING INFORMATION MECHANICAL DRAWING REVISION HISTORY... 5 How to Reach Us

2 . DEVICE PIN ASSIGNMENT MR4A6B Figure. Block Diagram G OUTPUT ENABLE BUFFER UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE A[9:0] 0 ADDRESS BUFFER 0 0 ROW DECODER COLUMN DECODER UPPER BYTE OUTPUT BUFFER E W UB LB CHIP ENABLE BUFFER WRITE ENABLE BUFFER BYTE ENABLE BUFFER UB LB M x 6 BIT MEMORY ARRAY 6 6 SENSE AMPS FINAL WRITE DRIVERS UPPER BYTE WRITE ENABLE LOWER BYTE WRITE ENABLE LOWER BYTE OUTPUT BUFFER UPPER BYTE WRITE DRIVER LOWER BYTE WRITE DRIVER DQU[5:] DQL[7:0] Table. Pin Functions Signal Name A E W G UB LB DQ V DD V SS DC Function Address Input Chip Enable Write Enable Output Enable Upper Byte Enable Lower Byte Enable Data I/O Power Supply Ground Do Not Connect No Connection

3 DEVICE PIN ASSIGNMENT MR4A6B Figure. Pin Diagrams for Available Packages (Top View) LB G A0 A A A DQU UB A3 A4 E DQL0 B DQU9 DQU0 A5 A6 DQL DQL C VSS DQU A5 A3 A0 DQL3 VDD D VDD DQU DC A6 DQL4 VSS E DQU4 DQU3 A4 DQU5 A A A A9 A7 A7 DQL5 DQL6 F W DQL7 G A A9 H A9 A0 A A A3 A4 E DQ0 DQ DQ DQ3 VDD VSS DQ4 DQ5 DQ6 DQ7 W A5 A6 A7 A A A A7 A6 A5 G UB LB DQ5 DQ4 DQ3 DQ VSS VDD DQ DQ0 DQ9 DQ DC A4 A3 A A A0 4-Pin BGA 54-Pin TSOP Table. Operating Modes E G W LB UB Mode V DD Current DQL[7:0] DQU[5:] H X X X X Not selected I SB, I SB Hi-Z Hi-Z L H H X X Output disabled I DDR Hi-Z Hi-Z L X X H H Output disabled I DDR Hi-Z Hi-Z L L H L H Lower Byte Read I DDR D Out Hi-Z L L H H L Upper Byte Read I DDR Hi-Z D Out L L H L L Word Read I DDR D Out D Out L X L L H Lower Byte Write I DDW D in Hi-Z L X L H L Upper Byte Write I DDW Hi-Z D in L X L L L Word Write I DDW D in D in H = high, L = low, X = don t care Hi-Z = high impedance 3

4 . ELECTRICAL SPECIFICATIONS MR4A6B Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field greater than the maximum field intensity specified in the maximum ratings. Symbol Parameter Conditions Value Unit V DD Supply voltage -0.5 to 4.0 V V IN Voltage on an pin -0.5 to V DD V I OUT Output current per pin ±0 ma P D Package power dissipation W T BIAS Temperature under bias Commercial -0 to 5 C Industrial -45 to 95 C T stg Storage Temperature -55 to 50 C T Lead Lead temperature during solder (3 minute max) Table. Absolute Maximum Ratings 60 C H max_write Maximum magnetic field During Write H max_read Maximum magnetic field During Read or Standby 000 A/m Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. All voltages are referenced to V SS. The DC value of V IN must not exceed actual applied V DD by more than 0.5V. The AC value of V IN must not exceed applied V DD by more than V for 0ns with I IN limited to less than 0mA. 3 Power dissipation capability depends on package characteristics and use environment. 4

5 Electrical Specifications Symbol Parameter Temp Range Min Typical Max Unit V DD Power supply voltage V V WI Write inhibit voltage V V IH Input high voltage. - V DD V V IL Input low voltage V T A Temperature under bias Table. Operating Conditions MR4A6B Commercial 0-70 C Industrial C There is a ms startup time once V DD exceeds V DD, (min). See Power Up and Power Down Sequencing below. V IH (max) = V DD V DC ; V IH (max) = V DD +.0 V AC (pulse width 0 ns) for I 0.0 ma. 3 V IL (min) = -0.5 V DC ; V IL (min) = -.0 V AC (pulse width 0 ns) for I 0.0 ma. Power Up and Power Down Sequencing The MRAM is protected from write operations whenever V DD is less than V WI. As soon as V DD exceeds V DD (min), there is a startup time of ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track V DD on power up to V DD - 0. V or V IH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that a signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where V DD goes below V WI, writes are protected and a startup time must be observed when power returns above V DD (min). Figure. Power Up and Power Down Diagram V WI VDD ms STARTUP BROWNOUT or POWER LOSS ms RECOVER READ/WRITE INHIBITED NORMAL OPERATION READ/WRITE INHIBITED NORMAL OPERATION VIH VIH E W 5

6 Electrical Specifications Table.3 DC Characteristics MR4A6B Symbol Parameter Conditions Min Max Unit I lkg(i) Input leakage current All - ± μa I lkg(o) Output leakage current All - ± μa V OL Output low voltage I OL = +4 ma V I OL = +00 μa V SS + 0. V V OH Output high voltage I OH = -4 ma.4 - V I OH = -00 μa V DD V Table.4 Power Supply Characteristics Symbol Parameter Typical Max Unit I DDR AC active supply current - read modes (I OUT = 0 ma, V DD = max) 60 6 ma I DDW AC active supply current - write modes (V DD = max) 5 0 ma I SB I SB AC standby current (V DD = max, E = V IH ) no other restrictions on other inputs CMOS standby current (E V DD - 0. V and V In V + 0. V or V - 0. V) SS DD (V DD = max, f = 0 MHz) 9 4 ma 5 9 ma All active current measurements are measured with one address transition per cycle and at minimum cycle time. 6

7 3. TIMING SPECIFICATIONS MR4A6B Table 3. Capacitance Symbol Parameter Typical Max Unit C In Address input capacitance - 6 pf C In Control input capacitance - 6 pf C I/O Input/Output capacitance - pf f =.0 MHz, dv = 3.0 V, T A = 5 C, periodically sampled rather than 00% tested. Table 3. AC Measurement Conditions Parameter Value Unit Logic input timing measurement reference level.5 V Logic output timing measurement reference level.5 V Logic input pulse levels 0 or 3.0 V Input rise/fall time ns Output load for low and high impedance parameters See Figure 3. Output load for all other timing parameters See Figure 3. Figure 3. Output Load Test Low and High Output Z D = 50 Ω R L = 50 Ω V =.5 V L Figure 3. Output Load Test All Others 3.3 V Output 435 Ω 590 Ω 5 pf 7

8 Timing Specifications Read Mode Table 3.3 Read Cycle Timing MR4A6B Symbol Parameter Min Max Unit t AVAV Read cycle time 35 - ns t AVQV Address access time - 35 ns t ELQV Enable access time - 35 ns t GLQV Output enable access time - 5 ns t BLQV Byte enable access time - 5 ns t AXQX Output hold from address change 3 - ns t ELQX Enable low to output active ns t GLQX Output enable low to output active ns t BLQX Byte enable low to output active ns t EHQZ Enable high to output Hi-Z ns t GHQZ Output enable high to output Hi-Z ns t BHQZ Byte high to output Hi-Z ns W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. 3 This parameter is sampled and not 00% tested. Transition is measured ±00 mv from the steady-state voltage. A (ADDRESS) Figure 3.3A Read Cycle t AVAV t AXQX Q (DATA OUT) Previous Data Valid Data Valid t AVQV Note: Device is continuously selected (E V IL, G V IL ). Figure 3.3B Read Cycle t AVAV A (ADDRESS) E (CHIP ENABLE) t AVQV t ELQV t ELQX t EHQZ G (OUTPUT ENABLE) LB, UB (BYTE ENABLE) t GLQX t GLQV t GHQZ Q (DATA OUT) t BLQX t BLQV Data Valid t BHQZ

9 Timing Specifications Table 3.4 Write Cycle Timing (W Controlled) MR4A6B Symbol Parameter Min Max Unit t AVAV Write cycle time 35 - ns t AVWL Address set-up time 0 - ns t AVWH Address valid to end of write (G high) 0 - ns t AVWH Address valid to end of write (G low) 0 - ns t WLWH t WLEH Write pulse width (G high) 5 - ns t WLWH t WLEH Write pulse width (G low) 5 - ns t DVWH Data valid to end of write 0 - ns t WHDX Data hold time 0 - ns t WLQZ Write low to data Hi-Z ns t WHQX Write high to output active ns t WHAX Write recovery time - ns All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. 3 This parameter is sampled and not 00% tested. Transition is measured ±00 mv from the steady-state voltage. At any given voltage or temperate, t WLQZ (max) < t WHQX (min). A (ADDRESS) Figure 3.4 Write Cycle Timing (W Controlled) tavav tavwh twhax E (CHIP ENABLE) W (WRITE ENABLE) twleh twlwh tavwl UB, LB (BYTE ENABLED) tdvwh twhdx D (DATA IN) DATA VALID twlqz Q (DATA OUT) Hi -Z Hi -Z twhqx 9

10 Timing Specifications Table 3.5 Write Cycle Timing (E Controlled) MR4A6B Symbol Parameter Min Max Unit t AVAV Write cycle time 35 - ns t AVEL Address set-up time 0 - ns t AVEH Address valid to end of write (G high) 0 - ns t AVEH Address valid to end of write (G low) 0 - ns t ELEH t ELWH Enable to end of write (G high) 5 - ns t ELEH t ELWH Enable to end of write (G low) ns t DVEH Data valid to end of write 0 - ns t EHDX Data hold time 0 - ns t EHAX Write recovery time - ns All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal must remain in steady-state high for a minimum of ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. 3 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 3.5 Write Cycle Timing (E Controlled) A (ADDRESS) t AVAV t AVEH t EHAX E (CHIP ENABLE) t ELEH t AVEL t ELWH W (WRITE ENABLE) UB, LB (BYTE ENABLE) t DVEH t EHDX D (DATA IN) Data Valid Q (DATA OUT) Hi-Z 0

11 Timing Specifications Table 3.6 Write Cycle Timing 3 (LB/UB Controlled) MR4A6B Symbol Parameter Min Max Unit t AVAV Write cycle time 35 - ns t AVBL Address set-up time 0 - ns t AVBH Address valid to end of write (G high) 0 - ns t AVBH Address valid to end of write (G low) 0 - ns t BLEH t BLWH Write pulse width (G high) 5 - ns t BLEH t BLWH Write pulse width (G low) 5 - ns t DVBH Data valid to end of write 0 - ns t BHDX Data hold time 0 - ns t BHAX Write recovery time - ns All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of ns. If both byte control signals are asserted, the two signals must have no more than ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. A (ADDRESS) Figure 3.6 Write Cycle Timing 3 (LB/UB Controlled) tavav taveh tbhax E (CHIP ENABLE) W (WRITE ENABLE) UB, LB (BYTE ENABLED) tavbl tbleh tblwh tdvbh tbhdx D (DATA IN) Data Valid Q (DATA OUT) Hi -Z Hi -Z

12 MR4A6B 4. ORDERING INFORMATION Figure 4. Part Numbering System MR 4 A 6 B C MA 35 R Carrier Speed Package Temperature Range Blank = Tray, R = Tape & Reel 35 ns MA = FBGA, YS = TSOP Blank= Commercial (0 to +70 C), C= Industrial (-40 to +5 C ) Revision Data Width Type 6 = 6-bit A = Asynchronous Density 4 =6Mb Magnetoresistive RAM Table 4. Available Parts Grade Temp Range Package 4-BGA Commercial 0 to +70 C 54-TSOP 4-BGA Industrial -40 to +5 C 54-TSOP Shipping Container Trays Tape & Reel Trays Tape & Reel Tray Tape & Reel Tray Tape & Reel Order Part Number MR4A6BMA35 MR4A6BMA35R MR4A6BYS35 MR4A6BYS35R MR4A6BCMA35 MR4A6BCMA35R MR4A6BCYS35 MR4A6BCYS35R

13 MR4A6B 5. MECHANICAL DRAWING Figure 5. 4-FBGA BOTTOM VIEW (DATUM B) TOP VIEW PIN A INDEX PIN A INDEX (DATUM A) A B C D E F G H SEATING PLANE SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS ø 0.35mm Ref Min Nominal Max A A b D 0.00 BSC E 0.00 BSC D 5.5 BSC E 3.75 BSC DE BSC SE BSC e 0.75 BSC Ref Tolerance of, from and position aaa 0.0 bbb 0.0 ddd 0.0 eee 0.5 fff 0.0 Print Version Not To Scale. Dimensions in Millimeters.. The e represents the basic solder ball grid pitch. 3. b is measurable at the maximum solder ball diameter in a plane parallel to datum C. 4. Dimension ddd is measured parallel to primary datum C. 5. Primary datum C (seating plane) is defined by the crowns of the solder balls. 6. Package dimensions refer to JEDEC MO-05 Rev. G. 3

14 θ θ MR4A6B 5. MECHANICAL DRAWING Figure TSOP D 54 A A A θ θ3 L E E 7 c e b 0.0(0.00) M R 0.7 REF. R 0.(0.00)R C SEATING PLANE 0.0 C 0.665(0.06)R GAGE 0.5 mm Ref Min Nominal Max A.0 A A b c D E E e 0.0 BSC L L 0.0 REF R R θ 0 - θ θ 5 REF θ3 5 REF Print Version Not To Scale. Dimensions in Millimeters.. Package dimensions refer to JEDEC MS-04 4

15 MR4A6B 6. REVISION HISTORY Rev Date Description of Change May 9, 009 Establish Speed and Power Specifications July 7, 009 Increase BGA Package to mm x mm 3 Nov 6, 009 Changed ball definition of H6 to A9 and G to in Figure.. 4 Mar 0, 00 Changed speed marking and timing specs to 35 ns part. Changed BGA package to 0 mm x 0mm 5 Apr 7, 00 Added 54-TSOP package options. 6 Oct 7, 0 7 Oct, 0 August 6, 0 9 August 7, 03 Added AEC-Q00 Grade product option. Max. magnetic field during write (H max_write ) increased to 000 A/m. Revised IDDW typical from0 to 5mA, max from TBD to 0mA; IDDR max from TBD to 6mA; ISB typical from to 9ma; ISB from typical 7 to 5mA. Added note to BGA package option products are MSL-6 only, MSL-3 qualification underway. Fixed typo on BGA drawing: Top View incorrectly labeled Bottom View. Figure. Power Up and Power Down Timing redrawn. Added 54-TSOP illustrations. Reformatted all parametric tables. Reformatted Table 4. Ordering Part Numbers. Corrected the AEC Q-00 Grade A ordering option to be available in 54-TSOP, not 4- BGA. 9. Jaunary 9, 04 Corrected minor typo in Ordering PN table. 0 April 5, 04 AEC-Q00 removed until qualified product is available. September 7, 04 4-BGA package options moisture sensitivity level upgraded to MSL-5.. May 9, 05 Revised Everspin contact information.. June, 05 Corrected Japan Sales Office telephone number..3 July 9, 05 Minor correction to the ddd tolerance value for the BGA Package (Note 4.).4 March, 06 The BGA package moisture sensitivity level rating is changed to MSL-6 in Table November, 06 The BGA package moisture sensitivity level rating is changed to MSL-5 in Table May 09, 07 All products meet MSL-3 moisture sensitivity level.7 March 3, 0 Updated the Contact Us table 5

16 7. HOW TO CONTACT US How to Reach Us: Home Page: World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 00 Chandler, Arizona 56 Tel: MRAM (676) Local Tel: Fax: support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com Everspin Technologies, Inc. Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including Typicals must be validated for each customer application by customer s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Filename: EST0035_MR4A6B_Datasheet_Rev

RoHS MR256DL08B FEATURES BENEFITS INTRODUCTION

RoHS MR256DL08B FEATURES BENEFITS INTRODUCTION FEATURES 3.3 Volt V DD power supply with a range of 2.7V to 3.6V I/O Voltage range supports wide +.65 to +3.6 Volt interfaces Fast 45 ns read/write cycle SRAM compatible timing Unlimited read & write endurance