RoHS MR4A08B FEATURES BENEFITS INTRODUCTION

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TSOP2 packages ll products meet MSL-3 moisture sensitivity level 2M x 8 MRM Memory BENEFITS One memory replaces FLSH, SRM, EEPROM and BBSRM in systems for simpler, more efficient designs Improves

1 MR408B FETURES +3.3 Volt power supply Fast 35 ns read/write cycle SRM compatible timing Unlimited read & write endurance Data always non-volatile for >20-years at temperature RoHS-compliant small footprint BG and TSOP2 packages ll products meet MSL-3 moisture sensitivity level 2M x 8 MRM Memory BENEFITS One memory replaces FLSH, SRM, EEPROM and BBSRM in systems for simpler, more efficient designs Improves reliability by replacing battery-backed SRM INTRODUCTION The MR408B is a 6,777,26-bit magnetoresistive random access memory (MRM) device organized as 2,097,52 words of 8 bits. The MR408B offers SRM compatible 35ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by lowvoltage inhibit circuitry to prevent writes with voltage out of specification. The RoHS MR408B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR408B is available in small footprint 400-mil, 44-lead plastic small-outline TSOP type-ii package or 0 mm x 0 mm, 48-pin ball grid array (BG) package with 0.75 mm ball centers. These packages are compatible with similar low-power SRM products and other non-volatile RM products. The MR408B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial (0 to +70 C) and industrial (-40 to +85 C) operating temperature range options. CONTENTS. DEVICE PIN SSIGNMENT ELECTRICL SPECIFICTIONS TIMING SPECIFICTIONS ORDERING INFORMTION MECHNICL DRWING REVISION HISTORY... 4 How to Reach Us... 5 MR408B Rev /207

2 . DEVICE PIN SSIGNMENT MR408B Figure. Block Diagram G OUTPUT ENBLE BUFFER OUTPUT ENBLE [20:0] 2 DDRESS BUFFER 0 ROW DECODER COLUMN DECODER E CHIP ENBLE BUFFER 8 SENSE MPS 8 OUTPUT BUFFER 8 W WRITE ENBLE BUFFER 2M x 8 BIT MEMORY RRY FINL 8 8 WRITE WRITE 8 DRIVERS DRIVER DQ[7:0] WRITE ENBLE Signal Name E W G DQ V DD V SS DC NC Function ddress Input Chip Enable Write Enable Output Enable Data I/O Power Supply Ground Do Not Connect No Connection Table. Pin Functions 2 MR408B Rev /207

3 DEVICE PIN SSIGNMENT MR408B Figure.2 Pin Diagrams for vailable Packages (Top View) DC E VDD VSS W DC 2 DC DC DC G VSS VDD DC DC DC DC G DC NC DC E DC B DQ NC NC DQ C VSS VDD DQ 3 NC DQ DQ DQ DC DQ NC NC 20 VDD VSS DQ W NC 9 D E F G H 44 Pin TSOP2 48 Pin FBG Table.2 Operating Modes E G W Mode V DD Current DQ[7:0] 2 H X X Not selected I SB, I SB2 Hi-Z L H H Output disabled I DDR Hi-Z L L H Byte Read I DDR D Out L X L Byte Write I DDW D in H = high, L = low, X = don t care 2 Hi-Z = high impedance 3 MR408B Rev /207

4 2. ELECTRICL SPECIFICTIONS MR408B bsolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Parameter Symbol Value Unit Supply voltage 2 V DD -0.5 to 4.0 V Voltage on any pin 2 V IN -0.5 to V DD Output current per pin I OUT ±20 m Package power dissipation 3 P D W Temperature under bias MR408B (Commercial) MR408BC (Industrial) T BIS -0 to to 95 Storage Temperature T stg -55 to 50 C Lead temperature during solder (3 minute max) T Lead 260 C Maximum magnetic field during write MR408B (ll Temperatures) Table 2. bsolute Maximum Ratings V C H max_write 8000 /m Maximum magnetic field during read or standby H max_read 8000 /m Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 ll voltages are referenced to V SS. 3 Power dissipation capability depends on package characteristics and use environment. 4 MR408B Rev /207

5 Electrical Specifications Table 2.2 Operating Conditions MR408B Parameter Symbol Min Typical Max Unit Power supply voltage V DD V Write inhibit voltage V WI V Input high voltage V IH V DD V Input low voltage V IL V Temperature under bias MR408B (Commercial) MR408BC (Industrial) T C. There is a 2 ms startup time once V DD exceeds V DD, (min). See Power Up and Power Down Sequencing below. 2. V IH (max) = V DD V DC ; V IH (max) = V DD V C (pulse width 0 ns) for I 20.0 m. 3. V IL (min) = -0.5 V DC ; V IL (min) = -2.0 V C (pulse width 0 ns) for I 20.0 m. Power Up and Power Down Sequencing MRM is protected from write operations whenever V DD is less than V WI. s soon as V DD exceeds V DD (min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track V DD on power up to V DD V or V IH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. ny logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where V DD goes below V WI, writes are protected and a startup time must be observed when power returns above V DD (min). Figure 2. Power Up and Power Down Diagram V WIDD VDD STRTUP 2 ms RED/WRITE INHIBITED NORML OPERTION BROWNOUT or POWER LOSS RED/WRITE INHIBITED 2 ms RECOVER NORML OPERTION VIH VIH E W 5 MR408B Rev /207

6 Electrical Specifications Table 2.3 DC Characteristics MR408B Parameter Symbol Min Typical Max Unit Input leakage current I lkg(i) - - ± μ Output leakage current I lkg(o) - - ± μ Output low voltage (I OL = +4 m) (I OL = +00 μ) Output high voltage (I OL = -4 m) (I OL = -00 μ) V OL V SS V V OH V V DD Table 2.4 Power Supply Characteristics Parameter Symbol Typical Max Unit C active supply current - read modes (I OUT = 0 m, V DD = max) I DDR m C active supply current - write modes (V DD = max) I DDW m C standby current (V DD = max, E = V IH ) no other restrictions on other inputs CMOS standby current (E V DD V and V In V V or V V) SS DD (V DD = max, f = 0 MHz) I SB 9 4 m I SB2 5 9 m ll active current measurements are measured with one address transition per cycle and at minimum cycle time. 6 MR408B Rev /207

7 3. TIMING SPECIFICTIONS MR408B Table 3. Capacitance Parameter Symbol Typical Max Unit ddress input capacitance C In - 6 pf Control input capacitance C In - 6 pf Input/Output capacitance C I/O - 8 pf f =.0 MHz, dv = 3.0 V, T = 25 C, periodically sampled rather than 00% tested. Table 3.2 C Measurement Conditions Parameter Value Unit Logic input timing measurement reference level.5 V Logic output timing measurement reference level.5 V Logic input pulse levels 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 3. Output load for all other timing parameters See Figure 3.2 Figure 3. Output Load Test Low and High Output Z D = 50 Ω R L = 50 Ω V =.5 V L Figure 3.2 Output Load Test ll Others 3.3 V Output 435 Ω 590 Ω 5 pf 7 MR408B Rev /207

8 Timing Specifications Read Mode Table 3.3 Read Cycle Timing MR408B Parameter Symbol Min Max Unit Read cycle time t VV 35 - ns ddress access time t VQV - 35 ns Enable access time 2 t ELQV - 35 ns Output enable access time t GLQV - 5 ns Output hold from address change t XQX 3 - ns Enable low to output active 3 t ELQX 3 - ns Output enable low to output active 3 t GLQX 0 - ns Enable high to output Hi-Z 3 t EHQZ 0 5 ns Output enable high to output Hi-Z 3 t GHQZ 0 0 ns W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. 2 ddresses valid before or at the same time E goes low. 3 This parameter is sampled and not 00% tested. Transition is measured ±200 mv from the steady-state voltage. (DDRESS) Figure 3.3 Read Cycle t VV t XQX Q (DT OUT) Previous Data Valid Data Valid t VQV Note: Device is continuously selected (E V IL, G V IL ). Figure 3.3B Read Cycle 2 (DDRESS) t VV t VQV E (CHIP ENBLE) t ELQV t ELQX t EHQZ G (OUTPUT ENBLE) Q (DT OUT) t GLQX t GLQV Data Valid t GHQZ 8 MR408B Rev /207

9 Timing Specifications Table 3.4 Write Cycle Timing (W Controlled) MR408B Parameter Symbol Min Max Unit Write cycle time 2 t VV 35 - ns ddress set-up time t VWL 0 - ns ddress valid to end of write (G high) t VWH 8 - ns ddress valid to end of write (G low) t VWH 20 - ns Write pulse width (G high) Write pulse width (G low) t WLWH t WLEH 5 - ns t WLWH t WLEH 5 - ns Data valid to end of write t DVWH 0 - ns Data hold time t WHDX 0 - ns Write low to data Hi-Z 3 t WLQZ 0 2 ns Write high to output active 3 t WHQX 3 - ns Write recovery time t WHX 2 - ns ll write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. fter W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 ll write cycle timings are referenced from the last valid address to the first transition address. 3 This parameter is sampled and not 00% tested. Transition is measured ±200 mv from the steady-state voltage. t any given voltage or temperature, t WLQZ (max) < t WHQX (min) Figure 3.4 Write Cycle Timing (W Controlled) (DDRESS) t VV t VWH t WHX E (CHIP ENBLE) W (WRITE ENBLE) t WLEH t WLWH t VWL t DVWH t WHDX D (DT IN) DT VLID Q (DT OUT) t WLQZ Hi -Z Hi -Z t WHQX 9 MR408B Rev /207

10 Timing Specifications MR408B Table 3.5 Write Cycle Timing 2 (E Controlled) Parameter Symbol Min Max Unit Write cycle time 2 t VV 35 - ns ddress set-up time t VEL 0 - ns ddress valid to end of write (G high) t VEH 8 - ns ddress valid to end of write (G low) t VEH 20 - ns Enable to end of write (G high) Enable to end of write (G low) 3 t ELEH t ELWH 5 - ns t ELEH t ELWH 5 - ns Data valid to end of write t DVEH 0 - ns Data hold time t EHDX 0 - ns Write recovery time t EHX 2 - ns ll write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. fter W, E or UB/ LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 ll write cycle timings are referenced from the last valid address to the first transition address. 3 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 3.5 Write Cycle Timing 2 (E Controlled) t VV (DDRESS) t VEH t EHX E (CHIP ENBLE) t ELEH t VEL t ELWH W (WRITE ENBLE) t DVEH t EHDX D (DT IN) Data Valid Q (DT OUT) Hi-Z 0 MR408B Rev /207

11 MR408B 4. ORDERING INFORMTION Figure 4. Part Numbering System MR 4 08 B C YS 35 R Carrier (Blank = Tray, R = Tape & Reel) Speed (35 ns) Package (YS = TSOP2, M = FBG) Temperature Range (Blank= Commercial (0 to +70 C), C= Industrial (-40 to +85 C) Revision Data Width (08 = 8-Bit) Type ( = synchronous) Density (4 =6Mb) Magnetoresistive RM (MR) Table 4. vailable Parts Grade Temp Range Package Shipping Container Part Number Commercial 0 to +70 C 44-TSOP2 Tray MR408BYS35 Tape and Reel MR408BYS35R 48-BG Tray MR408BM35 Tape and Reel MR408BM35R Industrial -40 to +85 C 44-TSOP2 Tray MR408BCYS35 Tape and Reel MR408BCYS35R 48-BG Tray MR408BCM35 Tape and Reel MR408BCM35R MR408B Rev /207

12 5. MECHNICL DRWING Figure 5. TSOP2 MR408B Print Version Not To Scale. Dimensions and tolerances per SME Y4.5M Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DM bar protrusions. DM Bar protrusion shall not cause the lead width to exceed MR408B Rev /207

13 Mechanical Drawings MR408B Figure 5.2 FBG BOTTOM VIEW (DTUM B) TOP VIEW PIN INDEX PIN INDEX (DTUM ) B C D E F G H SETING PLNE SOLDER BLL DIMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIMETER IS ø 0.35mm Ref Min Nominal Max b D 0.00 BSC E 0.00 BSC D 5.25 BSC E 3.75 BSC DE BSC SE BSC e 0.75 BSC Ref Tolerance of, from and position aaa 0.0 bbb 0.0 ddd 0.0 eee 0.5 fff 0.08 Not To Scale. Dimensions in Millimeters. 2. The e represents the basic solder ball grid pitch. 3. b is measurable at the maximum solder ball diameter in a plane parallel to datum C. 4. Dimension ddd is measured parallel to primary datum C. 5. Primary datum C (seating plane) is defined by the crowns of the solder balls. 6. Package dimensions refer to JEDEC MO-205 Rev. G. 3 MR408B Rev /207

14 MR408B 6. REVISION HISTORY Revision Date Description of Change May 29, 2009 Establish Speed and Power Specifications 2 July 27, 2009 Increase BG Package to mm x mm 3 May 5, 200 Changed speed marking and timing specs to 35 ns part. Changed BG package to 0 mm x 0mm 4 ug 0, 20 Max. magnetic field during write (H max_write ) increased to 8000 /m. 5 March, 202 dded preliminary information on EC-Q00 Grade. 6 September 20, 203 Replaced missing V OH specification line in Table pril 25, 204 EC-Q00 removed until qualified product is available. 8 September 7, BG package options moisture sensitivity level upgraded to MSL May 9, 205 Revised Everspin contact information. 8.2 June, 205 Corrected Japan Sales Office telephone number. 8.3 July 29, 205 Minor correction to the ddd tolerance value for the BG Package (Note 4.) 8.4 March, 206 The BG package moisture sensitivity level rating is changed to MSL-6 in Table November 22, 206 The BG package moisture sensitivity level rating is changed to MSL-5 in Table May 9, 207 The BG package moisture sensitivity level is upgraded to MSL-3 4 MR408B Rev /207

15 MR408B 7. HOW TO CONTCT US Home Page: World Wide Information Request WW Headquarters - Chandler, Z 347 N. lma School Road, Suite 220 Chandler, rizona Tel: MRM (6726) Local Tel: Fax: Europe, Middle East and frica Everspin Sales Office Tel: Japan Everspin Sales Office Tel: + (79) sia Pacific Everspin Sales Office Tel: Fax: Everspin Technologies, Inc. Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters including Typicals must be validated for each customer application by customer s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin and the Everspin logo are trademarks of Everspin Technologies, Inc. ll other product or service names are the property of their respective owners., Inc. Filename: EST00356_MR408B_Datasheet_Rev MR408B Rev /207

16 Mouser Electronics uthorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Everspin Technologies: MR408BCYS35 MR408BCYS35R MR408BYS35 MR408BYS35R MR408BCM35

RoHS MR256A08B INTRODUCTION. 32K x 8 MRAM

RoHS MR256A08B INTRODUCTION. 32K x 8 MRAM MR25608B FETURES 3.3 Volt power supply Fast 35 ns read/write cycle SRM compatible timing Native non-volatility Unlimited read & write endurance Data always non-volatile for >20 years at temperature Commercial