8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS

Transcription

1 TECHNICAL ATA IN74HC299 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS The IN74HC299 is identical in pinout to the LS/ALS299. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC299features a multiplexed parallel input/output data port to achieve full 8-bit handling in a pin package. ue to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both Mode- Select lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low asynchronous Reset overrides all other inputs. Outputs irectly Interface to CMOS, NMOS, and TTL Operating Voltage Range: to V Low Input Current: 1.0 μa High Noise Immunity Characteristic of CMOS evices ORERING INFORMATION IN74HC299N Plastic IN74HC299W SOIC TA = - to 12 C for all packages PIN ASSIGNMENT LOGIC IAGRAM PIN =VCC PIN 10 = GN 1

2 MAXIMUM RATINGS * Symbol Parameter Value Unit VCC C Supply Voltage (Referenced to GN) -0. to +7.0 V VIN C Input Voltage (Referenced to GN) -1. to VCC +1. V VOUT C Output Voltage (Referenced to GN) -0. to VCC +0. V IIN C Input Current, per Pin ± ma IOUT C Output Current, per Pin ±3 ma ICC C Supply Current, VCC and GN Pi ±7 ma P Power issipation in Still Air, Plastic IP+ SOIC Package+ Tstg Storage Temperature -6 to +10 C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic IP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +erating - Plastic IP: - 10 mw/ C from 6 to 12 C SOIC Package: : - 7 mw/ C from 6 to 12 C mw 0 C RECOMMENE OPERATING CONITIONS Symbol Parameter Min Max Unit VCC C Supply Voltage (Referenced to GN) V VIN, VOUT C Input Voltage, Output Voltage (Referenced to GN) 0 VCC V TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time (Figure 1) VCC = V VCC = V VCC = V This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be cotrained to the range GN (VIN or VOUT) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or VCC). Unused outputs must be left open. I/O pi must be connected to a properly terminated line or bus. 2

3 C ELECTRICAL CHARACTERISTICS(Voltages Referenced to GN) Symbol Parameter Test Conditio V 2 C to - C VIH Minimum High- Level Input Voltage VIL Maximum Low - Level Input Voltage VOH Minimum High- Level Output Voltage VOUT= V or VCC- V IOUT μa VOUT= V or VCC- V IOUT μa IOUT μa VCC Guaranteed Limit C C Unit V V V IOUT ma (P/Q) IOUT 7.8 ma (P/Q) IOUT 4.0 ma (Q ) IOUT.2 ma (Q ) VOL Maximum Low- Level Output Voltage VIN= VIL or VIH IOUT μa V IOUT ma (P/Q) IOUT 7.8 ma (P/Q) IIN IOZ ICC Maximum Input Leakage Current Maximum Three- State Leakage Current (QA thru QH) Maximum Quiescent Supply Current (per Package) IOUT 4.0 ma (Q ) IOUT.2 ma (Q ) VIN=VCC or GN ± ±1.0 ±1.0 μa Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GN VIN=VCC or GN IOUT=0μA ±0. ±.0 ±10 μa μa 3

4 AC ELECTRICAL CHARACTERISTICS(CL=0pF,Input tr=tf= ) Symbol Parameter V 2 C to - C fmax tplh, tphl tplh, tphl tphl tphl Maximum Clock Frequency (0% uty Cycle) (Figures 1 and ) Maximum Propagation elay, Clock to QA or QH (Figures 1 and ) Maximum Propagation elay, Clock to QA thru QH (Figures 1 and ) Maximum Propagation elay, Reset to QA or QH (Figures 2 and ) Maximum Propagation elay, Reset to QA thru QH (Figures 2 and ) tplz, tphz Maximum Propagation elay, OE1, OE2, S1, or S2 to QA thru QH (Figures 3 and 6) tpzl, tpzh Maximum Propagation elay, OE1, OE2, S1, or S2 to QA thru QH (Figures 3 and 6) ttlh, tthl ttlh, tthl Maximum Output Traition Time, QA thru QH (Figures 1 and ) Maximum Output Traition Time, QA thru QH (Figures 1 and ) VCC Guaranteed Limit 8 C 12 C Unit CIN Maximum Input Capacitance) pf Maximum Three-State I/O Capacitance pf (I/O in High-Impedance State), QA thru QH COUT MHz CP Power issipation Capacitance (Per Package), Output Enable Used to determine the no-load dynamic power coumption: P=CPVCC 2 f+iccvcc C,VCC=.0 V 240 pf 4

5 TIMING REQUIREMENTS(CL=0pF,Input tr=tf= ) VCC Guaranteed Limit Symbol Parameter V 2 C to- C 8 C 12 C Unit tsu tsu th th trec tw tw tr, tf Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) Minimum Setup Time, ata Inputs SA, SH, PA thru PH to Clock (Figure 4) Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) Minimum Hold Time, Clock to ata Inputs, SA, SH, PA thru PH (Figure 4) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Maximum Input Rise and Fall Times (Figure 1)

6 FUNCTION TABLE Inputs Respoe Mode Reset Mode Select Output Enables Clock Serial Inputs PA/ QA PB/ QB PC/ QC P/ Q PE/ QE PF/ QF PG/ QG PH/ QH QA QH S2 S1 OE1 OE2 A H Reset L X L L L X X X L L L L L L L L L L Shift Right Shift Left Parallel Load L L X L L X X X L L L L L L L L L L L H H X X X X X QA through QH=Z L L H L H H X X Shift Right: QA through QH=Z; A FA; FA FB; etc H L H X H X Shift Right: QA through QH=Z; A FA; FA FB; etc H L H L L X Shift Right: A FA =QA; FA FB =QB; etc H H L H X X Shift Left: QA through QH=Z; H FH; FH FG; etc H H L X H X Shift Left: QA through QH=Z; H FH; FH FG; etc H H L L L X Shift Left: H FH =QH; FH FG =QG; etc H H H X X X X Parallel Load:PN FN PA PH Hold H L L H X X X X Hold: QA through QH=Z; FN=FN PA PH H L L X H X X X Hold: QA through QH=Z; FN=FN PA PH H L L L L X X X Hold: QN =QH PA PH Z = high impedance = data on serial input F = flip-flop (see Logic iagram) When one or both output controls are high the eight input/output terminals are disabled to the highimpedance state; however, sequential operation or clearing of the register is not affected. QB QB QB QG QG QG 6

7 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3a. Switching Waveforms Figure 3b. Switching Waveforms Figure 4. Switching Waveforms Figure. Test Circuit Figure 6. Test Circuit 7

8 EXPANE LOGIC IAGRAM 8