High Performance Silicon Gate CMOS

Transcription

1 SEIONUTOR TEHNIAL ATA High Performance Silicon Gate OS The 54/74H574A is identical in pinout to the LS574. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs. ata meeting the setup time is clocked to the outputs with the rising edge of the lock. The Output Enable input does not affect the states of the flip flops, but when Output Enable is high, all device outputs are forced to the high impedance state. Thus, data may be stored even when the outputs are not enabled. The H574A is identical in function to the HT374A but has the flip flop inputs on the opposite side of the package from the outputs to facilitate P board layout. The H574A is the noninverting version of the H564. Output rive apability: 5 LSTTL Loads Outputs irectly Interface to OS, NOS and TTL Operating oltage Range: 2.0 to Low Input urrent:.0 µa In ompliance with the Requirements efined by JEE Standard No. 7A hip omplexity: 266 FETs or 66.5 Equivalent Gates LOGI IAGRA ATA INPUTS LOK OUTPUT ENALE NON INERTING OUTPUTS PIN = PIN 0 = GN esign riteria alue Units ÎÎ Internal Gate ount* 66.5 ea ÎÎ Internal Gate Propagation elay.5 Internal Gate Power issipation 5.0 µw Speed Power Product pj * Equivalent to a two input NAN gate. OUTPUT ENALE 0 PIN ASSIGNENT GN FUNTION TALE LOK Inputs Output OE lock L H H L L L L L,H, X No hange H X X Z X = on t are Z = High Impedance N SUFFIX PLASTI PAKAGE ASE W SUFFIX SOI PAKAGE ASE ORERING INFORATION 54HXXXAJ 74HXXXAN 74HXXXAW J SUFFIX ERAI PAKAGE ASE eramic Plastic SOI 3/97 otorola, Inc RE 7

2 54/74H574A ÎÎ AXIU RATINGS* SymbolÎ Parameter alue Unit ÎÎ Supply oltage (Referenced to GN) ÎÎ 0.5 to ÎÎ in Input oltage (Referenced to GN) ÎÎ 0.5 to ÎÎ out Output oltage (Referenced to GN) ÎÎ 0.5 to ÎÎ I in Input urrent, per Pin ÎÎ ± ma ÎÎ I out Output urrent, per Pin ÎÎ ± 35 ma ÎÎ I Supply urrent, and GN Pi ÎÎ ± 75 ma ÎÎ P Power issipation in Still Air, Plastic or eramic IP ÎÎ 750 mw ÎÎ SOI Package ÎÎ 500 TstgÎÎ Storage Temperature ÎÎ 65 to + 50 TL ÎÎ Lead Temperature, mm from ase for 0 Seconds (Plastic IP or SOI Package) 260 Î (eramic IP) * aximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating onditio. erating Plastic IP: 0 mw/ from 65 to 25 eramic IP: 0 mw/ from 00 to 25 SOI Package: 7 mw/ from 65 to 25 For high frequency or heavy load coideratio, see hapter 2 of the otorola High Speed OS ata ook (L29/). REOENE OPERATING ONITIONS Symbol Parameter in ax Unit Supply oltage (Referenced to GN) 2.0 Î in, out Input oltage, Output oltage (Referenced to GN) 0 TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time = Î (Figure ) = Î = 0 ELETRIAL HARATERISTIS (oltages Referenced to GN) Guaranteed Limit 55 to ÎÎ Symbol Parameter Test onditio Unit Î IH inimum High Level Input out = oltage Î Iout µa Î Î IL aximum Low Level Input out = oltage Î Iout µa OH Î inimum High Level Output Î in = IH 2.0 Î oltage Iout µa 4.5 ÎÎ ÎÎ Î Î Î in = IH Iout ÎÎ 2.4 ma 3.0 Î Iout ma Iout 7.8 ma Î OL aximum Low Level Output in = IL oltage Î Iout µa Î Î Î in = IL Iout 2.4 ma Iout ÎÎ ma Î Iout 7.8 ma This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GN (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or ). Unused outputs must be left open. OTOROLA 3 2 High Speed OS Logic ata L29 Rev 6

3 54/74H574A ELETRIAL HARATERISTIS (oltages Referenced to GN) Guaranteed Limit 55 to ÎÎ Symbol Î Parameter Î Test onditio Unit Iin aximum Input Leakage urrent in = or GN ± 0. ±.0 ±.0 µa Î IOZ aximum Three State Leakage Output in High Impedance State ± 0.5 ± 5.0 ± 0 µa urrent Î in = IL or ÎÎ IH out = or GN ÎÎ I Î aximum uiescent Supply Î in = or GN µa urrent (per Package) Iout = 0 µa NOTE: Information on typical parametric values can be found in hapter 2 of the otorola High Speed OS ata ook (L29/). ELETRIAL HARATERISTIS (oltages Referenced to GN) Guaranteed Limit Î 55 to Symbol Parameter Test onditio Unit Î IOZ aximum Three State Leakage Output in High Impedance State urrent Î in = IL or IH ÎÎ ± 0.5 ± 5.0 ± 0 µa out = or GN Î Î Î I aximum uiescent Supply in = or GN Î ÎÎ µa urrent (per Package) Iout = 0 µa A ELETRIAL HARATERISTIS (L = 50 pf, Input tr = tf = ) Guaranteed Limit Î 55 to Symbol Parameter Unit Î fmax aximum lock Frequency ( uty ycle) Hz (Figures and 4) Î Î tplh, aximum Propagation elay, lock to tphl Î (Figures and 4) tplz, Î aximum Propagation elay, Output Enable to tphz Î (Figures 2 and 5) tpzl, Î aximum Propagation elay, Output Enable to tpzh Î (Figures 2 and 5) ttlh, Î aximum Output Traition Time, any Output tthl (Figures and 4) ÎÎ in aximum Input apacitance pf aximum Three State Output apacitance, Output in High Impedance State pf out NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see hapter 2 of the otorola High Speed OS ata ook (L29/). 25, = 5.0 P Power issipation apacitance (Per Enabled Output)* 24 pf * Used to determine the no load dynamic power coumption: P = P 2 f + I. For load coideratio, see hapter 2 of the otorola High Speed OS ata ook (L29/). High Speed OS Logic ata L29 Rev OTOROLA

4 54/74H574A Î TIING REUIREENTS (L = 50 pf, Input tr = tf = ) Î Guaranteed Limit Î 55 to 25 Î Symbol Î Parameter Fig. olts in ax in ax in ax Unit tsu Î inimum Setup Time, ata to lock th Î inimum Hold Time, lock to ata tw Î inimum Pulse Width, lock tr, tf Î aximum Input Rise and Fall Times ÎÎ OTOROLA 3 4 High Speed OS Logic ata L29 Rev 6

5 54/74H574A SWITHING WAEFORS LOK tr 90% 0% tw 90% 0% tplh /fmax ttlh tf tphl tthl GN.3 tpzl.3 tpzh tplz tphz 0% 90% 3.0 GN HIGH IPEANE OL OH HIGH IPEANE Figure. Figure 2. ATA tsu ALI th GN 0 2 EXPANE LOGI IAGRA 9 0 LOK GN 3 8 Figure EIE UNER TEST OUTPUT TEST POINT L* * Includes all probe and jig capacitance Figure TEST POINT EIE UNER TEST OUTPUT kω L* ONNET TO WHEN TESTING tplz AN tpzl. ONNET TO GN WHEN TESTING tphz AN tpzh. LOK OUTPUT ENALE * Includes all probe and jig capacitance Figure 5. Test ircuit High Speed OS Logic ata L29 Rev OTOROLA

6 54/74H574A OUTLINE IENSIONS H 0 F A SEATING PLANE G N K J SUFFIX ERAI PAKAGE ASE ISSUE E J L NOTES:. LEAS WITHIN 0.25 (0.00) IAETER, TRUE POSITION AT SEATING PLANE, AT AXIU ATERIAL ONITION. 2. IENSION L TO ENTER OF LEAS WHEN FORE PARALLEL. 3. IENSIONS A AN INLUE ENISUS. ILLIETERS INHES I IN AX IN AX A F G 2.54 S 0.00 S H J K L 7.62 S S N T SEATING PLANE G E A F 0 N K PL 0.25 (0.00) T A N SUFFIX PLASTI PAKAGE ASE ISSUE E L J PL 0.25 (0.00) T NOTES:. IENSIONING AN TOLERANING PER ANSI Y4.5, ONTROLLING IENSION: INH. 3. IENSION L TO ENTER OF LEA WHEN FORE PARALLEL. 4. IENSION OES NOT INLUE OL FLASH. INHES ILLIETERS I IN AX IN AX A E S.27 S F G 0.00 S 2.54 S J K L S 7.62 S N A X (0.25) T A S S 8X G K 0X P 0.00 (0.25) T SEATING PLANE W SUFFIX PLASTI SOI PAKAGE ASE ISSUE E J F R X 45 NOTES:. IENSIONING AN TOLERANING PER ANSI Y4.5, ONTROLLING IENSION: ILLIETER. 3. IENSIONS A AN O NOT INLUE OL PROTRUSION. 4. AXIU OL PROTRUSION 0.50 (0.006) PER SIE. 5. IENSION OES NOT INLUE AAR PROTRUSION. ALLOWALE AAR PROTRUSION SHALL E 0.3 (0.005) TOTAL IN EXESS OF IENSION AT AXIU ATERIAL ONITION. ILLIETERS INHES I IN AX IN AX A F G.27 S S J K P R OTOROLA 3 6 High Speed OS Logic ata L29 Rev 6

7 54/74H574A otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters which may be provided in otorola data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/Affirmative Action Employer. fax is a trademark of otorola, Inc. How to reach us: USA / EUROPE / Locatio Not Listed: otorola Literature istribution; JAPAN: Nippon otorola Ltd.; Tatsumi SP JL, 6F Seibu utsuryu enter, P.O. ox 5405, enver, olorado or Tatsumi Koto Ku, Tokyo 35, Japan fax : RFAX0@ .sps.mot.com TOUHTONE ASIA/PAIFI: otorola Semiconductors H.K. Ltd.; 8 Tai Ping Industrial Park, US & anada ONLY Ting Kok Road, Tai Po, N.T., Hong Kong INTERNET: High Speed OS Logic ata L29 Rev 6 74H574A/ 3 7 OTOROLA