MC1455, MC1455B, NCV1455B. Timers

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1 M, MB, NVB Timers The M monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode, time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the freerunning frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to ma or drive MTTL circuits. Direct Replacement for NE Timers Timing from Microseconds through Hours Operates in Both Astable and Monostable Modes Adjustable Duty ycle High urrent an Source or Sink ma an Drive MTTL Temperature Stability of.% per Normally ON or Normally OFF k. F. F M t =.; R and = sec Time delay (t) is variable by changing R and (see Figure ).. k R. F MT M G MT N V. k V Load N F + Vac/ Hz P SUFFIX PLASTI PAKAGE ASE D SUFFIX PLASTI PAKAGE ASE xx A WL, L = Wafer Lot YY, Y = Year WW, W = Work Week MARKING DIAGRAMS XXXXXXXXX AWL YYWW XXXXXX ALYW = Specific Device ode = Assembly Location ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. (reate Named OrderingInfoText.) Figure. Second Solid State Time Delay Relay ircuit V R I ontrol Voltage k k k + omp A + omp B Gnd R S Flip Flop Q Inhibit/ +. F V O ontrol Voltage M I Sink I Source Gnd I th. k V S Test circuit for measuring D parameters (to set output and measure parameters): a) When V S /, V O is low. b) When V S /, V O is high. c) When V O is low, Pin sinks current. To test for, set V O c) high, apply voltage, and test for current flowing into Pin. c) When is not in use, it should be tied to. Figure. Representative Block Diagram Figure. General Test ircuit Semiconductor omponents Industries, LL, March, Rev. Publication Order Number: M/D

2 M, MB, NVB MAXIMUM RATINGS (T A = +, unless otherwise noted.) Rating Symbol Value Unit Power Supply Voltage + Vdc urrent (Pin ) I ma Power Dissipation (Package Limitation) P Suffix, Plastic Package Derate above T A = + D Suffix, Plastic Package Derate above T A = + Operating Temperature Range (Ambient) MB M NVB P D P D. T A to + to + to + Maximum Operating Die Junction Temperature T J + Storage Temperature Range T stg to + ELETRIAL HARATERISTIS (T A = +, = +. V to + V, unless otherwise noted.) haracteristics Symbol Min Typ Max Unit Operating Supply Voltage Range. V Supply urrent =. V, R L = = V, R L =, Low State (Note ) Timing Error (R =. k to k ) (Note ) Initial Accuracy =. F Drift with Temperature Drift with Supply Voltage Voltage/Supply Voltage V th / / Voltage V T = V =. V.. urrent I T. A Voltage V R... V urrent I R. ma urrent (Note ) I th.. A Leakage urrent (Pin ) I dischg na ontrol Voltage Level = V =. V Voltage Low I Sink = ma ( = V) I Sink = ma ( = V) I Sink = ma ( = V) I Sink = ma ( = V) I Sink =. ma ( =. V) I Sink =. ma ( =. V) Voltage High = V (I Source = ma) = V (I Source = ma) =. V (I Source = ma) I V L 9.. V OL V OH.. Rise Time Differential t r ns Fall Time Differential t f ns. Supply current when output is high is typically. ma less.. Tested at =. V and = V Monostable mode.. This will determine the maximum value of R A + R B for V operation. The maximum total R = M.. T low = for M, T low = for MB, NVB T high = + for M, T high = + for MB, T high = + for NVB. NV prefix is for Automotive and other applications requiring site and change control mw mw/ mw /W ma % PPM/ %/V V V V V

3 M, MB, NVB PW, PULSE WIDTH (ns min) I, SUPPLY URRENT (ma) V T (min), MINIMUM TRIGGER VOLTAGE (x = Vdc).., SUPPLY VOLTAGE (Vdc) Figure. Pulse Width Figure. Supply urrent. V OH (Vdc) V V.. I Source (ma) V OL, LOW OUTPUT VOLTAGE (Vdc).. I Sink (ma).... Figure. High Voltage Figure. Low =. Vdc V OL, LOW OUTPUT VOLTAGE (Vdc).. V OL, LOW OUTPUT VOLTAGE (Vdc) I Sink (ma) Figure. Low = Vdc.... I Sink (ma) Figure 9. Low = Vdc

4 M, MB, NVB.. td, DELAY TIME NORMALIZED t d, DELAY TIME NORMALIZED , SUPPLY VOLTAGE (Vdc) T A, AMBIENT TEMPERATURE ( ) Figure. Delay Time versus Supply Voltage Figure. Delay Time versus Temperature tpd, PROPAGATION DELAY TIME (ns).... V T (min), MINIMUM TRIGGER VOLTAGE (x = Vdc) Figure. Propagation Delay versus Voltage

5 M, MB, NVB omparator. k. k omparator. k ontrol Voltage FlipFlop. k. k. k.9 k k c b. k e. k c b k. k. k Gnd Figure. Representative ircuit Schematic GENERAL OPERATION The M is a monolithic timing circuit which uses an external resistor capacitor network as its timing element. It can be used in both the monostable (oneshot) and astable modes with frequency and duty cycle controlled by the capacitor and resistor values. While the timing is dependent upon the external passive components, the monolithic circuit provides the starting circuit, voltage comparison and other functions needed for a complete timing circuit. Internal to the integrated circuit are two comparators, one for the input signal and the other for capacitor voltage; also a flipflop and digital output are included. The comparator reference voltages are always a fixed ratio of the supply voltage thus providing output timing independent of supply voltage. Monostable Mode In the monostable mode, a capacitor and a single resistor are used for the timing network. Both the threshold terminal and the discharge transistor terminal are connected together in this mode (refer to circuit in Figure ). When the input voltage to the trigger comparator falls below /, the comparator output triggers the flipflop so that its output sets low. This turns the capacitor discharge transistor off and drives the digital output to the high state. This condition allows the capacitor to charge at an exponential rate which is set by the R time constant. When the capacitor voltage reaches /, the threshold comparator resets the flipflop. This action discharges the timing capacitor and returns the digital output to the low state. Once the flipflop has been triggered by an input signal, it cannot be retriggered until the present timing period has been completed. The time that the output is high is given by the equation t =. R A. Various combinations of R and and their associated times are shown in Figure. The trigger pulse width must be less than the timing period. A reset pin is provided to discharge the capacitor, thus interrupting the timing cycle. As long as the reset pin is low, the capacitor discharge transistor is turned on and prevents the capacitor from charging. While the reset voltage is applied the digital output will remain the same. The reset pin should be tied to the supply voltage when not in use. R L R L + (. V to V) M ontrol Voltage Figure. Monostable ircuit. F R A

6 M, MB, NVB, APAITANE ( µ F)... t = s/cm (R A = k, =. F, R L =. k, = V) Figure. Monostable Waveforms. s s. ms ms ms. t d, TIME DELAY (s) Figure. Time Delay + (. V to V) R L R A R L M ontrol Voltage R B t = s/cm (R A =. k, =. F, R L =. k ; R B =.9 k, = V) Figure. Astable ircuit Figure. Astable Waveforms Astable Mode In the astable mode the timer is connected so that it will retrigger itself and cause the capacitor voltage to oscillate between / and /. See Figure. The external capacitor changes to / through R A and R B and discharges to / through R B. By varying the ratio of these resistors the duty cycle can be varied. The charge and discharge times are independent of the supply voltage. The charge time (output high) is given by: t.9(ra RB) The discharge time (output low) is given by: t.9(rb) Thus the total period is given by: T t t.9(ra RB) The frequency of oscillation is then: f. (RA RB) and may be easily found as shown in Figure 9. The duty cycle is given by: D R B RA RB To obtain the maximum duty cycle R A must be as small as possible; but it must also be large enough to limit the discharge current (Pin current) within the maximum rating of the discharge transistor ( ma). The minimum value of R A is given by: RA (Vdc) (Vdc) I (A)., APAITANE ( µ F)... (R A + R B ).... k k f, FREE RUNNING FREQUENY (Hz) Figure 9. Free Running Frequency

7 M, MB, NVB APPLIATIONS INFORMATION Linear Voltage Ramp In the monostable mode, the resistor can be replaced by a constant current source to provide a linear ramp voltage. The capacitor still charges from to /. The linear ramp time is given by: t =, where I = V B V BE R E If V B is much larger than V BE, then t can be made independent of. Missing Pulse Detector The timer can be used to produce an output when an input pulse fails to occur within the delay of the timer. To accomplish this, set the time delay to be slightly longer than the time between successive input pulses. The timing cycle is then continuously reset by the input pulse train until a change in frequency or a missing pulse allows completion of the timing cycle, causing a change in the output level. + (. V to V) Digital R E N R V or Equiv E V B M I Sweep. F ontrol Voltage R Input R L R A M ontrol Voltage. F N or Equiv Figure. Linear Voltage Sweep ircuit Figure. Missing Pulse Detector t = s/cm t = s/cm (R E = k, R = k, R = 9 k, =. F, = V) (R A =. k, R L =. k, =. F, = V) Figure. Linear Voltage Ramp Waveforms Figure. Missing Pulse Detector Waveforms

8 Pulse Width Modulation If the timer is triggered with a continuous pulse train in the monostable mode of operation, the charge time of the capacitor can be varied by changing the control voltage at Pin. In this manner, the output pulse width can be modulated by applying a modulating signal that controls the threshold voltage. + (. V to V) M, MB, NVB lock Input R L M Figure. Pulse Width Modulator R A Modulation Input t =. ms/cm (R A = k, =. F, = V) Figure. Pulse Width Modulation Waveforms Test Sequences Several timers can be connected to drive each other for sequential timing. An example is shown in Figure where the sequence is started by triggering the first timer which runs for ms. The output then switches low momentarily and starts the second timer which runs for ms and so forth. (. V to V) 9. k k 9. k k. k. F. F. F M M M. F. F. F. F. F Load Load Figure. Sequential Timer Load DEVIE ORDERING INFORMATION Device Operating Temperature Range Package Shipping MP T A = to + Plastic Dip Units/Rail MD T A = to + SO 9 Units/Rail MBD T A = to + SO 9 Units/Rail MBP T A = to + Plastic Dip Units/Rail NVBDR* T A = to + SO /Tape & Rail *NV prefix is for automotive and other applications requiring site and control changes.

9 M, MB, NVB PAKAGE DIMENSIONS P SUFFIX PLASTI PAKAGE ASE ISSUE L B NOTES:. DIMENSION L TO ENTER OF LEAD WHEN FORMED PARALLEL.. PAKAGE ONTOUR OPTIONAL (ROUND OR SQUARE ORNERS).. DIMENSIONING AND TOLERANING PER ANSI Y.M, 9. NOTE T SEATING PLANE H F A N D K G. (.) M T A M B M L J M MILLIMETERS INHES DIM MIN MAX MIN MAX A B D.... F.... G. BS. BS H.... J.... K.9... L. BS. BS M N.... 9

10 M, MB, NVB PAKAGE DIMENSIONS X B Y A S. (.) M D SUFFIX PLASTI PAKAGE ASE (SO) ISSUE AA Y M K NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y.M, 9.. ONTROLLING DIMENSION: MILLIMETER.. DIMENSION A AND B DO NOT INLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION. (.) PER SIDE.. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION.. THRU ARE OBSOLETE. NEW STANDARD IS. Z H G D. (.) M Z Y S X S SEATING PLANE. (.) N X M J MILLIMETERS INHES DIM MIN MAX MIN MAX A B D.... G. BS. BS H.... J.9... K.... M N.... S.... ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box, Denver, olorado USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/anada Japan: ON Semiconductor, Japan ustomer Focus enter 9 Kamimeguro, Meguroku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. M/D

TIMING CIRCUIT SEMICONDUCTOR TECHNICAL DATA ORDERING INFORMATION. Figure Second Solid State Time Delay Relay Circuit

TIMING CIRCUIT SEMICONDUCTOR TECHNICAL DATA ORDERING INFORMATION. Figure Second Solid State Time Delay Relay Circuit The MC1455 monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In