MC bit Multiplying D/A Converter

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1 M bit Multiplying D/A onverter The M is an bit monolithic digital to analog converter which provides high speed performance with low cost. It is designed for use where the output current is a linear product of an bit digital word and an analog reference voltage. Features Fast Settling Time: ns (typ) Relative Accuracy ±.% (max error) Non inverting Digital Inputs are TTL and MOS ompatible High speed Multiplying Rate. ma/ s (Input Slew) Output Voltage Swing +. V to. V Standard Supply Voltages +. V and. V to V Pb Free Packages are Available* Applications Tracking A to D onverters / Digit Panel Meters and DVMs Waveform Synthesis Sample and Hold Peak Detector Programmable Gain and Attenuation RT haracter Generation Audio Digitizing and Decoding Programmable Power Supplies Analog Digital Multiplication Digital Digital Multiplication Analog Digital Division Digital Addition and Subtraction Speech ompression and Expansion Stepping Motor Drive Modems Servo Motor and Pen Drivers SOI D SUFFIX ASE B PDIP N SUFFIX ASE MARKING DIAGRAMS PIN ONNETIONS N Package M DG AWLYWW M N AWLYYWWG A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb Free Package N GND OMPEN V REF( ) V EE V REF(+) I O MSB A A LSB A A A A A A D Package* A LSB V REF(+) A V REF( ) A OMPEN A N A GND A A I O A MSB (Top View) *SO and non standard pinouts. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor omponents Industries, LL, May, Rev. Publication Order Number: M /D

2 M MSB LSB A A A A A A A A URRENT SWITHES I O V REF (+) ( ) V REF R-R LADDER BIAS URRENT REFERENE URRENT AMPLIFIER GND OMPEN NPN URRENT SOURE PAIR Figure. Block Diagram PIN FUNTION DESRIPTION Pin N Package / D Package Symbol Description / N No onnect / GND Ground / Negative Power Supply / Io Output urrent / A Output, Most Significant Bit (MSB) / A Output / A Output / A Output / A Output / A Output / A Output / A Output, Least Significant Bit (LSB) / Positive Power Supply / V REF(+) Positive Reference Voltage / V REF( ) Negative Reference Voltage / OMPEN ompensator apacitor Pin

3 M MAXIMUM RATINGS Rating Symbol Value Unit Positive Power Supply Voltage +. V Negative Power Supply Voltage. V Digital Input Voltage V V to V Applied Output Voltage V O. to + V Reference urrent I. ma Reference Amplifier Inputs V, V to Maximum Power Dissipation, T amb = (still air) (Note ) N Package D Package Thermal Resistance, Junction to Ambient N Package D Package P D R JA mw /W Operating Temperature Range T amb to + Operating Junction Temperature T J Storage Temperature Range T stg to + Lead Soldering Temperature ( sec) T sld + Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability.. Derate above, at the following rates: N package at. mw/ ; D package at. mw/. TYPIAL PERFORMANE HARATERISTIS I O OUTPUT URRENT (ma).. ()INPUT DIGITAL WORD() Figure. D to A Transfer haracteristics

4 M D ELETRIAL HARATERISTIS (Pin must be. V more negative than the potential to which R is returned. +. V D, = V D, V REF /R =. ma unless otherwise specified. T amb = to, unless otherwise noted.) haracteristic Test onditions Symbol Min Typ Max Unit Relative Accuracy Error relative to full scale I O, E r ±. % Figure Settling Time (Note ) To within / LSB, includes t PLH ; T amb = +, Figure t S ns Propagation Delay Time Low to High High to Low T amb = +, Figure t PLH t PHL Output Full scale urrent Drift TI O ppm/ Digital Input Logic Level (MSB) High Low Figure V IH. V IL. ns V D Digital Input urrent (MSB) High Low Figure V IH =. V V IL =. V I IH IIL... ma Reference Input Bias urrent Pin, Figure I.. A Output urrent Range Figure =. V =. V to V I OR.... ma Output urrent Off State Figure V REF =. V, R = All bits low I O I O(min).... ma A Output Voltage ompliance E r.%. at T A = +, Figure =. V below V V O. +., +., +.., +. V D Reference urrent Slew Rate Figure SRI REF. ma/ s Output urrent Power Supply Sensitivity I REF =. ma PSRR( ).. A/V Power Supply urrent Positive Negative All bits low, Figure I +. I EE. + ma Power Supply Voltage Range Positive Negative T amb = +, Figure R R V D Power Dissipation All bits low, Figure =. V D =. V D P D mw. All bits switched.

5 M ircuit Description The M consists of a reference current amplifier, an R R ladder, and high speed current switches. For many applications, only a reference resistor and reference voltage need be added. The switches are non inverting in operation; therefore, a high state on the input turns on the specified output current component. The switch uses current steering for high speed, and a termination amplifier consisting of an active load gain stage with unity gain feedback. The termination amplifier holds the parasitic capacitance of the ladder at a constant voltage during switching, and provides a low impedance termination of equal voltage for all legs of the ladder. The R R ladder divides the reference amplifier current into binary related components, which are fed to the remainder current which is equal to the least significant bit. This current is shunted to ground, and the maximum output current is / of the reference amplifier current, or. ma for a. ma reference amplifier current if the NPN current source pair is perfectly matched. Functional Description Reference Amplifier Drive and ompensation The reference amplifier input current must always flow into Pin. regardless of the setup method or reference supply voltage polarity. onnections for a positive reference voltage are shown in Figure. The reference voltage source supplies the full reference current. For bipolar reference signals, as in the multiplying mode, R can be tied to a negative voltage corresponding to the minimum input level. R may be eliminated and Pin grounded, with only a small sacrifice in accuracy and temperature drift. The compensation capacitor value must be increased with increasing values of R to maintain proper phase margin. For R values of.,., and. k, minimum capacitor values are,, and pf. The capacitor may be tied to either or ground, but using increases negative supply rejection. (Fluctuations in the negative supply have more effect on accuracy than do any changes in the positive supply.) A negative reference voltage may be used if R is grounded and the reference voltage is applied to R, as shown in Figure. A high input impedance is the main advantage of this method. The negative reference voltage must be at least. V above the supply. Bipolar input signals may be handled by connecting R to a positive reference voltage equal to the peak positive input level at Pin. apacitive bypass to ground is recommended when a D reference voltage is used. The. V logic supply is not recommended as a reference voltage, but if a well regulated. V supply which drives logic is to be used as the reference, R should be formed of two series resistors and the junction of the two resistors bypassed with. F to ground. For reference voltages greater than. V, a clamp diode is recommended between Pin and ground. If Pin is driven by a high impedance such as a transistor current source, none of the above compensation methods apply and the amplifier must be heavily compensated, decreasing the overall bandwidth. A A A A A A A A M R = R R R I O R L (+)V REF A A A A A A A A M R = R R R I O R L ( )V REF SEE TEXT FOR VALUES OF. SEE TEXT FOR VALUES OF. Figure. Positive V REF Figure. Negative V REF

6 M Output Voltage Range The voltage at Pin must always be at least. V more positive than the voltage of the negative supply (Pin ) when the reference current is. ma or less, and at least V more positive than the negative supply when the reference current is between. ma and. ma. This is necessary to avoid saturation of the output transistors, which would cause serious degradation of accuracy. ON Semiconductor s M does not need a range control because the design extends the compliance range down to. V (or. V see above) above the negative supply voltage without significant degradation of accuracy. ON Semiconductor s M can be used in sockets designed for other manufacturers M without circuit modification. Output urrent Range Any time the full scale current exceeds. ma, the negative supply must be at least. V more negative than the output voltage. This is due to the increased internal voltage drops between the negative supply and the outputs with higher reference currents. Accuracy Absolute accuracy is the measure of each output current level with respect to its intended value, and is dependent upon relative accuracy, full scale accuracy and full scale current drift. Relative accuracy is the measure of each output current level as a fraction of the full scale current after zero scale current has been nulled out. The relative accuracy of the M is essentially constant over the operating temperature range because of the excellent temperature tracking of the monolithic resistor ladder. The reference current may drift with temperature, causing a change in the absolute accuracy of output current; however, the M has a very low full scale current drift over the operating temperature range. The M series is guaranteed accurate to within ±/ LSB at + at a full scale output current of. ma. The relative accuracy test circuit is shown in Figure. The bit converter is calibrated to a full scale output current of. ma; then the M s full scale current is trimmed to the same value with R so that a zero value appears at the error amplifier output. The counter is activated and the error band may be displayed on the oscilloscope, detected by comparators, or stored in a peak detector. Two bit D to A converters may not be used to construct a bit accurate D to A converter. bit accuracy implies a total of ±/ part in,, or ±.%, which is much more accurate than the ±.% specification of the M. MSB A A -BIT A D-TO-A A ONVERTER A (±.% A ERROR MAX) A A AAA A k TO +V OUTPUT LSB V REF = V. F R k + NE ERROR (V = %) -BIT OUNTER MSB M LSB k Figure. Relative Accuracy

7 M Monotonicity A monotonic converter is one which always provides an analog output greater than or equal to the preceding value for a corresponding increment in the digital input code. The M is monotonic for all values of reference current above. ma. The recommended range for operation is a D reference current between. ma and. ma. Settling Time The worst case switching condition occurs when all bits are switched on, which corresponds to a low to high transition for all input bits. This time is typically ns for settling to within /LSB for bit accuracy. This time applies when R L < and O < pf. The slowest single switch is the least significant bit, which typically turns on and settles in ns. In applications where the D to A converter functions in a positive going ramp mode, the worst case condition does not occur and settling times less than ns may be realized. Extra care must be taken in board layout since this usually is the dominant factor in satisfactory test results when measuring settling time. Short leads, F supply bypassing for low frequencies, minimum scope lead length, good ground planes, and avoidance of ground loops are all mandatory. e IN. F. F M.k.k pf +V D R R L. F FOR SETTLING TIME MEASUREMENT e O (ALL BITS O pf SWITHED LOW TO HIGH).V e IN.V.V SETTLING TIME TRANSIENT RESPONSE mv t PHL = t PLH = ns t S = ns TYPIAL TO ±/LSB t PLH.V USE R L to GND FOR TURN OFF MEASUREMENT R L = R L = PIN TO GND t PHL Figure. Transient Response and Settling Time DIGITAL INPUTS A A A A A A A A (+) I I V I I M I EE TYPIAL VALUES R = R = k V REF = +.V = pf I R I R I O R L V REF(+) V O OUTPUT (SEE TEXT FOR VALUES OF ) V I AND I I APPLY TO INPUTS A THROUGH A THE RESISTOR TIED TO PIN IS TO TEMPERATURE OMPENSATE THE BIAS URRENT AND MAY NOT BE NEESSARY FOR ALL APPLIATIONS I O K A A A A A A A A where K V REF R and A N = IF A N IS AT HIGH LEVEL A N = IF A N IS AT LOW LEVEL Figure. Notation Definitions

8 M M pf k k V REF R L = SOPE di I dv dt R L dt % % SLEWING TIME.mA Figure. Reference urrent Slew Rate Measurement ORDERING INFORMATION M D M DG Device Temperature Range Package Shipping SOI SOI (Pb Free) Units/Rail M DR SOI M DRG to + SOI (Pb Free) Tape and Reel M N M NG PDIP PDIP (Pb Free) Units/Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D.

9 M PAKAGE DIMENSIONS PDIP ASE ISSUE T A B NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y.M,.. ONTROLLING DIMENSION: INH.. DIMENSION L TO ENTER OF LEADS WHEN FORMED PARALLEL.. DIMENSION B DOES NOT INLUDE MOLD FLASH.. ROUNDED ORNERS OPTIONAL. H G F D PL S K. (.) M T SEATING T PLANE A M J L M INHES MILLIMETERS DIM MIN MAX MIN MAX A.... B D.... F.... G. BS. BS H. BS. BS J.... K.... L.... M S.... SOI ASE B ISSUE J A B P PL. (.) M B S NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y.M,.. ONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS A AND B DO NOT INLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION. (.) PER SIDE.. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE. (.) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION. T SEATING PLANE G K D PL. (.) M T B S A S M R X J F MILLIMETERS INHES DIM MIN MAX MIN MAX A.... B D.... F.... G. BS. BS J.... K.... M P.... R.... ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box, Denver, olorado USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative M /D

INTEGRATED CIRCUITS MC1408-8

INTEGRATED CIRCUITS MC1408-8 INTEGRATED CIRCUITS Supersedes data of 99 Aug File under Integrated Circuits, IC Handbook 00 Aug 0 DESCRIPTION The is an -bit monolithic digital-to-analog converter which provides high-speed performance