NCP51199, NCV DDR 2-Amp Source / Sink V TT Termination Regulator

Transcription

1 DDR 2-Amp Source / Sink V TT Termination Regulator The NP/NV599 is a linear regulator designed to supply a regulated V TT termination voltage for DDR 2 and DDR 3 memory applications. The regulator is capable of actively sourcing and sinking ±2 A peak currents for DDR 2, and DDR 3 up to ±.5 A while regulating the V TT output voltage to within ± mv. The output termination voltage is regulated to track V DDQ / 2 by two external voltage divider resistors connected to the PV, GND, and V REF pins. The NP/NV599 incorporates a high speed differential amplifier to provide ultra fast response to line and load transients. Other features include source/sink current limiting, soft start and on chip thermal shutdown protection. Features Supports DDR 2 V TT Termination to ±2 A, DDR 3 to ±.5 A (peak) Stable with F eramic apacitance on V TT Output Integrated Power MOSFETs High Accuracy V TT Output at Full Load Fast Transient Response Built in Soft Start Shutdown for Standby or Suspend Mode Integrated Thermal and urrent Limit Protection NV Prefix for Automotive and Other Applications Requiring Unique Site and ontrol hange Requirements; AE Q Qualified and PPAP apable These Devices are Pb Free and are RoHS ompliant Typical Applications SDRAM Termination Voltage for DDR 2 / DDR 3 Motherboard, Notebook, and VGA ard Memory Termination Set Top Box, Digital TV, Printers 8 PV GND VREF SOI8 NB EP PD SUFFIX ASE 75BU XXXXXX = Specific Device ode A = Assembly Location L = Wafer Lot Y = Year WW = Work Week = Pb Free Package PIN ONNETION V TT 8 SOI 8 EP MARKING DIAGRAM N N V N XXXXXX ALYW ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 6 of this data sheet. 8 Semiconductor omponents Industries, LL, 24 March, 24 Rev. 2 Publication Order Number: NP599/D

2 NP599 PV =.5 to 5. V* 2 PV V V R2 k 2 GND Enable R k 3 V REF V TT 4 4 V TT =.75 to 2.5 V* R3 *For DDR2: PV =.8 V, V TT =.9 V DDR3: PV =.5 V, V TT =.75 V = F (Low ESR) 2 = 47 F (Low ESR) 3 = 47 F 4 = F + F ( F ceramic) R3 = Optional V TT discharge resistor N ch MOSFET = Optional Enable / Disable Figure. Application Diagram PIN FUNTION DESRIPTION Pin No. Pin Name Description PV Input voltage which supplies current to the output pin. IN = 47 F with low ESR. 2 GND ommon Ground 3 V REF Buffered reference voltage input equal to ½ of V DDQ and active low shutdown pin. An external resistor divider dividing down the PV voltage creates the regulated output voltage. Pulling the pin to ground (.5 V maximum) turns the device off. 4 V TT Regulator output voltage capable of sourcing and sinking current while regulating the output rail. OUT = F + F ceramic with low ESR. 5 N True No onnect 6 V The V pin is a 5 V input pin that provides internal bias to the controller. PV should always be kept lower or equal to V. 7 N True No onnect 8 N True No onnect EP Thermal Pad Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance. 2

3 ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Supply Voltage Range (V cc PV ) (Note ) PV, V.3 to 6 V Output Voltage Range V TT.3 to 6 V Reference Input Range V REF.3 to 6 V Maximum Junction Temperature T J(max) Storage Temperature Range TSTG 65 to 5 ESD apability, Human Body Model (Note 2) ESDHBM 2 kv ESD apability, Machine Model (Note 2) ESDMM 5 V Lead Temperature Soldering Reflow (SMD Styles Only), Pb Free Versions (Note 3) T SLD 26 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability.. Refer to ELETRIAL HARATERISTIS and APPLIATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AE Q 2 (EIA/JESD22 A4) ESD Machine Model tested per AE Q 3 (EIA/JESD22 A5) Latchup urrent Maximum Rating: 5 ma per JEDE standard: JESD78 3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D THERMAL HARATERISTIS Rating Symbol Value Unit Thermal haracteristics, SO8 EP (Note 4) Thermal Resistance, Junction to Air (Note 5) Power Rating at Ambient =.9 W, derate 2 mw/ Thermal Reference, Junction to Lead2 (Note 5) 4. Refer to ELETRIAL HARATERISTIS and APPLIATION INFORMATION for Safe Operating Area. 5. Values based on copper area of 645 mm 2 (or in 2 ) of oz copper thickness and FR4 PB substrate. R JA R JL 84 2 /W OPERATING RANGES (Note 6) Rating Symbol Min Max Unit Input Voltage PV V Bias Supply Voltage V V Ambient Temperature T A 4 85 Junction Temperature T J 4 6. Refer to ELETRIAL HARATERISTIS and APPLIATION INFORMATION for Safe Operating Area. 3

4 ELETRIAL HARATERISTIS PV =.8 V /.5 V; V = 5 V; V REF =.9 V /.75 V; OUT = F (eramic); T A = +, unless otherwise noted. Parameter Test onditions Symbol Min Typ Max Unit REGULATOR OUTPUT Output Offset Voltage I out = A V OS 2 +2 mv Load Regulation V REF = 9 mv, I out = ±.8 A, PV =.8 V V REF = 75 mv, I out = ±.4 A, PV =.5 V Reg load + mv INPUT AND STANDBY URRENTS Bias Supply urrent I out = A I BIAS ma Standby urrent V REF <.2 V (Shutdown), R LOAD = 8 I STB 9 A URRENT LIMIT PROTETION PV =.8 V, V REF =.9 V urrent Limit PV =.5 V, V REF =.75 V I LIM A SHUTDOWN THRESHOLDS Enable V IH.6 Shutdown Threshold Voltage Shutdown V IL.5 V THERMAL SHUTDOWN Thermal Shutdown Temperature V = 5 V T SD Thermal Shutdown Hysteresis V = 5 V T SH

5 TYPIAL HARATERISTIS.95.9 PV =.8 V, V = 5 V PV =.5 V, V = 5 V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 2. Output Voltage vs. Temperature Figure 3. Output Voltage vs. Temperature.6.2 SHUTDOWN THRESHOLD (V) V = 5 V Enabled Shutdown V URRENT (ma) PV =.8 V, V = 5 V Figure 4. Shutdown Threshold vs. Temperature Figure 5. V urrent vs. Temperature PV URRENT (ma) PV =.8 V, V = 5 V SOURE URRENT LIMIT (A) PV =.8 V, V = 5 V PV =.5 V, V = 5 V Figure 6. PV urrent vs. Temperature Figure 7. Source urrent Limits vs. Temperature 5

6 TYPIAL HARATERISTIS SINK URRENT LIMIT (A) PV =.8 V, V = 5 V PV =.5 V, V = 5 V 5 75 V TT, TRANSIENT RESPONSE (mv) TIME ( sec / div) Figure 8. Sink urrent Limits vs. Temperature Figure 9.. V,.6 A Transient Response Table. ORDERING INFORMATION Device Marking Package Shipping NP599PDR2G 599 NV599PDR2G* V599 SOI 8 (Pb-Free) / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *NV Prefix for Automotive and Other Applications Requiring Unique Site and ontrol hange Requirements; AE Q Qualified and PPAP apable. 6

7 PAKAGE DIMENSIONS 2X 4 TIPS.2. D NOTE 5 B A E 8 e TOP VIEW NOTE 4 D SIDE VIEW BOTTOM VIEW A NOTE E NOTE 4 8X b. M 8X NOTE 7 F 2X. D. 2X. A-B G SEATING PLANE A-B L2 D B SOI8 NB EP ASE 75BU ISSUE B F L DETAIL A B DETAIL A c c END VIEW NOTE 6 A SEATING PLANE REOMMENDED SOLDERING FOOTPRINT b h b ÇÇÇ ÉÉÉ SETION B B 3.3 NOTES:. DIMENSIONING AND TOLERANING PER ASME Y4.5M, ONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE.mm IN EXESS OF MAXIMUM MATERIAL ONDITION. 4. DIMENSION D DOES NOT INLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXEED.5mm PER SIDE. DIMENSION E DOES NOT INLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXEED.mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F. 6. A IS DEFINED AS THE VERTIAL DISTANE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PAKAGE BODY. 7. TAB ONTOUR MAY VARY MINIMALLY TO INLUDE TOOLING FEATURES. MILLIMETERS DIM MIN MAX A A. b.3.5 b c.7. c.7.23 D 4.9 BS E 6. BS E 3.9 BS e.27 BS F G h..5 L.4.27 L2. BS 8X PITH 8X.6 DIMENSION: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SILL s product/patent coverage may be accessed at Marking.pdf. SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any license under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 827 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada orderlit@onsemi.com N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NP599/D