NCP A DDR Memory Termination Regulator

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NCP9.A DDR Memory Termination Regulator The NCP9 is a simple, costeffective, highspeed linear regulator designed to generate the termination voltage rail for DDRI, DDRII and DDRIII memory.

The output termination voltage is tightly regulated to track = ( DDQ / ) over the entire current range.

1 NCP9.A DDR Memory Termination Regulator The NCP9 is a simple, costeffective, highspeed linear regulator designed to generate the termination voltage rail for DDRI, DDRII and DDRIII memory. The regulator is capable of actively sourcing or sinking up to ±. A for DDRI, or up to ±. A for DDRII /III while regulating the output voltage to within ± m. The output termination voltage is tightly regulated to track = ( DDQ / ) over the entire current range. The NCP9 incorporates a highspeed differential amplifier to provide ultrafast response to line and load transients. Other features include extremely low initial offset voltage, excellent load regulation, source/sink softstart and onchip thermal shutdown protection. The NCP9 features the powersaving Suspend To Ram (STR) function which will tristate the regulator output and lower the quiescent current drawn when the /SS pin is pulled low. The NCP9 is available in a DFN8 package. Features Generate DDR Memory Termination oltage ( ) For DDRI, DDRII, DDRIII Source / Sink Currents Supports DDRI to ±. A, DDRII, DDRIII to ±. A (peak) Integrated Power MOSFETs with Thermal Protection Stable with F Ceramic Capacitor High Accuracy Output oltage at FullLoad Minimal External Component Count Shutdown for Standby or Suspend to RAM (STR) mode Builtin Soft Start These are PbFree Devices Appications Desktop PC s, Notebooks, and Workstations Graphics Card DDR Memory Termination Set Top Boxes, Digital T s, Printers Embedded Systems Active Bus Termination DFN8 MN SUFFIX CASE AA ORDERING INFORMATION MARKING DIAGRAM Device Package Shipping NCP9MNTAG PIN CONNECTION DFN8 (PbFree) AM A = Specific Device Code M = Date Code = PbFree Device (Note: Microdot may be in either location) / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. Semiconductor Components Industries, LLC, May, Rev. Publication Order Number: NCP9/D

2 NCP9. A, DDRI /II /III TERMINATION REGULATOR Figure. Typical Application Schematic PIN FUNCTION DESCRIPTION NCP9 Pin Number Pin Name Pin Function P CC The P CC pin provides the rail voltage from where the pin draws load current. There is a limitation between CC and P CC. The P CC voltage must be less or equal to the CC voltage to ensure the correct output voltage regulation. The source current capability is dependent on P CC voltage. The higher the voltage on P CC, the higher the source current. Regulator output voltage capable of sinking and sourcing current while regulating the output rail. GND Common Ground. /SS Suspend Shutdown supports Suspend To RAM function. CMOS compatible input sets output to high impedance state. Logic HI = Enable, Logic LO = Shutdown. S S is the sense input. REF REF is an output pin that provides the buffered output of the internal reference voltage equal to half of DDQ. Two resistors dividing down the DDQ voltage on the pin to create the regulated output voltage. 7 DDQ The DDQ pin is an input pin for creating the internal reference voltage to regulate. The DDQ voltage is connected to an internal resistor divider. The central tap of resistor divider ( DDQ /) is connected to the internal voltage buffer, which output is connected to REF pin and the noninverting input of the error amplifier as the reference voltage. 8 CC Power for the analog control circuitry. THERMAL PAD Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance.

3 NCP9 ABSOLUTE MAXIMUM RATINGS Rating Symbol alue Unit CC, P CC, DDQ, /SS to GND (Note ). to + Storage Temperature T stg to + C Operating Junction Temperature Range T J to + C Thermal Characteristics, SO8EP Thermal Resistance, JunctiontoAir Power Rating at C ambient R JA TBD C/W ESD Capability, Human Body Model (Note ) ESD HBM ESD Capability, Machine Model (Note ) ESD MM Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. No pin to exceed CC. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.. This device series incorporates ESD protection and is tested by the following method: ESD Human Body Model tested per AECQ (EIA/JESDA) ESD Machine Model tested per AECQ (EIA/JESDA) Latchup Current Maximum Rating tested per JEDEC standard: JESD78. RECOMMENED OPERATING CONDITIONS Rating Symbol alue Unit Input oltage CC. to. Bias Supply oltage P CC. to. Reference Input oltage DDQ. to.7 ELECTRICAL CHARACTERISTICS C T J C; CC = P CC = DDQ =. ; unless otherwise noted. Typical values are at T J = + C Parameter Condition Symbol Min Typ Max Unit Reference oltage (DDR I) I REF = ma (unloaded) P CC = DDQ =. =. =.7 REF (DDRI) Reference oltage (DDR II) I REF = ma (unloaded) P CC = DDQ =.7 =.8 =.9 REF (DDRII) Reference oltage (DDR III) I REF = ma (unloaded) P CC = DDQ =. =. =. REF (DDRIII) REF Output Impedance I REF = A to + A Z REF. k Output oltage (DDRI) I OUT = A P CC = DDQ =. P CC = DDQ =. P CC = DDQ =.7 (DDRI) I OUT = +. A P CC = DDQ =. P CC = DDQ =. P CC = DDQ =.7 (DDRI) I OUT =. A P CC = DDQ =. P CC = DDQ =. P CC = DDQ =.7 (DDRI)

4 NCP9 ELECTRICAL CHARACTERISTICS C T J C; CC = P CC = DDQ =. ; unless otherwise noted. Typical values are at T J = + C Parameter Condition Symbol Min Typ Max Unit Output oltage (DDRII) I OUT = A P CC = DDQ =.7 P CC = DDQ =.8 P CC = DDQ =.9 (DDRII) I OUT = +. A P CC = DDQ =.7 P CC = DDQ =.8 P CC = DDQ =.9 (DDRII) I OUT =. A P CC = DDQ =.7 P CC = DDQ =.8 P CC = DDQ =.9 (DDRII) Output oltage (DDRIII) I OUT = A P CC = DDQ =. P CC = DDQ =. P CC = DDQ =. (DDRIII) I OUT = +. A, P CC = DDQ =. I OUT =. A, P CC = DDQ =. I OUT = +. A, P CC = DDQ =. I OUT =. A, P CC = DDQ =. (DDRIII) (DDRIII) I OUT = +. A, P CC = DDQ =. I OUT =. A, P CC = DDQ =. (DDRIII) Output Offset oltage I OUT = ±. A, P CC = DDQ =. OS (DDRI) + I OUT = ±.A, P CC = DDQ =.8 OS (DDRII) + m I OUT = ±.A, P CC = DDQ =. OS (DDRIII) + Quiescent Current I OUT = A I Q 8 A DDQ Input Impedance Z DDQ k /SS Leakage Current /SS = I L_SS A Quiescent Current in Suspend Shutdown /SS = I Q_SS A Suspend Shutdown Threshold IH.9 IL.8 leakage Current in Suspend Shutdown /SS =, =. I L_TT A S Current I TTS na Thermal Shutdown Temperature T SD C Thermal Shutdown Hysteresis T SH C

5 NCP9 TYPICAL PERFORMANCE CHARACTERISTICS 7 Iq SD ( A) 8 Iq ( A) CC () CC () Figure. Iq SD vs. CC Figure. Iq vs. CC SS (). REF () CC () DDQ () Figure. IH and IL Figure. REF vs. DDQ. ()..... Iq SD ( A) 8 C C 8 C C DDQ () CC () Figure. vs. DDQ Figure 7. Iq SD vs. CC over Temperature

6 NCP9 TYPICAL PERFORMANCE CHARACTERISTICS 8 7 Iq ( A) C C 8 C C CC () Figure 8. Iq vs. CC over Temperature

7 NCP9 General The NCP9 is a bus termination, linear regulator designed to meet the JEDEC requirements for DDRI, DDRII and DDRIII memory termination. The NCP9 is capable of sourcing and sinking current while accurately tracking and regulating the output voltage equal to ( DDQ / ). The output stage has been designed to maintain excellent load regulation and preventing shootthrough. The NCP9 uses two distinct power rails to separate the analog circuitry from the power output stage and decrease internal power dissipation. Supply oltage Inputs For added flexibility, separate input pins ( CC and P CC ) are provided for each required supply input. CC is used to supply all the internal control circuitry and P CC is used exclusively to provide the rail voltage for the output stage used to create. These pins have the capability to work off separate supplies with the condition that CC is always greater than or equal to P CC, and should always be used with either a.8 or. rail. If the junction temperature exceeds the thermal shutdown threshold, the part will enter a shutdown state identical to the manual shutdown where is tristated and REF remains active. Lower voltage rails, such as. can be used but will reduce the maximum available output current. Generation of Internal oltage Reference DDQ is the input used to create the internal reference voltage for regulating. The reference voltage is generated from a resistor divider of two internal k resistors. This guarantees that will precisely track ( DDQ / ). The optimal implementation of the DDQ input pin is as a remote sense. This can be achieved by connecting DDQ directly to the.8 rail at the DIMM memory module instead of connecting it to P CC. This ensures that the reference voltage precisely tracks the DDR memory power rail without introducing a large voltage drop due to power traces. For DDRII applications the DDQ input will be.8, which will create a ( DDQ / ) =.9 termination voltage at the output. REF provides a buffered output of the internal reference voltage ( DDQ / ). For improved performance, an output bypass capacitor can be placed, close to the pin, to help reduce any potential stray noise. A ceramic capacitor in the range of. F to. F is recommended. The REF output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality. Remote oltage Feedback Sensing The purpose of the S sense pin is to provide improved remote load regulation. In most motherboard applications, the termination resistors will connect to in a long plane. If the output voltage was regulated only at the output of the NCP9, then any long traces will generate a significant IR drop resulting in a sagging termination voltage at one end of the bus than the other. The S pin can be used to improve performance by connecting it to the middle of the bus. This will provide better power distribution across the entire termination bus. If remote load regulation is not used, then the S pin must still be connected to. Care should be taken when a long S trace is implemented in close proximity to the memory. Noise pickup in the S trace can cause problems with precise regulation of. A small. F ceramic capacitor placed next to the S pin can help filter out any high frequency noise and thereby keeping the power rail in spec. Regulator Shutdown Function The NCP9 contains an active low enable pin (/SS) that can be used for suspend to RAM functionality. In this condition the output will tristate, with the REF output remaining active in order to provide a constant reference signal for the memory and chipset. During shutdown, should not be exposed to voltages that exceed P CC. With the enable pin asserted low the quiescent current of the NCP9 will drop, however the DDQ input pin will always draw a constant current due to the integrated k impedance used for generating the internal reference. Therefore, to calculate the total power loss in shutdown, both currents need to be considered. The enable pin also has an internal pullup current. Therefore, to turn the part on, the enable pin can either be connected to CC or left open. Termination oltage Output Regulation is the regulated output that is used to terminate the bus resistors. It is capable of sourcing and sinking current while regulating the output precisely to DDQ /. The NCP9 is designed to handle continuous currents of up to ±. A with excellent load regulation. If a transient is expected to last above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor should be sized large enough to prevent an excessive voltage drop. Thermal Shutdown with Hysteresis If the NCP9 is to operate in elevated temperatures for long durations, care should be taken to ensure that the maximum operating junction temperature is not exceeded. To guarantee safe operation, the NCP9 provides onchip thermal shutdown protection. When the chip junction temperature exceeds C (typical) the part will shutdown. When the junction temperature falls back to C (typical) the device resumes normal operation. If the junction temperature exceeds the thermal shutdown threshold, will tristate until the part returns below the temperature hysteresis trippoint. 7

8 NCP9 PACKAGE DIMENSIONS DFN8 x,.p CASE AA ISSUE E X PIN ONE REFERENCE X.. C. C C D ÇÇ TOP IEW A B.8 C (A) NOTE A SEATING SIDE IEW C PLANE DETAIL A DETAIL B D E 8X L A L EXPOSED Cu L DETAIL A OPTIONAL CONSTRUCTIONS ÉÉ MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION L PACKAGE OUTLINE NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, 99.. CONTROLLING DIMENSION: MILLIMETERS.. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN. AND. MM FROM TERMINAL TIP.. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A.8. A.. A. REF b.. D. BSC D.. E. BSC E.7.9 e. BSC K. REF L.. L. RECOMMENDED SOLDERING FOOTPRINT*. 8X. E.9. K e/ e 8 BOTTOM IEW 8X b. C. C A B NOTE 8X.. PITCH DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 87 USA Phone: 77 or 88 Toll Free USA/Canada Fax: 77 or 887 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 8898 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCP9/D

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