NUS2045MN, NUS3045MN. Overvoltage Protection IC with Integrated MOSFET

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, Overvoltage Protection IC with Integrated MOSFET These devices represent a new level of safety and integration by combining the NCP34 overvoltage protection circuit (OVP) with a 2 V P channel power

1 , Overvoltage Protection IC with Integrated MOSFET These devices represent a new level of safety and integration by combining the NCP34 overvoltage protection circuit (OVP) with a 2 V P channel power MOSFET () or with a 3 V P channel power MOSFET (). They are specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. During such hazardous events, the IC quickly disconnects the input supply from the load, thus protecting the load before any damage can occur. The OVP ICs are optimized for applications using an external AC DC adapter or a car accessory charger to power a portable product or recharge its internal batteries. They have a nominal overvoltage threshold of 6. V which makes them ideal for single cell Li Ion as well as 3/4 cell NiCD/NiMH applications. Features OvervoltageTurn Off Time of Less Than. s Accurate Voltage Threshold of 6. V, Nominal Undervoltage Lockout Protection; 2. V, Nominal Control Input Compatible with. V Logic Levels 2 V or 3 V Integrated P Channel Power MOSFET Low R DS(on) = 7 4. V for Low R DS(on) = V for Low Profile 3.3 x 3.3 mm DFN Package Suitable for Portable Applications Maximum Solder Reflow 23 C for MNT suffix and 26 C for MNTG suffix Pb Free Packages are Available Benefits Provide Battery Protection Integrated Solution Offers Cost and Space Savings Integrated Solution Improves System Reliability Applications Portable Computers and PDAs Cell Phones and Handheld Products Digital Cameras DFN CASE 6AL V CC OUT GATE SRC x4 = Device Code x = 2 or 3 A = Assembly Location Y = Year WW = Work Week = Pb Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT 7 6 (Bottom View) MARKING DIAGRAM x4 AYWW ORDERING INFORMATION Device Package Shipping T DFN 3 Tape & Reel TG IN GND CNTRL DRAIN T DFN 3 Tape & Reel TG GND DRAIN 9 DFN (Pb Free) DFN (Pb Free) 3 Tape & Reel 3 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. Semiconductor Components Industries, LLC, 26 June, 26 Rev. 4 Publication Order Number: /D

2 , AC/DC Adapter of Accessory Charger V CC Schottky Diode P CH IN + Undervoltage Lock Out Logic FET Driver GATE OUT + C LOAD V ref NUSx4 GND CNTRL Microprocessor Port Figure. Simplified Schematic PIN FUNCTION DESCRIPTIONS Pin # Symbol Pin Description IN This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold (V TH ), the OUT pin will be driven to within. V of V CC, thus disconnecting the FET. The nominal threshold level is 6. V and this threshold level can be increased with the addition of an external resistor between IN and V CC. 2, GND Circuit Ground 3 CNTRL This logic signal is used to control the state of OUT and turn on/off the P channel MOSFET. A logic High results in the OUT signal being driven to within. V of V CC which disconnects the FET. If this pin is not used, the input should be connected to ground. 4, 9 DRAIN Drain pin of the power MOSFET SRC Source pin of the power MOSFET 6 GATE Gate pin of the power MOSFET 7 OUT This signal drives the gate of a P channel MOSFET. It is controlled by the voltage level on IN or the logic state of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within. V of V CC in less than. _sec provided that gate and stray capacitance is less than 2 nf. V CC Positive Voltage supply. If V CC falls below 2. V (nom), the OUT pin will be driven to within. V of V CC, thus disconnecting the P channel FET. OVERVOLTAGE PROTECTION CIRCUIT TRUTH TABLE IN CNTRL OUT <V th L GND <V th H V CC >V th L V CC >V th H V CC 2

3 , MAXIMUM RATINGS (T A = 2 C unless otherwise stated) Rating Pin Symbol Min Max Unit OUT Voltage to GND 7 V O.3 3 V Input and CNTRL Pin Voltage to GND 3 V input.3 V CNTRL.3 VCC Maximum Range V CC(max).3 3 V Maximum Power Dissipation (Note ) P D. W Thermal Resistance Junction to Air (Note ) OVP IC P Channel FET 3 3 R θja Junction Temperature T J C Operating Ambient Temperature T A 4 C V CNTRL Operating Voltage 3. V Storage Temperature Range T stg 6 C ESD Performance (HBM) (Note 2),2,3,7,, 2. kv V C/W Drain to Source Voltage V DSS 2 3 V Gate to Source Voltage Continuous Drain Current, Steady State, T A = 2 C (Note ) V GS 2 2 I D.. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Surface mounted on FR4 board using inch sq pad size (Cu area =.27 in sq [ oz] including traces). 2. Human body model (HBM): MIL STD 3C Method 3 7, (R =, C = pf, F = 3 pulses delay s). V A 3

4 , ELECTRICAL CHARACTERISTICS (T A = 2 C, Vcc = 6. V, unless otherwise specified) Characteristic Symbol Pin Min Typ Max Unit V CC Operating Voltage Range V CC(opt) V Supply Current (I CC + IInput; V CC = 6. V Steady State),.7. ma Input Threshold (V Input connected to V CC ; V Input increasing) V Th V Input Hysteresis (V Input connected to V CC ; V Input decreasing) V Hyst 2 mv Input Impedance (Input = V Th ) R in 7 k CNTRL Voltage High V ih 3. V CNTRL Voltage Low V il 3. V CNTRL Current High (V ih =. V) I ih A CNTRL Current Low (V il =. V) I il 3 2 A Undervoltage Lockout (V CC decreasing) V Lock V Output Sink Current (V CC < V Th, V OUT =. V) I Sink 7 33 A Output Voltage High (V CC = V in =. V; I Source = ma) Output Voltage High (V CC = V in =. V; I Source =.2 ma) Output Voltage High (V CC = V in =. V; I Source = ma) V oh 7 V CC. V CC.2 V CC. V Output Voltage Low (Input < 6. V; I Sink = ma; V CC = 6. V, CNTRL = V) Turn ON Delay Input (Note 3) (V Input connected to V CC ; V Input step down signal from. to 6. V; measured to % point of OUT)* Turn OFF Delay Input (V Input connected to V CC ; V Input step up signal from 6. to. V; C L = 2 nf Output > V CC. V) Turn ON Delay CNTRL (CNTRL step down signal from 2. to. V; measured to % point of OUT) (Note 3) Turn OFF Delay CNTRL (CNTRL step up signal from. to 2. V; C L = 2 nf Output > V CC. V) V ol 7. V T ON IN 7 s T OFF IN 7.. s T ON CT 7 s T OFF CT s 3. Guaranteed by design. 4

5 , P CHANNEL MOSFET Parameter Symbol Min Typ Max Units Drain to Source On Resistance V GS = 4. V, I D = 6 ma V GS = 4. V, I D =. A V GS = 4. V, I D = 6 ma V GS = 4. V, I D =. A R DS(on) m Zero Gate Voltage Drain Current V GS = V, V DS = 6 V V GS = V, V DS = 24 V I DSS.. A Turn On Delay (Note 4) V GS = 4. V V GS = 4. V t on 7. ns Turn Off Delay (Note 4) V GS = 4. V V GS = 4. V t off ns Input Capacitance (Note 3) V GS = V, f =. MHz, V DS = V V GS = V, f =. MHz, V DS = V C in 67 7 pf Gate to Source Leakage Current V GS = ±. V, V DS = V V GS = ±2 V, V DS = V I GSS ± ± na Drain to Source Breakdown Voltage V GS = V, I D = 2 A V (BR)DSS 2 3 V Gate Threshold Voltage V GS = V DS, I D = 2 A V (GS)th V 4. Switching characteristics are independent of operating junction temperature.

6 , TYPICAL PERFORMANCE CURVES (T A = 2 C, unless otherwise specified) OVERVOLTAGE PROTECTION IC Voltage (V) Ambient Temperature ( C) Figure 2. Typical V th Threshold Variation vs. Temperature I supply (ma) Temperature ( C) Figure 3. Typical Supply Current vs. Temperature I cc I in, V CC 6 V 6

7 , TYPICAL PERFORMANCE CURVES (T A = 2 C, unless otherwise specified) 3 V, P CHANNEL MOSFET I D, DRAIN CURRENT (AMPS) 2 V V 4.2 V 4 V V 6 V 3. V. V V 3.6 V 3.4 V 3.2 V 3 V T J = 2 C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) R DS(on), DRAIN TO SOURCE RESISTANCE ( ) V GS, GATE VOLTAGE (VOLTS) T J = 2 C I D = 3.7 A I DSS, LEAKAGE CURRENT (na) Figure 4. On Region Characteristics V GS = V T J = C T J = C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 6. Drain to Source Leakage Current vs. Voltage I S, SOURCE CURRENT (AMPS)..3 Figure. On Resistance vs. Gate to Source Voltage V GS = V.4 T J = C T J = 2 C T J = C T J = C V SD, SOURCE TO DRAIN VOLTAGE (VOLTS) Figure 7. Diode Forward Voltage vs. Current 7

8 , TYPICAL PERFORMANCE CURVES (T A = 2 C, unless otherwise specified) 2 V, P CHANNEL MOSFET I D, DRAIN CURRENT (AMPS) R DS(on), DRAIN TO SOURCE RESISTANCE ( ). V T J = 2 C GS = V 2.4 V V T = 2 C.9 GS =. V 2.2 V..7 T = 2 C 2. V.6 T = C.. V V V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) I D, DRAIN CURRENT (AMPS) I DSS, LEAKAGE (na) Figure. On Region Characteristics V GS = V T J = C T J = 2 C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure. Drain to Source Leakage Current vs. Voltage I S, SOURCE CURRENT (AMPS) Figure 9. On Resistance vs. Drain Current and Temperature V GS = V T J = 2 C V SD, SOURCE TO DRAIN VOLTAGE (VOLTS) Figure. Diode Forward Voltage vs. Current.

9 , TYPICAL APPLICATION CIRCUITS & OPERATION WAVEFORMS (T A = 2 C, unless otherwise specified) 2 V, P CHANNEL MOSFET V CC P CH IN + Undervoltage Lock Out Logic FET Driver GATE OUT 2 6 Vdc Vdc V ref NUSx4 GND CNTRL Figure 2. Test Circuit for T ON IN and T OFF IN Input Voltage T ON IN Output Voltage T ON IN Test T A =2 C Figure 3. T ON IN Waveforms 9

10 , T OFF IN Input Voltage T OFF IN Test T A =2 C Output Voltage Figure 4. T OFF IN Waveforms V CC P CH IN + Undervoltage Lock Out Logic FET Driver GATE OUT 2 6 Vdc Vdc V ref NUSx4 GND CNTRL Figure. Test Circuit for T ON CT and T OFF CT

11 , CNTR signal T ON CT Input Voltage Output Voltage T ON CT Test T A =2 C Figure 6. T ON CT Waveforms T OFF CT CNTR signal Input Voltage T OFF CT Test T A =2 C Output Voltage Figure 7. T OFF CT Waveforms

12 , PACKAGE DIMENSIONS DFN CASE 6AL ISSUE A 2 X PIN ONE REFERENCE. C X 2 X X K D ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ. C. C. C X L D2 TOP VIEW SIDE VIEW 4 BOTTOM VIEW A D2 e A B E (A3) 2 X E2 X b A C. C A B. SEATING PLANE C NOTE X.2 NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN.2 AND.3mm. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN NOM MAX A..9. A..3. A3.2 REF b D 3.3 BSC D2.9.. E 3.3 BSC E e. BSC K.2 L.3.4. SOLDERING FOOTPRINT* DIMENSIONS: MILLIMETERS X.6 X.. PITCH *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 27 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 22 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative /D

NUS3046MNT1G. Overvoltage Protection IC with Integrated MOSFET

NUS3046MNT1G. Overvoltage Protection IC with Integrated MOSFET Overvoltage Protection IC with Integrated MOSFET This device represents a new level of safety and integration by combining the NCP346 overvoltage protection circuit (OVP) with a 30 V P channel power MOSFET.