NUS6160MNTWG. Low Profile Overvoltage Protection IC with Integrated MOSFET

Size: px

Start display at page:

Download "NUS6160MNTWG. Low Profile Overvoltage Protection IC with Integrated MOSFET"

Sheena Sanders
5 years ago
Views:

1 Low Profile Overvoltage Protection IC with Integrated MOSFET This device represents a new level of safety and integration by combining an overvoltage protection circuit (OVP) with a dual 2 V P channel power MOSFET. The OVP is specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. During such events, the IC quickly disconnects the input supply from the load, thus protecting it. The integration of the additional transistor and power MOSFET reduces layout space and promotes better charging performance. The IC is optimized for applications that use an external AC DC adapter or a car accessory charger to power a portable product or recharge its internal batteries. Features Overvoltage Turn Off Time of Less Than. s Undervoltage Lockout Protection; 3. V, Nominal High Accuracy Undervoltage Threshold of.% 2 V Integrated P Channel Power MOSFET Low R DS(on) = 6 V Compact 3. x. mm QFN Package Maximum Solder Reflow 26 C This is a Pb Free Device Benefits Provide Battery Protection Integrated Solution Offers Cost and Space Savings Integrated Solution Improves System Reliability Optimized for Commercial PMUs from Top Suppliers NUS66 = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping TWG MARKING DIAGRAM NUS 66 QFN22 ALYW CASE 8AT QFN22 (Pb Free) 3 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8/D. Applications Portable Computers and PDAs Cell Phones and Handheld Products Digital Cameras Semiconductor Components Industries, LLC, 28 December, 28 Rev. Publication Order Number: /D

2 In GND En 22 8 Out 7 Gate Flag Drain Gate2 Drain FET SW Drain FET REG Drain2 Drain2 Drain Drain Source Drain2 Source2 (Top View) Figure. Pinout Drain2 V bat 8 Wall Adaptor 2 IN FLAG OUT FET SW 3,, 6, 7 Charge SW NUS66 EN GND FET REG Charge REG 8 9 9,, 3 Battery Figure 2. Typical Charging Solution 2

3 MAXIMUM RATINGS (T J = 2 C, unless otherwise stated) Rating Symbol Min Max Unit V IN to Ground V IN.3 2 V OUT, EN, FLAG Pins Voltage to Ground V OUT, V EN, V FLAG.3 7. V Maximum Current from V IN to V OUT (PMOS) I max 6 ma Drain to Source Voltage V DSS 2 V Gate to Source Voltage V GS V Continuous Drain Current, Steady State I D 2. A Pulsed Drain Current, t p = ms I DM. A Source Current I S. A Operating Ambient Temperature T A 8 C Storage Temperature T STG C Operating Junction Temperature T J C Thermal Resistance (Note ) in 2 (6 mm 2 ) (All devices fully enhanced) OVP FET FET SW FET REG in 2 (6 mm 2 ) (OVP and FET SW fully enhanced, V drop across FET REG ) OVP FET FET SW FET REG.2 in 2 (6 mm 2) (All devices fully enhanced) OVP FET FET SW FET REG.2 in 2 (6 mm 2 ) (OVP and FET SW fully enhanced, V drop across FET REG ) OVP FET FET SW FET REG JA C/W ESD Performance (Human Body Model) Pins,, 8, 9, 2 2. kv Lead Temperature for Soldering Purposes (/8 from case for s) T L 26 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. oz. copper, double sided board. Thermal impedance requires total for T calculations. See example in thermal description. 3

4 PIN DESCRIPTION Pin Name Description Out This pin is the output of the internal OVP chip. It must be connected to the source of the upper FET (Pin 8). 3 Gate FET SW This pin is the gate of the upper FET which is normally used for a switch in series with the battery. It is controlled by the PMU.,, 6, 7 Drain FET SW These pins are the drain of the upper FET. For the lowest on resistance connect all pins together. This set of pins must be connected to the source of the lower (regulator) FET, Pin. 8 Source FET SW This pin is the source of the upper FET and must be connected to the output pin of the internal OVP chip (Pin ). 9,, 3 Drain FET REG These pins are the drain of the lower FET which is normally used for the regulation function. It connects to the positive terminal of the battery. Source FET REG This pin is the source of the lower FET and must be connected to the drain pins of the upper FET. 2 This pin has no internal connections and is isolated from all internal circuitry within the chip. Gate FET REG This pin is the gate of the lower FET which is normally used for the regulation function in series with the battery. It is controlled by the PMU. FLAG The fault flag is an open drain output and therefore requires a pullup resistor. The FLAG pin will be driven low when the input voltage exceeds the OVLO trip level. 2, 6, 7, 2, 22 These pins are connected to the ground of the analog chip. This is a medium impedance connection and should not be used for the ground signal. These pins should either be left floating or connected to ground, but not any other potential. If these pins are connected to ground, the ground pin (9) must still be used. 8 EN The ENABLE pin must be held low for normal operation. When this pin is tied high the unit will be shut down. The state of the enable pin has no impact on the FAULT pin. 9 Gnd This is the ground reference pin for the internal OVP chip. 2 In This pin is the input to the internal OVP chip and connects to the wall, or car adaptor.

5 OVP ELECTRICAL CHARACTERISTICS (Min/Max limits values ( C < T A < +8 C) and V in = +. V. Typical values are T A = +2 C, unless otherwise noted.) Characteristic Symbol Conditions Min Typ Max Unit Input Voltage Range V in.2 2 V Undervoltage Lockout Threshold UVLO V in falls down UVLO threshold V Undervoltage Lockout Hysteresis UVLO hyst 3 7 mv Overvoltage Lockout Threshold OVLO V in rises up OVLO threshold V Overvoltage Lockout Hysteresis OVLO hyst 2 mv V in versus V out Dropout V drop V in = V, I charge = ma 2 mv Supply Quiescent Current Idd No Load, V in =.2 V 2 3 A OVLO Supply Current Idd ovlo V in = 8 V 8 A Output Off State Current I std V in =.2 V, EN =.2 V A FLAG Output Low Voltage Vol flag V in > OVLO, Sink ma on FLAG pin mv FLAG Leakage Current FLAG leak FLAG level = V. na EN Voltage High V ih V in from 3.3 V to.2 V.2 V EN Voltage Low V ol V in from 3.3 V to.2 V. V EN Leakage Current EN leak EN =. V or GND 7 na TIMINGS Start Up Delay t on From V in > UVLO to V out =.8xV in, See Fig 3 & 9. ms FLAG going up Delay t start From V in > UVLO to FLAG =.2 V, See Fig 3 & 3. s Output Turn Off Time t off From V in > OVLO to V out.3 V, See Fig & V in increasing from normal operation to >OVLO at V/ s. No output capacitor. Alert Delay t stop From V in > OVLO to FLAG. V, See Fig & 2 V in increasing from normal operation to >OVLO at V/ s Disable Time t dis From EN. to.2v to V out.3v, See Fig & 3 V in =.7 V. No output capacitor..8. s. 2. s 2. s Thermal Shutdown Temperature T sd C Thermal Shutdown Hysteresis T sdhyst 3 C NOTE: Thermal Shutdown parameter has been fully characterized and guaranteed by design.

6 MOSFET ELECTRICAL CHARACTERISTICS (T J = 2 C unless otherwise noted, all parameters apply to both FET SW and FET REG ) Characteristic Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (Br)DSS V GS = V, I D = 2 A 2 V Drain to Source Breakdown Voltage Temperature Coefficient V (Br)DSS/ T J mv/ C Zero Gate Voltage Drain Current I DSS VGS = V V DS = 6 V T J = 2 C. A T J = 8 C. Gate to Source Leakage Current I GSS V DS = V, V GS = 8. V na ON CHARACTERISTICS (Note 2) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = 2 A.. V Gate Threshold Temperature Coefficient V GS(TH)/ T J 2.7 mv/ C Drain to Source On Resistance R DS(ON) V GS =. V, I D =. A 6 8 m V GS =. V, I D =.6 A 62 8 Forward Transconductance g FS V DS = V, I D = 2.9 A 7. S CHARGES, CAPACITANCES, AND GATE RESISTANCE Input Capacitance C ISS V GS = V, f =. MHz, 7 pf Output Capacitance C OSS V DS = 6 V Reverse Transfer Capacitance C RSS Total Gate Charge Q G(TOT) nc Gate to Source Charge Q GS V GS =. V, V DS = 6 V, I D = 2.6 A.3 Gate to Drain Charge Q GD 2.6 SWITCHING CHARACTERISTICS (Note 3) Turn On Delay Time Rise Time t r V GS =. V, V DD = 6 V, 2 Turn Off Delay Time t d(off) I D = 2.6 A, R G = Fall Time t f 23 t d(on). ns DRAIN SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD V GS = V, I S =. A.8.2 V Reverse Recovery Time Charge Time ta V GS = V, di S /dt = A/ s, Discharge Time tb I S =. A t RR 2 ns Reverse Recovery Charge Q RR. C 2. Pulse test: pulse width 3 s, duty cycle 2% 3. Switching characteristics are independent of operating junction temperatures 6

7 V in UVLO <OVLO V in OVLO V out FLAG t on t start.8 V in.2 V V in R DS(on) x I V out V in (R DS(on) I) FLA G t off.3 V t stop. Figure 3. Start Up Sequence V Figure. Shutdown on Over Voltage Detection EN.2 V EN.2 V V out V in R DS(on) x I FLAG t dis.3 V V in FLAG OVLO UVLO 3 s Figure. Disable on EN = Figure 6. FLAG Response with EN = IN OUT CONDITIONS V IN > OVLO or V IN < UVLO Voltage Detection Figure 7. IN OUT CONDITIONS UVLO < V IN < OVLO Voltage Detection Figure 8. 7

8 TYPICAL OPERATING CHARACTERISTICS Figure 9. Startup V in = Ch, V out = Ch3 Figure. FLAG Going Up Delay V out = Ch3, FLAG = Ch2 Figure. Output Turn Off Time V in = Ch, V out = Ch2 Figure 2. Alert Delay V out = Ch, FLAG = Ch3 Figure 3. Disable Time EN = Ch, V out = Ch2, FLAG = Ch3 Figure. Thermal Shutdown V in = Ch, V out = Ch2, FLAG = Ch3 8

9 TYPICAL OPERATING CHARACTERISTICS R DS(on) (m ) V in = 3.6 V V in = V TEMPERATURE ( C) Figure. Direct Output Short Circuit Figure 6. R DS(on) vs. Temperature (Load = ma) I Q, SUPPLY QUIESCENT CURRENT ( A) C 2 C 6 C V in, INPUT VOLTAGE (V) Figure 7. Supply Quiescent Current vs. V in 9

10 TYPICAL PERFORMANCE CURVES (T J = 2 C unless otherwise noted) I D, DRAIN CURRENT (AMPS) V GS = V to 2.8 V T J = 2 C 2. V.8 V.6 V. V V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) I D, DRAIN CURRENT (AMPS) C 2 2 C T J = C V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure 8. On Region Characteristics Figure 9. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) I D, DRAIN CURRENT (AMPS) V GS = 2. V V GS =. V Figure 2. On Resistance vs. Drain Current and Gate Voltage 6 R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) V GS =. V T J, JUNCTION TEMPERATURE ( C) Figure 2. On Resistance Variation with Temperature V GS = V I DSS, LEAKAGE (na). 2 T J = 2 C T J = C T J = 2 C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 22. Drain to Source Leakage Current vs. Voltage

11 TYPICAL PERFORMANCE CURVES (T J = 2 C unless otherwise noted) C, CAPACITANCE (pf) T J = 2 C C iss 2 C oss I D = 2.7 A C rss T J = 2 C V GS V DS Q g, TOTAL GATE CHARGE (nc) GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 23. Capacitance Variation V GS, GATE TO SOURCE VOLTAGE (VOLTS) 3 2 Q Q2 QT Figure 2. Gate to Source and Drain to Source Voltage vs. Total Gate Charge V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) t, TIME (ns) V DD = V I D =. A V GS =. V t d(off) t f t r t d(on) I S, SOURCE CURRENT (AMPS) 3 2 V GS = V T J = 2 C R G, GATE RESISTANCE (OHMS) V SD, SOURCE TO DRAIN VOLTAGE (VOLTS).2 Figure 2. Resistive Switching Time Variation vs. Gate Resistance Figure 26. Diode Forward Voltage vs. Current ID, DRAIN CURRENT (AMPS) s s ms V GS = 8 V ms SINGLE PULSE T C = 2 C. R DS(on) LIMIT THERMAL LIMIT dc PACKAGE LIMIT.. V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 27. Maximum Rated Forward Biased Safe Operating Area

12 Operational Description The NUS66 provides overvoltage protection for positive voltages up to 2 V. A P Channel FET protects the load connected on the Vout pin, against positive overvoltage conditions. The Output follows the V BUS level until OVLO threshold is reached. Undervoltage Lockout (UVLO) To ensure proper operation under all conditions, the device has a built in undervoltage lock out (UVLO) circuit. As the input ramps from V, the output remains disconnected from input until the V in voltage is above 3.2 V nominal. The FLAG output is pulled to low as long as Vin does not reach the UVLO threshold. This circuit incorporates hysteresis on the UVLO pin to provide noise immunity to transient condition. in the event of an overvoltage condition to protect the output from a positive overvoltage condition. The low Rds(on), during normal operation will minimize the voltage drop across the device. (See Figure 6). ESD Tests The NUS66 meets the requirements of the IEC6 2, level (Input pin, F mounted on board). For the air discharge condition, Vin is protected up to kv. In the contact condition, Vin is protected up to ±8 kv ESD. Please refer to Figure 29 to see the IEC 6 2 electrostatic discharge waveform. Figure 29. IEC 6 2 Curve Figure 28. Output Characteristic vs. Vin Overvoltage Lockout (OVLO) To protect connected systems on Vout Pin from overvoltage, the device has a built in overvoltage lock out (OVLO) circuit. During an overvoltage condition, the output remains disabled until the input voltage is reduced to below the OVLO hysteresis level. The FLAG output is tied to low until Vin is higher than OVLO. This circuit incorporates hysteresis on the OVLO pin to provide noise immunity from transient conditions. FLAG Output The NUS66 provides a FLAG output, which alerts external systems that a fault has occurred. This pin goes low as soon as the OVLO threshold is exceeded. When Vin level recovers to its normal range the FLAG is set high. The FLAG Pin is an open drain output, thus a pullup resistor (typically M Minimum k ) must be provided to V battery. EN Input To enable normal operation, the EN pin shall be forced low or connected to ground. A high level on the pin disconnects the OUT Pin from IN Pin. EN does not override an OVLO or UVLO fault. Internal PMOS FET The NUS66 includes an internal PMOS FET which connects the input to the output pin. This FET is turned off Thermal Impedance Due to cross heating of the three dice in the package, the equivalent thetas are given for this device rather than the individual thetas. To calculate the junction temperatures of a single die, the total power must be used. For example, given the following parameters, the die temperatures will be as shown: I dc = ma R DS(on) OVP = 3 m R DS(on) FETsw = 72 m FET reg has a. V Drop Board copper area = 6 mm 2 Calculate the individual power dissipations: P OVP = (. A) 2 x.3 =.76 W P SW = (. A) 2 x.72 =.8 W P REG =. A x. V =. W P TOT = =.9 W From the Maximum ratings table for thetas, 6 mm 2 and V drop across FET REG : OVP FET 3 C/W FET SW 9 C/W FET REG 92 C/W The die temperature rises above ambient are: T OVP = 3 C/W x.9 W = 32 C T SW = 9 C/W x.9 W = 29 C T REG = 92 C/W x.9 W = C 2

13 ÈÈÈ PIN REFERENCE ÈÈÈ ÈÈÈ 2X 2X. 2X..8 NOTE G G 6X K C. C C DETAIL A E3 E2 C D3 7 D TOP VIEW DETAIL B SIDE VIEW G A3 D 2 8 e G2 D2 BOTTOM VIEW A B E A E 22X b PACKAGE DIMENSIONS A C 22X L. C A B. L EXPOSED Cu QFN22, 3x,.P CASE 8AT ISSUE B SEATING PLANE C NOTE 3 L DETAIL A OPTIONAL CONSTRUCTIONS ÉÉ MOLD CMPD A DETAIL B OPTIONAL CONSTRUCTIONS L A3 ÉÉÉ.3. PITCH NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN. AND.3 MM FROM TERMINAL TIP.. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN NOM MAX A.8.9. A..2. A3.2 REF b D 3. BSC D2... D D E. BSC E2... E E... e. BSC K.2 L L. G.3.. G.9.. G SOLDERING FOOTPRINT* PACKAGE OUTLINE X X.3 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative /D

NTLUS3A90PZ. Power MOSFET 20 V, 5.0 A, Cool Single P Channel, ESD, 1.6x1.6x0.55 mm UDFN Package

NTLUS3A90PZ. Power MOSFET 20 V, 5.0 A, Cool Single P Channel, ESD, 1.6x1.6x0.55 mm UDFN Package NTLUS3A9PZ Power MOSFET V, 5. A, Cool Single P Channel, ESD,.x.x.55 mm UDFN Package Features UDFN Package with Exposed Drain Pads for Excellent Thermal Conduction Low Profile UDFN.x.x.55 mm for Board Space