N-Channel Logic Level Enhancement Mode Field Effect Transistor. Features. TA=25 o C unless otherwise noted

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1 BSS BSS N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These N-Channel enhancement mode field effect transistors are produced using ON Semiconductor s proprietary, high cell density, DMOS technology. These products have been designed to minimize onstate resistance while provide rugged, reliable, and fast switching performance. These products are particularly suited for low voltage, low current applications such as small servo motor control, power MOSFET gate drivers, and other switching applications. Features.7 A, V. R DS(ON) = V GS = V R DS(ON) = V GS =.5 V High density cell design for extremely low R DS(ON) Rugged and Reliable Compact industry standard SOT- surface mount package D D S SOT- G G S Absolute Maximum Ratings TA=5 o C unless otherwise noted Symbol Parameter Ratings Units V DSS Drain-Source Voltage V V GSS Gate-Source Voltage ± V I D Drain Current Continuous (Note ).7 A Pulsed.68 Maximum Power Dissipation (Note ).6 W P D Derate Above 5 C.8 mw/ C T J, T STG Operating and Storage Junction Temperature Range 55 to +5 C T L Maximum Lead Temperature for Soldering Purposes, /6 from Case for Seconds Thermal Characteristics R θja Thermal Resistance, Junction-to-Ambient (Note ) 5 C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity SA BSS 7 8mm units Semiconductor Components Industries, LLC. September-7, Rev. 7 Publication Order Number: BSS/D

2 Electrical Characteristics T A = 5 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain Source Breakdown Voltage V GS = V, I D = 5 µa V BVDSS T J Breakdown Voltage Temperature Coefficient I D = 5 µa,referenced to 5 C 97 mv/ C I DSS Zero Gate Voltage Drain Current V DS = V, V GS = V µa V DS = V,V GS = V T J = 5 C 6 µa V DS = V, V GS = V na I GSS Gate Body Leakage. V GS = ± V, V DS = V ±5 na BSS On Characteristics (Note ) V GS(th) Gate Threshold Voltage V DS = V GS, I D = ma.8.7 V VGS(th) T J Gate Threshold Voltage Temperature Coefficient I D = ma,referenced to 5 C.7 mv/ C R DS(on) Static Drain Source V GS = V, I D =.7 A. 6 Ω On Resistance V GS =.5 V, I D =.7 A. V GS = V, I D =.7 A, T J = 5 C. I D(on) On State Drain Current V GS = V, V DS = 5 V.68 A g FS Forward Transconductance V DS = V, I D =.7 A.8.8 S Dynamic Characteristics C iss Input Capacitance V DS = 5 V, V GS = V, 7 pf C oss Output Capacitance f =. MHz 7 pf C rss Reverse Transfer Capacitance. pf R G Gate Resistance V GS = 5 mv, f =. MHz. Ω Switching Characteristics (Note ) t d(on) Turn On Delay Time V DD = V, I D =.8 A,.7. ns t r Turn On Rise Time V GS = V, R GEN = 6 Ω 9 8 ns t d(off) Turn Off Delay Time 7 ns t f Turn Off Fall Time. 5 ns Q g Total Gate Charge V DS = V, I D =. A,.8.5 nc Q gs Gate Source Charge V GS = V. nc Q gd Gate Drain Charge. nc Drain Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain Source Diode Forward Current.7 A V SD Drain Source Diode Forward V GS = V, I S =. A(Note ).8. V Voltage t rr Diode Reverse Recovery Time I F =.7 A, ns Diode Reverse Recovery Charge d if/d t = A/µs nc Q rr NOTE:. R θja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θjc is guaranteed by design while R θca is determined by the user's board design. a) 5 C/W when mounted on a minimum pad.. Scale : on letter size paper. Pulse Test: Pulse Width µs, Duty Cycle.%

3 Typical Characteristics BSS V GS = V.5V 6.V.8.5V.V.6.5V...V 5 V DS, DRAIN TO SOURCE VOLTAGE (V) R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE V GS =.5V.V.5V.5V 6.V V Figure. On-Region Characteristics. Figure. On-Resistance Variation with Drain Current and Gate Voltage. R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D = 7mA V GS = V T J, JUNCTION TEMPERATURE ( o C) R DS(ON), ON-RESISTANCE (OHM). I D =.8A T A = 5 o C T A = 5 o C 6 8 V GS, GATE TO SOURCE VOLTAGE (V) Figure. On-Resistance Variation with Temperature. Figure. On-Resistance Variation with Gate-to-Source Voltage. V DS = V.8.6. T A = 5 o C. 5 o C -55 o C.5.5 V GS, GATE TO SOURCE VOLTAGE (V) I S, REVERSE DRAIN CURRENT (A).... V GS = V T A = 5 o C 5 o C -55 o C V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature.

4 Typical Characteristics BSS V GS, GATE-SOURCE VOLTAGE (V) I D =.7A V DS = V 5V 8 7V Q g, GATE CHARGE (nc) CAPACITANCE (pf) 8 6 C OSS C ISS C RSS 6 8 V DS, DRAIN TO SOURCE VOLTAGE (V) f = MHz V GS = V Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.... R DS(ON) LIMIT V GS = V R θja = 5 o C/W T A = 5 o C s s DC ms ms ms µs V DS, DRAIN-SOURCE VOLTAGE (V) P(pk), PEAK TRANSIENT POWER (W) 5... t, TIME (sec) R θja = 5 C/W T A = 5 C Figure 9. Maximum Safe Operating Area. Figure. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. D = t, TIME (sec) R θja (t) = r(t) * R θja R θja = 5 o C/W P(pk) t t T J - T A = P * R θja (t) Duty Cycle, D = t / t Figure. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note a. Transient thermal response will change depending on the circuit board design.

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