High Performance Silicon Gate CMOS
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1 SEIONDUTOR TEHNIAL High Performance Silicon Gate OS The 54/74H45A is identical in pinout to the LS45. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs. The H45A is a 3 state noninverting transceiver that is used for way asynchronous communication between data buses. The device has an active low Output Enable pin, which is used to place the I/O ports into high impedance states. The Direction control determines whether data flows from A to or from to A. Output Drive apability: 5 LSTTL Loads Outputs Directly Interface to OS, NOS, and TTL Operating Range: to 6 V Low Input urrent: µa High Noise Immunity haracteristic of OS Devices In ompliance with the Requirements Defined by JEDE Standard No. 7A hip omplexity: 308 FETs or 77 Equivalent Gates N SUFFIX PLASTI PAKAGE ASE DW SUFFIX SOI PAKAGE ASE 75D 04 ORDERING INFORATION 54HXXXAJ 74HXXXAN 74HXXXADW J SUFFIX ERAI PAKAGE ASE eramic Plastic SOI LOGI DIAGRA PIN ASSIGNENT A A A A3 A4 A5 A6 A7 A8 ENALE A A 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GND ENALE PIN 0 = GND PIN = FUNTION TALE ontrol Inputs Output Enable Direction Operation L L Data Transmitted from us to us A L H Data Transmitted from us A to us H X uses Isolated (High Impedance State) X = don t care /97 otorola, Inc. 997 REV 7
2 ÎÎ AXIU RATINGS* SymbolÎ Parameter Value Unit ÎÎ D Supply (Referenced to GND) ÎÎ 0.5 to V V in ÎÎ D Input (Referenced to GND) ÎÎ 0.5 to V VI/OÎÎ D Output (Referenced to GND) ÎÎ 0.5 to V Iin ÎÎ D Input urrent, per Pin ÎÎ ± ma I I/OÎÎ D Output urrent, per Pin ÎÎ ± 35 ma I ÎÎ D Supply urrent, and GND Pins ÎÎ ± 75 ma P D ÎÎ Power Dissipation in Still Air, Plastic or eramic DIP ÎÎ 750 mw SOI Package 500 ÎÎ T stg Storage Temperature 65 to + 50 ÎÎ T L Lead Temperature, mm from ase for 0 Seconds ÎÎ (Plastic DIP or SOI Package) ÎÎ 60 (eramic DIP) * aximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating onditions. Derating Plastic DIP: 0 mw/ from 65 to 5 eramic DIP: 0 mw/ from 00 to 5 SOI Package: 7 mw/ from 65 to 5 For high frequency or heavy load considerations, see hapter of the otorola High Speed OS Data ook (DL9/D). REOENDED OPERATING ONDITIONS Symbol Parameter in ax Unit D Supply (Referenced to GND) V Vin, Vout D Input, Output (Referenced to GND) 0 V TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time =.0 V ns Î (Figure ) = 4.5 V = 6.0 V ÎÎ Î Î Î D ELETRIAL HARATERISTIS (s Referenced to GND) Guaranteed Limit Symbol Parameter Test onditions V 55 to V Unit VIH inimum High Level Input Vout = 0. V V Î Iout µa Î VIL aximum Low Level Input Vout = 0. V V Î Iout µa Î VOH Î inimum High Level Output Î Vin = VIH.0 Î Î Î Iout µa V Vin = VIH Iout ÎÎ.4 ma Iout 6.0 ma Iout 7.8 ma Î Î VOL aximum Low Level Output Vin = VIL.0 0. V Î Iout µa Î Î Î Vin = VIL Iout.4 ma Iout ma Î Iout 7.8 ma This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. OTOROLA DL9 Rev 6
3 D ELETRIAL HARATERISTIS (s Referenced to GND) Guaranteed Limit 55 to ÎÎ Symbol Î Parameter Î Test onditions V Unit Iin aximum Input Leakage urrent Vin = or GND 6.0 ± 0. ±.0 ±.0 µa Î IOZ aximum Three State Leakage Output in High Impedance State 6.0 ± 0.5 ± 5.0 ± 0 µa urrent Î Vin = VIL or ÎÎ VIH Vout = or GND ÎÎ I Î aximum Quiescent Supply Î Vin = or GND µa urrent (per Package) Iout = 0 µa NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in hapter of the otorola High Speed OS Data ook (DL9/D). A ELETRIAL HARATERISTIS (L = 50 pf, Input tr = tf = 6 ns) Guaranteed Limit Î Î 55 to Symbol Parameter V Unit Î tplh, aximum Propagation Delay, A to, to A ns tphl Î (Figures and 3) Î Î tplz, aximum Propagation Delay, Direction or Output Enable to A or ns tphz Î (Figures and 4) Î Î tpzl, aximum Propagation Delay, Output Enable to A or ns tpzh Î (Figures and 4) ttlh, Î aximum Output Transition Time, Any Output ns tthl Î (Figures and 3) in aximum Input apacitance (Pin or Pin 9) pf out aximum Three State I/O apacitance Î (I/O in High Impedance State) ÎÎ ÎÎ pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see hapter of the otorola High Speed OS Data ook (DL9/D). 5, = 5.0 V PD Power Dissipation apacitance (Per Transceiver hannel)* 40 pf * Used to determine the no load dynamic power consumption: PD = PD f + I. For load considerations, see hapter of the otorola High Speed OS Data ook (DL9/D). DL9 Rev 6 3 OTOROLA
4 SWITHING WAVEFORS GND INPUT A OR OR A tr tplh ttlh 0% 90% 0% 90% tf GND tphl tthl ENALE A OR A OR tpzl tpzh tplz tphz 0% 90% GND HIGH IPEDANE VOL VOH HIGH IPEDANE Figure. Figure. TEST IRUITS TEST POINT TEST POINT DEVIE UNDER TEST L* DEVIE UNDER TEST kω L* ONNET TO WHEN TESTING tplz AND tpzl. ONNET TO GND WHEN TESTING tphz AND tpzh. * Includes all probe and jig capacitance Figure 3. * Includes all probe and jig capacitance Figure 4. OTOROLA 4 DL9 Rev 6
5 EXPANDED LOGI DIAGRA A 8 A 3 7 A A A4 A A A7 8 7 A8 9 8 ENALE 9 DL9 Rev 6 5 OTOROLA
6 OUTLINE DIENSIONS H 0 F D A SEATING PLANE G N K J SUFFIX ERAI PAKAGE ASE ISSUE E J L NOTES:. LEADS WITHIN 0.5 (0.00) DIAETER, TRUE POSITION AT SEATING PLANE, AT AXIU ATERIAL ONDITION.. DIENSION L TO ENTER OF LEADS WHEN FORED PARALLEL. 3. DIENSIONS A AND INLUDE ENISUS. ILLIETERS INHES DI IN AX IN AX A D F G.54 S 0.00 S H J K L 7.6 S S N T SEATING PLANE G E A F 0 N K D PL 0.5 (0.00) T A N SUFFIX PLASTI PAKAGE ASE ISSUE E L J PL 0.5 (0.00) T NOTES:. DIENSIONING AND TOLERANING PER ANSI Y4.5, 98.. ONTROLLING DIENSION: INH. 3. DIENSION L TO ENTER OF LEAD WHEN FORED PARALLEL. 4. DIENSION DOES NOT INLUDE OLD FLASH. INHES ILLIETERS DI IN AX IN AX A D E S.7 S F G 0.00 S.54 S J K L S 7.6 S N A X D (0.5) T A S S 8X G K 0X P 0.00 (0.5) T SEATING PLANE DW SUFFIX PLASTI SOI PAKAGE ASE 75D 04 ISSUE E J F R X 45 NOTES:. DIENSIONING AND TOLERANING PER ANSI Y4.5, 98.. ONTROLLING DIENSION: ILLIETER. 3. DIENSIONS A AND DO NOT INLUDE OLD PROTRUSION. 4. AXIU OLD PROTRUSION 0.50 (0.006) PER SIDE. 5. DIENSION D DOES NOT INLUDE DAAR PROTRUSION. ALLOWALE DAAR PROTRUSION SHALL E 0.3 (0.005) TOTAL IN EXESS OF D DIENSION AT AXIU ATERIAL ONDITION. ILLIETERS INHES DI IN AX IN AX A D F G.7 S S J K P R OTOROLA 6 DL9 Rev 6
7 otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in otorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any license under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/Affirmative Action Employer. fax is a trademark of otorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: otorola Literature Distribution; JAPAN: Nippon otorola Ltd.; Tatsumi SPD JLD, 6F Seibu utsuryu enter, P.O. ox 5405, Denver, olorado or Tatsumi Koto Ku, Tokyo 35, Japan fax : RFAX0@ .sps.mot.com TOUHTONE ASIA/PAIFI: otorola Semiconductors H.K. Ltd.; 8 Tai Ping Industrial Park, US & anada ONLY Ting Kok Road, Tai Po, N.T., Hong Kong INTERNET: DL9 Rev 6 74H45A/D 7 OTOROLA
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SEICONDUCTOR TECHNICAL DATA Order this document by /D The RF Line The is designed for 9 Hz base stations in both analog and digital applications. It incorporates high value emitter ballast resistors, gold
Distributed by: www.jameco.com 1--31-4242 The content and copyrights of the attached material are the property of its owner. Order this document by M3/D The M3 is an integrated circuit featuring wide range
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COLLECTOR BASE EMITTER BC 557 BC556. mw mw/ C PD PD Characteristic Symbol Min Typ Max Unit V(BR)CEO BC557 BC558 V(BR)CBO BC557 BC558
SEMICONDUCTOR TECHNICAL DATA Order this document by /D PNP Silicon COLLECTOR 2 BASE 3 EMITTER MAXIMUM RATINGS Rating Symbol BC 556 BC 557 BC 558 Unit Collector Emitter oltage CEO 65 45 3 dc Collector Base
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MARKING DIAGRAMS Figure 1. Logic Diagram ORDERING INFORMATION Figure 2. Dip Pin Assignment CDIP 16 L SUFFIX CASE 620A
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ARCHIVE INFORMATION LOW POWER NARROWBAND FM IF
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