High Performance Silicon Gate CMOS
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1 SEIONUTOR TEHNIAL ATA HighPerformance Siliconate OS The 74H75 is identical in pinout to the LS75. The device inputs are compatible with standard OS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device coists of two independent 2bit traparent latches. Each latch stores the input data while Latch Enable is at a logic low. The outputs follow the data inputs when Latch Enable is at a logic high. Output rive apability: 10 LSTTL Loads Outputs irectly Interface to OS, NOS, and TTL Operating oltage Range: 2 to 6 Low Input urrent: 1 µa High Noise Immunity haracteristic of OS evices In ompliance with the Requirements efined by EE Standard No. 7A hip omplexity: 80 ETs or 20 Equivalent ates 1 1 N SUIX PLASTI PAAE ASE SUIX SOI PAAE ASE ORERIN INORATION 74HXXN 74HXX Plastic SOI LOI IARA PIN ASSINENT a 1 a 0a a ATA INPUTS 0 1 2, 6 3, 7 2IT TRANSPARENT LATH, 10 1, 11 15, 14, a LEb 0b a LEa N b 1b 7 10 b 1b 8 1b LATH 13, 4 PIN 5 = PIN 12 = N UNTION TALE Inputs Outputs Latch Enable L H L H H H H L X L X = don t care = latched data 10/5 otorola, Inc RE 6
2 74H75 AXIU RATINS* SymbolÎ Parameter alue ÎÎ Supply oltage (Referenced to N) ÎÎ 0.5 to inîî Input oltage (Referenced to N) ÎÎ 1.5 to outîî Output oltage (Referenced to N) ÎÎ 0.5 to I ÎÎ in Input urrent, per Pin ÎÎ ± 20 I outîî Output urrent, per Pin ÎÎ ± 25 I ÎÎ Supply urrent, and N Pi ÎÎ ± 50 ÎÎ P Power issipation in Still Air Plastic IP ÎÎ 750 mw Î TstgÎÎ SOI Package 500 Storage Temperature 65 to LÎÎ T Lead Temperature, 1 mm from ase for 10 Seconds Î (Plastic IP or SOI Package) 260 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. or proper operation, in and out should be cotrained to the range N (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either N or ). Unused outputs must be left open. * aximum Ratings are those values beyond which damage to the device may occur. unctional operation should be restricted to the Recommended Operating onditio. erating Plastic IP: 10 mw/ from 65 to 125 SOI Package: 7 mw/ from 65 to 125 or high frequency or heavy load coideratio, see hapter 2 of the otorola HighSpeed OS ata ook (L12/). REOENE OPERATIN ONITIONS Symbol Parameter in ax Supply oltage (Referenced to N) 6.0 Î in, out Input oltage, Output oltage (Referenced to N) 0 TA Operating Temperature, All Package Types 55 + Î 125 tr, tf Input Rise and all Time = Î (igure 1) = = ELETRIAL HARATERISTIS (oltages Referenced to N) uaranteed Limit Î 55 to Symbol Parameter Test onditio IH inimum HighLevel Input out = 0.1 or 0.1 oltage Î Iout 20 µa Î ÎÎ IL Î aximum LowLevel Input Î out = 0.1 or 0.1 oltage Iout ÎÎ ÎÎ ÎÎ 20 µa Î OH inimum HighLevel Output in = IH or IL oltage Î Iout ÎÎ 20 µa in = IH or IL Iout 4.0 ÎÎ Iout Î OL aximum LowLevel Output in = IH or IL oltage Î Iout 20 µa Î ÎÎ in = IH or IL Iout 4.0 Iout 5.2 ÎÎ ÎÎ 0.40 Î Iin aximum Input Leakage urrent in = or N 6.0 ± 0.1 ± 1.0 ± 1.0 µa Î I aximum uiescent Supply in = or N 6.0 urrent (per Package) Iout = 0 µa ÎÎ µa NOTE: Information on typical parametric values can be found in hapter 2 of the otorola HighSpeed OS ata ook (L12/). OTOROLA 2 HighSpeed OS Logic ata
3 74H75 A ELETRIAL HARATERISTIS (L = 50 p, Input tr = tf = 6 ) Î uaranteed Limit Î 55 to SymbolÎ Parameter Î , Î aximum Propagation elay, to ÎÎ Î ÎÎ (igures 1 and 5) Î 26 32, aximum Propagation elay, to ÎÎ (igures 1 and 5) Î ÎÎ ÎÎ , Î aximum Propagation elay, Latch Enable to ÎÎ Î ÎÎ (igures 2 and 5) Î 31 38, aximum Propagation elay, Latch Enable to ÎÎ (igures 2 and 5) Î ÎÎ ÎÎ ttlh, Î aximum Output Traition Time, Any Output Î Î ÎÎ tthl (igures 3 and 5) aximum Input apacitance p in 1. or propagation delays with loads other than 50 p, see hapter 2 of the otorola HighSpeed OS ata ook (L12/). 2. Information on typical parametric values can be found in hapter 2 of the otorola HighSpeed OS ata ook (L12/). 25, = 5.0 P Power issipation apacitance (Per Latch)* 35 p * Used to determine the noload dynamic power coumption: P = P 2 f + I. or load coideratio, see hapter 2 of the otorola HighSpeed OS ata ook (L12/). TIIN REUIREENTS (Input tr = tf = 6 ) uaranteed Limit Î 55 to ÎÎ SymbolÎ Parameter Î tsu inimum Setup Time, to Latch Enable ÎÎ Î ÎÎ (igure 4) th inimum Hold Time, Latch Enable to Î (igure 4) Î ÎÎ tw Î inimum Pulse Width, Latch Enable Input ÎÎ Î ÎÎ (igure 4) tr, tf aximum Input Rise and all Times Î (igure 1) Î NOTE: Information on typical parametric values can be found in hapter 2 of the otorola HighSpeed OS ata ook (L12/). HighSpeed OS Logic ata 3 OTOROLA
4 74H75 SWITHIN WAEORS tr tf 10% 0% LATH igure 1. igure 2. ttlh ANY OUTPUT 10% 0% tthl LATH tsu ALI th N N tw igure 3. igure 4. TEST POINT EIE UNER TEST OUTPUT L* * Includes all probe and jig capacitance igure 5. Test ircuit EXPANE LOI IARA 0 2, 6, 10 ATA INPUTS 1, , 7 15, 1 LATH 13, 4 14, 8 1 OTOROLA 4 HighSpeed OS Logic ata
5 74H75 OUTLINE IENSIONS A 1 8 H S T SEATIN PLANE PL (0.010) T A N SUIX PLASTI PAAE ASE ISSUE R L 1. IENSIONIN AN TOLERANIN PER ANSI Y1, ONTROLLIN IENSION: INH. 3. IENSION L TO ENTER O LEAS WHEN ORE PARALLEL. 4. IENSION OES NOT INLUE OL LASH. 5. ROUNE ORNERS OPTIONAL. I A H L S INHES IN AX S S ILLIETERS IN AX S 1.27 S T SEATIN PLANE 1 8 A PL (0.010) T S A S SUIX PLASTI SOI PAAE ASE ISSUE P 8 PL (0.010) R X IENSIONIN AN TOLERANIN PER ANSI Y1, ONTROLLIN IENSION: ILLIETER. 3. IENSIONS A AN O NOT INLUE OL PROTRUSION. 4. AXIU OL PROTRUSION 0.15 (0.006) PER SIE. 5. IENSION OES NOT INLUE AAR PROTRUSION. ALLOWALE AAR PROTRUSION SHALL E (0.005) TOTAL IN EXESS O THE IENSION AT AXIU ATERIAL ONITION. I A P R ILLIETERS IN AX INHES IN AX S S otorola reserves the right to make changes without further notice to any products herein. otorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does otorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters can and do vary in different applicatio. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. otorola does not convey any licee under its patent rights nor the rights of others. otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the otorola product could create a situation where personal injury or death may occur. Should uyer purchase or use otorola products for any such unintended or unauthorized application, uyer shall indemnify and hold otorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that otorola was negligent regarding the design or manufacture of the part. otorola and are registered trademarks of otorola, Inc. otorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: otorola Literature istribution; APAN: Nippon otorola Ltd.; TatsumiSPL, Toshikatsu Otsuki, P.O. ox 2012; Phoenix, Arizona Seibuutsuryuenter, 3142 Tatsumi otou, Tokyo 135, apan AX: RAX0@ .sps.mot.com TOUHTONE (602) HON ON: otorola Semiconductors H.. Ltd.; 8 Tai Ping Industrial Park, INTERNET: 51 Ting ok Road, Tai Po, N.T., Hong ong HighSpeed OS Logic ata OELINE 74H75/ 5 OTOROLA
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MARKING DIAGRAMS LOGIC DIAGRAM PIN ASSIGNMENT ORDERING INFORMATION FUNCTION TABLE DIP 14 N SUFFIX CASE 646 MC74HC4066AN AWLYYWW
High Performance Silicon Gate CMOS The MC74HC466A utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF channel leakage current. This bilateral switch/
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SEMICONDUCTOR TECHNICAL DATA Order this document by TIP47/D... designed for line operated audio output amplifier, Switchmode power supply drivers and other switching applications. 25 V to 4 V (Min) VCEO(sus)
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO- Binary Counter. Separate
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BASE 2N2906A 2N2907,A N2904A 2N2905,A P D P D mw mw/ C Watts mw/ C T J, T stg 65 to +200 C
SEMICONDUCTOR TECHNICAL DATA Order this document by N94A/D PNP Silicon Annular Hermetic Transistors Designed for high speed switching circuits, DC to VHF amplifier applications and complementary circuitry.
MC14001B Series. B Suffix Series CMOS Gates MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B
MC4B Series B Suffix Series CMOS Gates MC4B, MC4B, MC4B, MC4B, MC4B, MC4B, MC4B, MC4B The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure
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MARKING DIAGRAMS Figure 1. Logic Diagram ORDERING INFORMATION Figure 2. Dip Pin Assignment CDIP 16 L SUFFIX CASE 620A
The MC0H6 is a functional/pinout duplication of the MC06, with 00% improvement in propagation delay and no increase in power supply current. Propagation Delay,.0 ns Typical Power Dissipation 85 mw Typ/Pkg
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Order this document by MC43/D The seven NPN Darlington connected transistors in these arrays are well suited for driving lamps, relays, or printer hammers in a variety of industrial and consumer applications.
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Order this document by MC7/D... includes Oscillator, Mixer, Limiting Amplifier, Quadrature Discriminator, Active, Squelch, Scan Control, and Mute Switch. The MC7 is designed for use in FM dual conversion
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The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
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