P54FCT373T/74fct373T OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES DESCRIPTION. Function, Pinout and Drive Compatible with the FCT and F Logic

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1 P54FCT373T/74fct373T OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.6ns max (MIL) Reduced VOH (typically = 3.3 V) versions of equivalent FCT functions DESCRIPTION The P54/74FCT373T is an octal transparent latch, built using advanced CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data Edge-rate control circuitry for significantly improved noise characteristics ESD protection exceeds 2000V Power-off disable feature Matched rise and fall times Fully compatible with TTL input and output logic levels 32 ma sink current, 12 ma source current (MIL) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high-impedance state. Functional Block Diagram Pin ConfigurationS DIP (D2) LCC (L2) Created April 2016

2 Maximum Ratings (1,2) Sym Parameter Value Unit T STG Storage Temperature -65 to +150 C T A Ambient Temperature Under Bias -65 to +135 C Potentional to Ground -0.5 to +7.0 V P T Power Dissipation 0.5 W I OUTPUT Current Applied to Output 120 ma Input Voltage -0.5 to +7.0 V V OUT Voltage Applied to Output -0.5 to +7.0 V RECOMMENDED OPERATING CONDITIONS Grade Ambient Temp GND Military -55 C to +125 C 0V 5.0V ± 10% Industrial -40 C to +85 C 0V 5.0V ± 5% CAPACITANCES ( = 5.0V, T A = 25 C, f = 1.0MHz) Sym Parameter Conditions Typ Unit C IN Input Capacitance = 0V 6 pf C OUT Output Capacitance V OUT = 0V 8 pf DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Sym Parameter Test Conditions Min Max Unit V OH1 V OH2 High Level Output Voltage For all inputs affecting output under test = 2.0V or 0.8V For all other inputs I OH = -300 µa, (Min) For all inputs affecting output under test = 2.0V or 0.8V For all other inputs I OH = -12 ma, (Min) V V V OL1 V OL2 Low Level Output Voltage For all inputs affecting output under test = 2.0V or 0.8V For all other inputs I OL = 300 µa, (Min) For all inputs affecting output under test = 2.0V or 0.8V For all other inputs I OL = 32 ma, (Min) 0.20 V 0.55 V I OZH Three-State Output Leakage Current High OE = V IH or V IL V IH = 2.0V, V IL = 0.8V For all other inputs, V OUT, 0.1 µa I OZL Three-State Output Leakage Current Low OE = V IH or V IL V IH = 2.0V, V IL = 0.8V For all other inputs, V OUT = GND, -0.1 µa V IC- Negative Input Clamp Voltage For input under test, I IN = -15 ma, (Min) -1.2 V I IH Input Current High For input under test, For all other inputs,, 0.1 µa I IL Input Current Low For input under test, = GND For all other inputs,, -0.1 µa C IN Input Capacitance T C = +25 C, = GND, F = 1 MHz 10 pf C OUT Output Capacitance T C = +25 C, = GND, F = 1 MHz 12 pf Notes: 1. Operation beyond the limits set forth in the above table may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 2. Unused inputs must always be connected to an appropriate logic voltage level, preferably either or ground. 3. Per TTL driven input ( =3.4V); all other inputs at. Page 2

3 Sym Parameter Test Conditions Min Max Unit I OS Output Short Circuit Current For all inputs, V OUT = GND, ma I CCD Dynamic Power Supply Current Outputs open, 0.25 ma/ MHz ΔI CC Quiescent Supply Current Delta, TTL Input Level For input under test, V For all other inputs,, 2.0 ma I CCH I CCL Quiescent Supply Current, Outputs High Quiescent Supply Current, Outputs Low For all other inputs,, 1.5 ma 1.5 ma I CCZ Quiescent Supply Current, Outputs Three-State For all other inputs,, 1.5 ma I CCT1 Total Supply Current Outputs open LE OE = GND 50% duty cycle For nonswitching input,, f i = 10 MHz One bit toggling f i = 2.5 MHz Eight bits toggling For switching inputs, For switching inputs, = 3.4 V For switching inputs, For switching inputs, = 3.4 V ma V OLP 980 Low Level Ground Bounce Noise V OLV V IH = 3.0 V, V IL = 0.0 V, T A = +25 C, = 5.0 V V OHP mv High Level Bounce Noise V OHV -440 Page 3

4 AC CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Sym Parameter Condition 54/74FCT373T 54/74FCT373AT Ind Mil Ind Mil Min Max Min Max Min Max Min Max Unit t PLH t PHL Propagation Delay D N to O N ns t PLH t PHL Propagation Delay LE to O N ns t PZH t PZL Output Enable Time ns t PHZ C L = 50pF Output Disable Time ns t PLZ R L = 500Ω t SU Set-up Time HIGH or LOW, D N to LE ns t H Hold Time HIGH or LOW, D N to LE ns t W LE Pulse Width High ns Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open Page 4

5 SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH PROPAGATION DELAY ENABLE/DISABLE TIMES PIN DESCRIPTION FUNCTION TABLE Pin Names Description Inputs Outputs D N LE OE O N Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs D N LE OE O N H H L H L H L L X X H Z H = HIGH voltage level steady-state L = LOW voltage level steady state X = Don't Care Z = High Impedance Page 5

6 ORDERING INFORMATION Page 6

7 Pkg # D2 # Pins 20 (300 mil) Symbol Min Max A b b c D E ea e BSC BSC L Q S S α 0 15 SIDEBRAZED DUAL INLINE PACKAGE Pkg # L2 # Pins 20 Symbol Min Max A A B D/E D1/E BSC D2/E BSC D3/E e BSC h REF j REF L L L ND 5 NE 5 SQUARE LEADLESS CHIP CARRIER Page 7

8 REVISIONS DOCUMENT NUMBER DOCUMENT TITLE LOGIC114 P54FCT373T - OCTAL TRANSPARENT LATCHES REV ISSUE DATE ORIGINATOR DESCRIPTION OF CHANGE OR Apr 2016 JDB New Data Sheet Page 8