74LCX573TTR OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

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1 OCTAL D-TYPE LATCH NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : t PD = 8.0 (MAX.) at V CC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: I OH = I OL = 24mA (MIN) at V CC = 3V PCI BUS LEVELS GUARANTEED AT 24 ma BALANCED PROPAGATION DELAYS: t PLH t PHL OPERATING VOLTAGE RANGE: V CC (OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LCX573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2 MOS technology. It is ideal for low power and high speed 3.3V applicatio; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type latch are controlled by a latch SOP ORDER CODES TSSOP PACKAGE TUBE T & R SOP 74LCX573M 74LCX573MTR TSSOP 74LCX573TTR enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power coumption. All inputs and outputs are equipped with protection circuits agait static discharge, giving them 2KV ESD immunity and traient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS September /10

2 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION TRUTH TABLE INPUT OUTPUT 1 OE 3 State Output Enable Input (Active LOW) 2, 3, 4, 5, 6, D0 to D7 Data Inputs 7, 8, 9 12, 13, 14, Q0 to Q7 3-State Latch Outputs 15, 16, 17, 18, LE Latch Enable Input 10 GND Ground (0V) 20 V CC Positive Supply Voltage OE LE D Q H X X Z L L X NO CHANGE* L H L L L H H H X : Don t Care Z : High Impedance * : Q Outputs are latched at the time when the LE input is taken LOW. LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10

3 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V CC Supply Voltage -0.5 to +7.0 V V I DC Input Voltage -0.5 to +7.0 V V O DC Output Voltage (OFF State) -0.5 to +7.0 V V O DC Output Voltage (High or Low State) (note 1) -0.5 to V CC V I IK DC Input Diode Current - 50 ma I OK DC Output Diode Current (note 2) - 50 ma I O DC Output Current ± 50 ma I CC DC Supply Current per Supply Pin ± 100 ma I GND DC Ground Current per Supply Pin ± 100 ma T stg Storage Temperature -65 to +150 C T L Lead Temperature (10 sec) 300 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditio is not implied 1) I O absolute maximum rating must be observed 2) V O < GND RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit V CC Supply Voltage (note 1) 2.0 to 3.6 V V I Input Voltage 0 to 5.5 V V O Output Voltage (OFF State) 0 to 5.5 V V O Output Voltage (High or Low State) 0 to V CC V I OH, I OL High or Low Level Output Current (V CC = 3.0 to 3.6V) ± 24 ma I OH, I OL High or Low Level Output Current (V CC = V) ± 12 ma T op Operating Temperature -55 to 125 C dt/dv Input Rise and Fall Time (note 2) 0 to 10 /V 1) Truth Table guaranteed: 1.5V to 3.6V 2) V IN from 0.8V to 2V at V CC = 3.0V 3/10

4 DC SPECIFICATIONS Test Condition Value Symbol V IH V IL V OH V OL I I I off I OZ Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage V CC (V) to to 85 C -55 to 125 C Min. Max. Min. Max. Unit V to 3.6 I O =-100 µa V CC -0.2 V CC -0.2 I O =-12 ma I O =-18 ma I O =-24 ma V to 3.6 I O =100 µa I O =12 ma Input Leakage Current Power Off Leakage Current High Impedance Output Leakage to 3.6 Current Quiescent Supply Current to 3.6 I O =16 ma I O =24 ma to 3.6 V I = 0 to 5.5V ± 5 ± 5 µa 0 V I or V O = 5.5V µa V I = V IH or V IL V O = 0 to V CC ± 5 ± 5 µa I CC V I = V CC or GND µa V I or V O = 3.6 to 5.5V ± 10 ± 10 I CC I CC incr. per Input to 3.6 V IH = V CC - 0.6V µa V V DYNAMIC SWITCHING CHARACTERISTICS Test Condition Value Symbol Parameter T V A = 25 C CC (V) Min. Typ. Max. V OLP Dynamic Low Level Quiet C L = 50pF 0.8 Output (note 1) 3.3 V OLV V IL = 0V, V IH = 3.3V ) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. Unit V 4/10

5 AC ELECTRICAL CHARACTERISTICS Test Condition Value Symbol t PLH t PHL t PLH t PHL t PZL t PZH t PLZ t PHZ t S t h t W t OSLH t OSHL Parameter Propagation Delay Time (Dn to Qn) Propagation Delay Time (LE to Qn) Output Enable Time to HIGH and LOW level Output Disable Time from HIGH to LOW level Set-Up Time, HIGH or LOW level (Dn to LE) Hold Time, HIGH or LOW level (Dn to LE) LE Pulse Width, HIGH Output To Output Skew Time (note1, 2) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (t OSLH = t PLHm - t PLHn, t OSHL = t PHLm - t PHLn ) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS V CC (V) C L (pf) R L (Ω) t s = t r () -40 to 85 C -55 to 125 C Min. Max. Min. Max to to to to to to to to Unit Test Condition Value Symbol Parameter V CC T A = 25 C Unit (V) Min. Typ. Max. C IN Input Capacitance 3.3 V IN = 0 to V CC 6 pf C OUT Output Capacitance 3.3 V IN = 0 to V CC 12 pf C PD Power Dissipation Capacitance 3.3 f IN = 10MHz 25 (note 1) V IN = 0 or V CC pf 1) C PD is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current coumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /8 (per latch) 5/10

6 TEST CIRCUIT t PLH, t PHL t PZL, t PLZ TEST t PZH, t PHZ C L = 50 pf or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = Z OUT of pulse generator (typically 50Ω) SWITCH Open 6V GND WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1mhz; 50% duty cycle) 6/10

7 WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1mhz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY TIME (f=1mhz; 50% duty cycle) 7/10

8 SO-20 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A a a b b C c1 45 (typ.) D E e e F L M S 8 (max.) PO13L 8/10

9 TSSOP20 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A A A b c D E E e 0.65 BSC BSC K L A A2 A1 b e c K L E D E1 PIN 1 IDENTIFICATION C 9/10

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