74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)

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1 INTEGRATED CIRCUIT Quad 2-line to 1-line selector/multiplexer, non-inverting (3-tate) 1995 Mar 31 IC15 Data Handbook Philips emiconductors

2 (3-tate) FEATURE Industrial range available ( 40 C to +85 C) Multifunction capability Non-inverting data path 3-tate outputs ee 74F258A for inverting version PIN CONFIGURATION 1 I0a 2 I1a 3 Ya 4 I0b V CC I0d I1d Yd DECRIPTION The has four identical 2-input multiplexers with 3-tate outputs which select 4 bits of data from two sources uncer control of a common elect () input. The I0a inputs are selected when the common elect input is Low and the I1n inputs are selected when the common elect input is High. Data appears at the outputs in true non-inverted form from the selected inputs. The is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the common lect input. Outputs are forced to a high impedance off state when the Output Enable () is High. All but one device must be in high impedance state to avoid currents that would exceed the maximum rating if the outputs were tied together. Design of the Output Enable signals must ensure that there is no overlap when outputs of 3-state devices were tied together. TYPE I1b Yb GND TYPICAL PROPAGATION DELAY I0c I1c Yc F00673 TYPICAL UPPLY CURRENT (TOTAL) 4.3ns 12mA ORDERING INFORMATION DECRIPTION COMMERCIAL RANGE V CC = 5V ±10%, T amb = 0 C to +70 C ORDER CODE INDUTRIAL RANGE V CC = 5V ±10%, T amb = 40 C to +85 C DRAWING NUMBER 16-pin plastic DIP NN IN OT pin plastic O ND ID OT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PIN DECRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW I0n, I1n Data inputs 1.0/1.0 20µA/0.6mA Common elect input 1.0/1.0 20µA/0.6mA Output Enable input (active Low) 1.0/1.0 20µA/0.6mA Ya Yd Data outputs 150/33 3.0mA/20mA NOTE: One (1.0) FAT unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC YMBOL LOGIC YMBOL (IEEE/IEC) EN G I0a I1a I0b I1b I0c I1c I0d I1d MUX V CC = Pin 16 GND = Pin F F Mar

3 (3-tate) LOGIC DIAGRAM I0a I1a I0b I1b I0c I1c I0d I1d FUNCTION TABLE INPUT OUTPUT I0 I1 Y H X X X Z L H X L L L H X H H L L L X L L L H X H H = High voltage level L = Low voltage level X = Don t care Z = High impedance off state V CC = Pin 16 GND = Pin 8 F00676 APPLICATION 2 1 ENABLE C B A 74F139 Y0 Y1 Y2 Y3 0 WORD A WORD B WORD C WORD D WORD E WORD F WORD G WORD H I0a I1a I0b I1b I0c I1c I0d I1d I0a I1a I0b I1b I0c I1c I0d I1d I0a I1a I0b I1b I0c I1c I0d I1d I0a I1a I0b I1b I0c I1c I0d I1d 4-BIT DATA BU F Mar 31 3

4 (3-tate) ABOLUTE MAXIMUM RATING (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) YMBOL PARAMETER RATING UNIT V CC upply voltage 0.5 to +7.0 V V IN Input voltage 0.5 to +7.0 V I IN Input current 30 to +5 ma V OUT Voltage applied to output in High output state 0.5 to V CC V I OUT Current applied to output in Low output state 48 ma T amb Operating free-air temperature range Commercial range 0 to +70 C Industrial range 40 to +85 C T stg torage temperature range 65 to +150 C RECOMMENDED OPERATING CONDITION YMBOL PARAMETER LIMIT MIN NOM MAX V CC upply voltage V V IH High-level input voltage V V IL Low-level input voltage 0.8 V I IK Input clamp current 18 ma I OH High-level output current 3 ma I OL Low-level output current 24 ma T amb Operating free-air temperature range UNIT Commercial range C Industrial range C 1995 Mar 31 4

5 (3-tate) DC ELECTRICAL CHARACTERITIC (Over recommended operating free-air temperature range unless otherwise noted.) YMBOL PARAMETER TET CONDITION 1 MIN TYP 2 MAX LIMIT UNIT V = MIN, V = MAX, ±10%V CC 2.4 V V OH High-level output voltage CC IL V IH = MIN, I OH = MAX ±5%V CC V V = MIN, V = MAX, ±10%V CC V V OL Low-level output voltage CC IL V IH = MIN, I OL = MAX ±5%V CC V V IK Input clamp voltage V CC = MIN, I I = I IK V I I Input current at maximum input voltage V CC = MAX, V I = 7.0V 100 µa I IH High-level input current V CC = MAX, V I = 2.7V 20 µa I IL Low-level input current V CC = MAX, V I = 0.5V 0.6 ma I OZH I OZL Off state output current, High-level voltage applied Off state output current, Low-level voltage applied V CC = MAX, V O = 2.7V 50 µa V CC = MAX, V O = 0.5V 50 µa I O hort-circuit output current 3 V CC = MAX ma I CCH ma I CC upply current 4 (total) I CCL V CC = MAX 1 2 ma I CCZ ma NOTE: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at V CC = 5V, T amb = 25 C. 3. Not more than one output should be shorted at a time. For testing I O, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I O tests should be performed last. 4. Measure I CC with all outputs open and inputs grounded. AC ELECTRICAL CHARACTERITIC YMBOL t PLH t PHL t PLH t PHL t PZH t PZL t PHZ t PLZ PARAMETER Propagation delay In to Yn Propagation delay to Yn Output Enable time to High or Low level Output Disable time from High or Low level TET CONDITION Waveform 1 Waveform 1 Waveform 2 Waveform 3 Waveform 2 Waveform 3 T amb = +25 C V CC = +5.0V C L = 50pF R L = 500Ω LIMIT T amb = 0 C to +70 C V CC = +5.0V ± 10% C L = 50pF R L = 500Ω T amb = 40 C to +85 C V CC = +5.0V ± 10% C L = 50pF R L = 500Ω MIN TYP MAX MIN MAX MIN MAX UNIT ns ns ns ns 1995 Mar 31 5

6 (3-tate) AC WAVEFORM For all waveforms, = 1.5V. In or t PHL t PLH Yn F00679 Waveform 1. Propagation Delay, Data and elect to Output t PZH t PHZ t PZL t PLZ Yn V OH 0.3V 0V Yn V OL +0.3V F00213 Waveform 2. 3-tate Output Enable Time to High Level and Output Disable Time from High Level F00214 Waveform 3. 3-tate Output Enable Time to Low Level and Output Disable Time from Low Level TET CIRCUIT AND WAVEFORM PULE GENERATOR V IN V CC D.U.T. V OUT R L 7.0V NEGATIVE PULE 90% 10% t THL ( t f ) t w t TLH ( t r ) 10% 90% AMP (V) 0V R T C L R L Test Circuit for 3-tate Outputs WITCH POITION TET WITCH t PLZ closed t PZL closed All other open POITIVE PULE 10% t TLH ( t r ) t THL ( t f ) 90% 90% t w Input Pulse Definition 10% AMP (V) 0V DEFINITION: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 74F INPUT PULE REQUIREMENT amplitude rep. rate t w t TLH t THL 3.0V 1.5V 1MHz 500ns 2.5ns 2.5ns F Mar 31 6

7 Quad 2-line 1-line selector/multiplexer, non-inverting (3-tate) DIP16: plastic dual in-line package; 16 leads (300 mil) OT Mar 31 7

8 Quad 2-line 1-line selector/multiplexer, non-inverting (3-tate) O16: plastic small outline package; 16 leads; body width 3.9 mm OT Mar 31 8

TYPE. ORDER CODE INDUSTRIAL RANGE V CC = 5V ±10%, T amb = 40 C to +85 C

TYPE. ORDER CODE INDUSTRIAL RANGE V CC = 5V ±10%, T amb = 40 C to +85 C Philips emiconductors Quad 2-line to -line selector/multiplexer, non-inverting (3-tate) FEATURE Industrial range available ( 40 C to +85 C) Multifunction capability Non-inverting data path 3-tate outputs

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