74AC821 74ACT Bit D-Type Flip-Flop with 3-STATE Outputs

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1 74AC821 74ACT Bit D-Type Flip-Flop with 3-STATE Outputs General Description The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE outputs arranged in a broadside pinout. Ordering Code: Features 3-STATE outputs for bus interfacing Noninverting outputs Outputs source/sink 24 ma TTL compatible inputs November 1988 Revised August 2000 Order Number Package Number Package Description 74AC821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, Wide 74AC821SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide 74ACT821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, Wide 74ACT821MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT821SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. (SPC not available in Tape and Reel.) Logic Symbols Connection Diagram 74AC821 74ACT Bit D-Type Flip-Flop with 3-STATE Outputs IEEE/IEC Pin Descriptio Pin Names D 0 D 9 O 0 O 9 OE CP Description Data Inputs Data Outputs Output Enable Input Clock Input FACT is a trademark of Fairchild Semiconductor Corporation Fairchild Semiconductor Corporation DS

2 74AC821 74ACT821 Functional Description The AC/ACT821 coists of ten D-type edge-triggered flipflops. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP traition. Function Table With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. L H H H Load H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance = LOW-to-HIGH Clock Traition Logic Diagram Inputs Internal Outputs Function OE CP D Q O H L L Z High Z H H H Z High Z L L L L Load Please note that this diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays. 2

3 Absolute Maximum Ratings(Note 1) Supply Voltage (V CC ) 0.5V to + 7.0V DC Input Diode Current (I IK ) V I = 0.5V 20 ma V I = V CC + 0.5V + 20 ma DC Input Voltage (V I ) 0.5V to V CC + 0.5V DC Output Diode Current (I OK ) V O = 0.5V 20 ma V O = V CC + 0.5V + 20 ma DC Output Voltage (V O ) 0.5V to V CC + 0.5V DC Output Source or Sink Current (I O ) ± 50 ma DC V CC or Ground Current per Output Pin (I CC or I GND ) ± 50 ma Storage Temperature (T STG ) 65 C to C Junction Temperature (T J ) PDIP 140 C DC Electrical Characteristics for AC Recommended Operating Conditio Supply Voltage (V CC ) AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V I ) 0V to V CC Output Voltage (V O ) 0V to V CC Operating Temperature (T A ) 40 C to + 85 C Minimum Input Edge Rate ( V/ t) AC Devices V IN from 30% to 70% of V CC V 3.3V, 4.5V, 5.5V 125 mv/ Minimum Input Edge Rate ( V/ t) ACT Devices V IN from 0.8V to 2.0V V 4.5V, 5.5V 125 mv/ Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specificatio should be met, without exception, to eure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specificatio. 74AC821 74ACT821 Symbol Parameter Units Conditio (V) Typ Guaranteed Limits V IH Minimum HIGH Level V OUT = 0.1V Input Voltage V or V CC 0.1V V IL Maximum LOW Level V OUT = 0.1V Input Voltage V or V CC 0.1V V OH Minimum HIGH Level Output Voltage V I OUT = 50 µa V IN = V IL or V IH I OH = 12 ma V I OH = 24 ma I OH = 24 ma (Note 2) V OL Maximum LOW Level Output Voltage V I OUT = 50 µa V IN = V IL or V IH I OL = 12 ma V I OL = 24 ma I OL = 24 ma (Note 2) I IN (Note 4) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µa V I = V CC, GND I OZ Maximum 3-STATE Current V I (OE) = V IL, V IH 5.5 ±0.5 ±5.0 µa V I = V CC, GND V O = V CC, GND I OLD Minimum Dynamic ma V OLD = 1.65V Max I OHD Output Current (Note 3) ma V OHD = 3.85V Min I CC (Note 4) Maximum Quiescent Supply Current µa V IN = V CC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: I IN and I 3.0V are guaranteed to be less than or equal to the respective 5.5V V CC. 3

4 74AC821 74ACT821 DC Electrical Characteristics for ACT Symbol Parameter Units Conditio (V) Typ Guaranteed Limits V IH Minimum HIGH Level V OUT = 0.1V V Input Voltage or V CC 0.1V V IL Maximum LOW Level V OUT = 0.1V V Input Voltage or V CC 0.1V V OH Minimum HIGH Level Output Voltage V I OUT = 50 µa V IN = V IL or V IH V I OH = 24 ma I OH = 24 ma (Note 5) V OL Maximum LOW Level Output Voltage V I OUT = 50 µa V IN = V IL or V IH V I OL = 24 ma I OL = 24 ma (Note 5) I IN Maximum Input (Note 4) Leakage Current 5.5 ±0.1 ±1.0 µa V I = V CC, GND I OZ Maximum 3-STATE V I = V IL, V IH 5.5 ±0.5 ±5.0 µa Current V O = V CC, GND I CCT Maximum I CC /Input ma V I = V CC 2.1V I OLD Minimum Dynamic ma V OLD = 1.65V Max I OHD Output Current (Note 6) ma V OHD = 3.85V Min I CC Maximum Quiescent V IN = V CC µa Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol Parameter (V) C L = 50 pf C L = 50 pf Units (Note 7) Min Typ Max Min Max f MAX Maximum Clock Frequency MHz t PLH Propagation Delay CP to O n t PHL Propagation Delay CP to O n t PZH Output Enable Time OE to O n t PZL Output Enable Time OE to O n t PHZ Output Disable Time OE to O n t PLZ Output Disable Time OE to O n Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V 4

5 AC Operating Requirements for AC Symbol Parameter (V) C L = 50 pf C L = 50 pf Units (Note 8) Typ Guaranteed Minimum t S Setup Time, HIGH or LOW D n to CP t H Hold Time, HIGH or LOW D n to CP t W CP Pulse Width HIGH or LOW Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V 74AC821 74ACT821 AC Electrical Characteristics for ACT Symbol Parameter (V) C L = 50 pf C L = 50 pf Units (Note 9) Min Typ Max Min Max f MAX Maximum Clock Frequency t PLH Propagation Delay CP to O n t PHL Propagation Delay CP to O n t PZH Output Enable Time OE to O n t PZL Output Enable Time OE to O n t PHZ Output Disable Time OE to O n t PLZ Output Disable Time OE to O n Note 9: Voltage Range 5.0 is 5.0V ± 0.5V MHz AC Operating Requirements for ACT Symbol Parameter (V) C L = 50 pf C L = 50 pf Units t S Setup Time, HIGH or LOW D n to CP t H Hold Time, HIGH or LOW D n to CP t W CP Pulse Width HIGH or LOW Note 10: Voltage Range 5.0 is 5.0V ± 0.5V (Note 10) Typ Guaranteed Minimum Capacitance Symbol Parameter Typ Units Conditio C IN Input Capacitance 4.5 pf V CC = OPEN C PD Power Dissipation Capacitance 35.0 pf V CC = 5.0V 5

6 74AC821 74ACT821 Physical Dimeio inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, Wide Package Number M24B 6

7 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 74AC821 74ACT Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 7

8 74AC821 74ACT Bit D-Type Flip-Flop with 3-STATE Outputs Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Package Number N24C Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

9 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Fairchild Semiconductor: 74AC821SC 74AC821SPC 74AC821SCX

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